Separated By Insulator (i.e., Floating Gate) Patents (Class 438/593)
  • Patent number: 10510764
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Ryota Katsumata, Toru Matsuda, Yu Hirotsu, Naoki Yamamoto
  • Patent number: 10319787
    Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 11, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Haruhiko Terada
  • Patent number: 10103235
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Ming Pan, Chiang-Ming Chuang, Pei-Chi Ho, Ping-Pang Hsieh
  • Patent number: 9997365
    Abstract: A method of manufacturing a semiconductor device includes: loading a substrate into a process container after dry-etching a portion of a silicon film formed in a recess on the substrate; performing etching to partially or entirely remove the silicon film remaining on a side wall inside the recess by supplying an etching gas selected from a hydrogen bromide gas and a hydrogen iodide gas into the process container of a vacuum atmosphere while heating the substrate; subsequently forming a silicon film inside the recess; and heating the substrate to increase a grain size of the silicon film.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 12, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Mitsuhiro Okada
  • Patent number: 9786677
    Abstract: A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: October 10, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Antoine Khoueir, Frank R Dropps
  • Patent number: 9666680
    Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 30, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Hsiang Chang, Shen-De Wang, Chih-Chien Chang, Jianjun Yang, Aaron Chen
  • Patent number: 9397228
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Ming Wu, Wei-Hang Huang, Shih-Chang Liu
  • Patent number: 9368588
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 14, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Kuo Tung Chang, Chun Chen, Shenqing Fang
  • Patent number: 9356059
    Abstract: A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 9153459
    Abstract: According to embodiments, there is provided a manufacturing method of a semiconductor device includes forming a semiconductor thin film on a substrate; processing the thin film to a predetermined shape; executing an ion implantation process on the thin film processed to the predetermined shape; executing an anneal treatment on the thin film on which the ion implantation process has been executed to create a resistor element; and adjusting both or any one of a process condition of the ion implantation process and a treatment condition of the anneal treatment based on at least any one of a film forming condition and a film formation result of the forming and a film process result of the processing.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Kyuho
  • Patent number: 9105740
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 11, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Helmut Puchner, Igor Polishchuk, Sagy Charel Levy
  • Publication number: 20150145017
    Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a substrate can be provided. The substrate can have a plurality of isolation structures. A top surface of the plurality of isolation structures can be higher than a surface of the substrate. A device layer can be formed on the substrate and on the plurality of isolation structures. The device layer can be polished using a polishing process, such that the top surface of the plurality of isolation structures are exposed, with residue remaining on the device layer and on the plurality of isolation structures. The residue can be removed from the device layer and from the plurality of isolation structures using a non-polishing-removal process, such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially leveled and smooth.
    Type: Application
    Filed: July 24, 2014
    Publication date: May 28, 2015
    Inventors: XINPENG WANG, XIANJIE NING
  • Patent number: 9041088
    Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
  • Patent number: 9034698
    Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Ozu, Shota Yoshimura, Hiroto Ohtake, Kosuke Kariu, Takashi Tsukamoto
  • Patent number: 9029215
    Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Gordon M. Grivna, Duane B. Barber, Peter McGrath, Balaji Padmanabhan, Prasad Venkatraman
  • Publication number: 20150123186
    Abstract: A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 7, 2015
    Inventors: Chaw-Sing Ho, Reynaldo Villavelez, Xin Ping Cao
  • Patent number: 9024289
    Abstract: Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Dae Ho Rho, Jeong Tae Kim, Hyun Kyu Kim
  • Patent number: 9012972
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisakazu Matsumori, Hideto Takekida, Akira Mino, Jun Murakami
  • Patent number: 9012320
    Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Kil-Su Jeong, Hansoo Kim, Youngwoo Park
  • Publication number: 20150102398
    Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Henderikus Albert Van der Vegt, Guido Jozef Maria Dormans, Johan Dick Boter, Guoqiao Tao
  • Patent number: 9006093
    Abstract: A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: April 14, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang, Jane A. Yater
  • Patent number: 8999833
    Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Shih-Chang Liu, Chia-Shiung Tsai
  • Publication number: 20150093864
    Abstract: A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: ASANGA H. PERERA
  • Patent number: 8987087
    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 24, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Henry Chien, Donovan Lee, Vinod R. Purayath, Yuan Zhang, James K. Kai, George Matamis
  • Publication number: 20150069493
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor layer; a first insulating film provided on the semiconductor layer; a floating gate layer provided on the first insulating film; a second insulating film provided on the floating gate layer; and a gate electrode provided on the second insulating film, the first insulating film including silicon, oxygen, and carbon. Concentration of the carbon in a direction from the semiconductor layer side toward the floating gate layer side has a maximum between the semiconductor layer and the floating gate layer, and the maximum being located nearer to the semiconductor layer side than to the floating gate layer side.
    Type: Application
    Filed: January 29, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi MURAKOSHI, Keiichi Sawa
  • Publication number: 20150069490
    Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Inventors: Jane A. Yater, Cheong Min Hong, Sung-Taeg Kang
  • Publication number: 20150072514
    Abstract: A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 12, 2015
    Inventors: Tatsuya FUKUMURA, Yoshihiro IKEDA, Shunichi NARUMI, Izumi TAKESUE
  • Patent number: 8975114
    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8975131
    Abstract: A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 10, 2015
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Nhan Do, Vipin Tiwari, Hieu Van Tran, Xian Liu
  • Patent number: 8975164
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: March 10, 2015
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Wei-Ya Wang, Li-Feng Teng
  • Publication number: 20150060981
    Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.
    Type: Application
    Filed: October 2, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20150060982
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.
    Type: Application
    Filed: January 13, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi ITOKAWA
  • Patent number: 8956950
    Abstract: A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a subsequent process of forming a mask pattern and where the filling layer formed to have a lower height than the plurality of patterns, between the plurality of patterns, forming a mask layer on the entire structure where the filling layer is formed, and forming the mask pattern by removing some of the mask layer so that some of the plurality of patterns is removed.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Min Gyu Koo
  • Patent number: 8952439
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate on which an element isolation groove is formed, memory cells each including a gate electrode having a charge storage layer, an interelectrode insulating film, and a control electrode, that is formed on the semiconductor substrate via a tunnel insulating film, and an insulating film disposed in the element isolation groove. The interelectrode insulating film is formed to have a first portion above the insulating film that is separated from one of the insulating film and the control electrode by an air gap and a second portion above the charge storage layer that is separated from the charge storage layer by a cavity.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryota Suzuki
  • Patent number: 8951861
    Abstract: Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 10, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Maitreyee Mahajani
  • Publication number: 20150036437
    Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: Qualcomm Incorporated
    Inventors: Xia Li, Bin Yang, Zhongze Wang
  • Publication number: 20150035040
    Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Inventors: Jong-Won Yoo, Alexander Kotov, Yuri Tkachev, Chien-Sheng Su
  • Publication number: 20150028409
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions arranged each via a space in a direction crossing a first direction; a plurality of control gate electrodes; and a select gate electrode extending in a second direction, and the select gate electrode aligned with a control gate electrode located on an outermost side out of the plurality of control gate electrodes via the space; a first insulating layer covering the plurality of control gate electrodes and the select gate electrode, the first insulating layer provided on a side wall of the select gate electrode via the space, and a portion of the first insulating layer bridged between adjacent ones of the plurality of control gate electrodes protruding toward the space between adjacent ones of the plurality of control gate electrodes.
    Type: Application
    Filed: January 7, 2014
    Publication date: January 29, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuhito KUGE
  • Patent number: 8940603
    Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 27, 2015
    Assignee: Infineon Technologies AG
    Inventors: Georg Tempel, Ernst-Otto Andersen, Achim Gratz
  • Patent number: 8936984
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventor: Joo Hee Han
  • Publication number: 20150014762
    Abstract: A semiconductor storage device is disclosed. The semiconductor device includes a semiconductor substrate; and a gate electrode disposed above the semiconductor substrate. The gate electrode includes a conductive film, a metal film, and a first insulating film. In a cross sectional view of the gate electrode, at least the metal film includes a receding portion receding in a lateral direction as compared to the first insulating film, and wherein a second insulating film is disposed in the receding portion and contacts sidewalls of the metal film.
    Type: Application
    Filed: February 11, 2014
    Publication date: January 15, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryota OHNUKI
  • Patent number: 8933449
    Abstract: Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8932948
    Abstract: A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 13, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventors: Jongsun Sel, Tuan Pham, Ming Tian
  • Patent number: 8927353
    Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 8921913
    Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Hsu, Zhaobing Li, Chi Ren, Ching-Long Tsai, Wei Cheng
  • Patent number: 8921219
    Abstract: A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: December 30, 2014
    Assignee: STMicroelectronics (Roesset) SAS
    Inventor: Philippe Boivin
  • Publication number: 20140377945
    Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Cheng-Yuan Hsu, ZHAOBING LI, CHI REN, Ching-Long Tsai, Wei Cheng
  • Publication number: 20140374811
    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control region.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Christopher J. Larsen, David A. Daycock, Kunal Shrotri
  • Publication number: 20140363963
    Abstract: In one embodiment, a method includes forming workpiece, first and second films on a substrate, processing the second films to form first and second core patterns, forming third and fourth sidewall patterns on side surfaces of the first and second core patterns via first and second sidewall patterns, and removing the first core patterns and first sidewall patterns so that the second core pattern and second to fourth sidewall patterns remain. The method includes processing the first films by transferring the second core pattern and second to fourth sidewall patterns to form third and fourth core patterns, forming fifth and sixth sidewall patterns on side surfaces of the third and fourth core patterns, removing the third core patterns so that the fourth core pattern and fifth and sixth sidewall patterns remain, and processing the workpiece film by transferring the fourth core pattern and fifth and sixth sidewall patterns.
    Type: Application
    Filed: August 29, 2013
    Publication date: December 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Masahiro KIYOTOSHI
  • Patent number: 8906762
    Abstract: Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 9, 2014
    Assignee: Sandisk Technologies, Inc.
    Inventor: Kenji Sato