Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

Abstract: Disclosed are semiconductor device fabricating method and semiconductor device fabricated by the same. The method includes forming on a lower mask layer first upper mask patterns and sacrificial spacers that cover sidewalls of the first upper mask patterns, forming first holes in the lower mask layer below the first upper mask patterns, forming second holes in the lower mask layer not covered by the first upper mask patterns and the sacrificial spacers, forming second upper mask patterns filling a space between the sacrificial spacers on the lower mask layer and also forming sacrificial patterns filling the first and second holes, removing the sacrificial spacers, using the first and second upper mask patterns to etch the lower mask layer, and removing the sacrificial patterns.

Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Abstract: A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a to-be-etched layer including a first region; forming a first pattern material layer on the to-be-etched layer; forming a sacrificial layer on the first pattern material layer; forming a first opening in the sacrificial layer over the first region, where the first opening exposes a first portion of the first pattern material layer; forming a first doped region in the first pattern material layer using the sacrificial layer as a mask; forming a second opening in the sacrificial layer over the first region, where the second opening exposes a second portion of the first pattern material layer; and forming a second doped region in the first pattern material layer using the sacrificial layer as a mask, where the second doped region is connected with the first doped region.

Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Abstract: A semiconductor device according to an embodiment includes a first dielectric film wall configured to separate one elliptic cylinder region into two regions in a long diameter direction of an ellipse, a first memory film disposed in a tubular shape along a sidewall surface of one region of the two regions, a second memory film disposed in a tubular shape along a sidewall surface of another region of the two regions, first wire groups connected to the first memory film, second wire groups provided in the same layers as the first wire groups and parallel to the first wire groups, and connected to the second memory film, and a second dielectric film wall formed integrally with the first dielectric film wall and separating the plurality of layers of the first wire groups and the plurality of layers of the second wire groups.

Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

Abstract: A method of manufacturing a semiconductor device includes: loading a substrate into a process container after dry-etching a portion of a silicon film formed in a recess on the substrate; performing etching to partially or entirely remove the silicon film remaining on a side wall inside the recess by supplying an etching gas selected from a hydrogen bromide gas and a hydrogen iodide gas into the process container of a vacuum atmosphere while heating the substrate; subsequently forming a silicon film inside the recess; and heating the substrate to increase a grain size of the silicon film.

Abstract: A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed.

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.

Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.

Abstract: A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.

Abstract: According to embodiments, there is provided a manufacturing method of a semiconductor device includes forming a semiconductor thin film on a substrate; processing the thin film to a predetermined shape; executing an ion implantation process on the thin film processed to the predetermined shape; executing an anneal treatment on the thin film on which the ion implantation process has been executed to create a resistor element; and adjusting both or any one of a process condition of the ion implantation process and a treatment condition of the anneal treatment based on at least any one of a film forming condition and a film formation result of the forming and a film process result of the processing.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a substrate can be provided. The substrate can have a plurality of isolation structures. A top surface of the plurality of isolation structures can be higher than a surface of the substrate. A device layer can be formed on the substrate and on the plurality of isolation structures. The device layer can be polished using a polishing process, such that the top surface of the plurality of isolation structures are exposed, with residue remaining on the device layer and on the plurality of isolation structures. The residue can be removed from the device layer and from the plurality of isolation structures using a non-polishing-removal process, such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially leveled and smooth.

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.

Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Abstract: A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.

Abstract: Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part.

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.

Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.

Abstract: A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor layer; a first insulating film provided on the semiconductor layer; a floating gate layer provided on the first insulating film; a second insulating film provided on the floating gate layer; and a gate electrode provided on the second insulating film, the first insulating film including silicon, oxygen, and carbon. Concentration of the carbon in a direction from the semiconductor layer side toward the floating gate layer side has a maximum between the semiconductor layer and the floating gate layer, and the maximum being located nearer to the semiconductor layer side than to the floating gate layer side.

Abstract: A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.

Abstract: A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.

Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.

Abstract: A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a subsequent process of forming a mask pattern and where the filling layer formed to have a lower height than the plurality of patterns, between the plurality of patterns, forming a mask layer on the entire structure where the filling layer is formed, and forming the mask pattern by removing some of the mask layer so that some of the plurality of patterns is removed.

Abstract: Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate on which an element isolation groove is formed, memory cells each including a gate electrode having a charge storage layer, an interelectrode insulating film, and a control electrode, that is formed on the semiconductor substrate via a tunnel insulating film, and an insulating film disposed in the element isolation groove. The interelectrode insulating film is formed to have a first portion above the insulating film that is separated from one of the insulating film and the control electrode by an air gap and a second portion above the charge storage layer that is separated from the charge storage layer by a cavity.

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.