Possessing Plural Conductive Layers (e.g., Polycide) Patents (Class 438/592)
  • Patent number: 10418287
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, multiple trenches extending through the interlayer dielectric layer to the semiconductor substrate and having a first trench of a PMOS device and a second trench of an NMOS device, and a high-k dielectric layer on sidewalls and a bottom of the trenches. The method also includes forming a semiconductor layer filling the trenches, removing the semiconductor layer in the first trench, forming a PMOS work function adjustment layer in the first trench and a metal electrode layer on the PMOS work function adjustment layer in the first trench, removing the semiconductor layer in the second trench, and forming an NMOS work function adjustment layer in the second trench and a metal electrode layer on the NMOS work function adjustment layer in the second trench.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 17, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jiaqi Yang, Jie Zhao
  • Patent number: 10361281
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 23, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 10347492
    Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Johanes S. Swenberg, Wei Liu, Houda Graoui
  • Patent number: 10170332
    Abstract: A method and structure for protecting high-mobility materials from exposure to high temperature processes includes providing a substrate having at least one fin extending therefrom. The at least one fin includes a dummy channel and source/drain regions. A dummy gate stack is formed over the dummy channel. A first inter-layer dielectric (ILD) layer is formed on the substrate including the fin. The first ILD layer is planarized to expose the dummy gate stack. After planarizing the first ILD layer, the dummy gate stack and the dummy channel are removed to form a recess, and a high-mobility material channel region is formed in the recess. After forming the high-mobility material channel region, contact openings are formed within a second ILD layer overlying the source/drain regions, and a low Schottky barrier height (SBH) material is formed over the source/drain regions.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10141416
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
  • Patent number: 10135027
    Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 20, 2018
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 10115804
    Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 30, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Guilei Wang, Junfeng Li, Jinbiao Liu, Chao Zhao
  • Patent number: 9972697
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 15, 2018
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 9947756
    Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Li, Chih-Hao Chang, Sheng-Yu Chang, Jen-Hsiang Lu, Jyun-Yang Shen
  • Patent number: 9941387
    Abstract: A semiconductor device may include the following elements: a fin member including a first doped portion, a second doped portion, and a semiconductor portion positioned between the first doped portion and the second doped portion; a composite structure including a conductor and an insulator positioned between the conductor and the semiconductor portion in a first direction; a first spacer having a first dielectric constant and positioned close to the second doped portion; a second spacer having a second dielectric constant and positioned close to the first doped portion; and a third spacer having a third dielectric constant. The second spacer is positioned between the third spacer and the fin member in the first direction. The composite structure is positioned between the first spacer and the second spacer. The first dielectric constant is less than at least one of the second dielectric constant and the third dielectric constant.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: April 10, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Hai Yang Zhang, Zhe Zheng
  • Patent number: 9793513
    Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 17, 2017
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 9786668
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 9773800
    Abstract: The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Chen, Tzu-Ping Chen
  • Patent number: 9748234
    Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
  • Patent number: 9728409
    Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a stacked metal nitride film including a first metal nitride film and a second metal nitride film on a substrate by alternately performing steps (a) and (b) a plurality of times, wherein the step (a) includes alternately supplying: a first metal source containing a first halogen element and a metal element; and a nitrogen-containing source to the substrate a plurality of times to form the first metal nitride film, and the step (b) includes alternately supplying: a second metal source containing a second halogen element different from the first halogen element and the metal element; and the nitrogen-containing source to the substrate a plurality of times to form the second metal nitride film.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: August 8, 2017
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Harada, Kimihiko Nakatani, Hiroshi Ashihara
  • Patent number: 9716044
    Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Chi Chang, Chun-Li Lin, Kai-Shiung Hsu, Ming-Shiou Kuo, Wen-Long Lee, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 9634006
    Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
  • Patent number: 9583400
    Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 9548361
    Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 17, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 9490140
    Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Yong Go, Eun Young Lee, Jung Geun Jee, Eun Yeoung Choi, Jin Gyun Kim, Hun Hyeong Lim
  • Patent number: 9397009
    Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Patent number: 9385047
    Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 5, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Pushkar Ranade, Bruce McWilliams
  • Patent number: 9379012
    Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 9362419
    Abstract: A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance device, a conductive line arranged in a current direction is formed over an impurity region, and a resistance value of the resistance device is precisely adjusted by adjusting a level of a voltage applied to the conductive line. The variable resistance device includes a first impurity region formed in a substrate, a second impurity region formed in the substrate and arranged parallel to the first impurity region, a conductive line formed over the first impurity region, and electrode terminals formed at both longitudinal ends of the second impurity region to be coupled to the second impurity region.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 7, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hyung Jin Park
  • Patent number: 9349731
    Abstract: A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Je-Don Kim
  • Patent number: 9324707
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Patent number: 9312324
    Abstract: Embodiments of the invention provide an organic thin film transistor, an organic thin film transistor array substrate and a display device. The organic thin film transistor comprises a transparent substrate; source and drain electrodes formed on the transparent substrate; an active layer formed on the transparent substrate by an organic semiconductor material and disposed between the source and drain electrodes; a gate insulating layer formed on the active layer; a gate electrode formed on the gate insulating layer; and first and second banks disposed on the transparent substrate, inner sides of the first and second banks being covered by the source and drain electrodes, respectively.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 12, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ze Liu
  • Patent number: 9293337
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang
  • Patent number: 9281310
    Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 8, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Patent number: 9252273
    Abstract: A process for fabrication of semiconductor devices, particularly fin-shaped Field Effect Transistors (FinFETs), having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Hui Zang
  • Patent number: 9240483
    Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: June-hee Lee, Jae-yeol Song, Hye-Ian Lee, Hong-bae Park, Sang-jin Hyun
  • Patent number: 9236345
    Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 9230954
    Abstract: The present invention provides a LDNMOS device for an ESD protection structure, by means of disposing a metal portion above the isolation portion and overlapping thereof, so as to protect the internal device from ESD more completely, comprising: a substrate; an ILD; a deep N-well region; a P-body region; a doped region, the doped region defines a diffusion area on the top thereof; a Poly gate electrode; an isolation structure disposed between the Poly gate electrode and the doped region; a contact portion connecting to the diffusion area of the doped region; and a metal portion disposed above the doped region, connecting to the contact portion. Wherein there is an overlap between the isolation structure and the metal portion, the direction of the overlap is parallel to the direction of channel length.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 5, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Chi-Hong Wu
  • Patent number: 9209258
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Feng Zhou, Tien-Ying Luo, Haiting Wang, Padmaja Nagaiah, Jean-Baptiste Laloe, Isabelle Pauline Ferain, Yong Meng Lee
  • Patent number: 9202815
    Abstract: According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier is fluorine doped and a second surface region of the carrier is at least one of free from the fluorine doping or less fluorine doped than the first surface region; and oxidizing the carrier to grow a first gate oxide layer from the first surface region of the carrier with a first thickness and simultaneously from the second surface region of the carrier with a second thickness different from the first thickness.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 1, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Kerstin Kaemmer, Thomas Bertrams, Henning Feick, Olaf Storbeck, Matthias Schmeide
  • Patent number: 9196528
    Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin, Robert R. Robison
  • Patent number: 9190280
    Abstract: A method for manufacturing a semiconductor device including: preparing a semiconductor substrate with a gate oxide layer on the top thereof; depositing a polycrystalline silicon layer on the top of the semiconductor substrate; depositing a protection layer overlying the top of the polycrystalline silicon layer; etching the protection layer and the polycrystalline silicon layer to form a gate body block; forming an oxide layer overlying the gate body block and the semiconductor substrate; polishing the oxide layer through Chemical Mechanical Polishing (CMP) until the top of the gate body block; removing the protection layer on the top of the gate body block; and forming a metal silicide layer on the gate body block.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 17, 2015
    Assignees: PEKING UNIVERSITY FOUNDER GROUP CO., LTD., FOUNDER MICROELECTRONICS INTERNATIONAL CO., LTD.
    Inventor: Zhengfeng Wen
  • Patent number: 9153668
    Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Guan-Lin Chen, Ting-Hung Hsu, Jiun-Jia Huang
  • Patent number: 9147578
    Abstract: Embodiments provide methods for treating a metal silicide contact which includes positioning a substrate having an oxide layer disposed on a metal silicide contact surface within a processing chamber, cleaning the metal silicide contact surface to remove the oxide layer while forming a cleaned silicide contact surface during a cleaning process, and exposing the cleaned silicide contact surface to a silicon-containing compound to form a recovered silicide contact surface during a regeneration process. In some examples, the cleaning of the metal silicide contact surface includes cooling the substrate to an initial temperature of less than 65° C., forming reactive species from a gas mixture of ammonia and nitrogen trifluoride by igniting a plasma, exposing the oxide layer to the reactive species to form a thin film, and heating the substrate to about 100° C. or greater to remove the thin film from the substrate while forming the cleaned silicide contact surface.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: September 29, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinliang Lu, Chien-Teh Kao, Chiukin Steve Lai, Mei Chang
  • Patent number: 9129945
    Abstract: The invention provides a method of forming a film stack on a substrate, comprising depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer without depositing a tungsten nucleation layer on the tungsten nitride layer as a growth site for tungsten.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 8, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sang-Hyeob Lee, Sang Ho Yu, Wei Ti Lee, Seshadri Ganguli, Hyoung-Chan Ha, Hoon Kim
  • Patent number: 9123827
    Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 1, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Sven Beyer, Jan Hoentschel, Alexander Ebermann, Carsten Grass
  • Patent number: 9099439
    Abstract: A semiconductor device includes a substrate, an epi-layer, an etch stop layer, an interlayer dielectric (ILD) layer, a silicide layer cap and a contact plug. The substrate has a first portion and a second portion neighboring to the first portion. The etch stop layer is disposed on the second portion. The ILD layer is disposed on the etch stop layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the ILD layer.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Fu Chang, Jen-Pan Wang
  • Patent number: 9048236
    Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Jong-Mil Youn, Jong-Joon Park, Kwang-Yong Jang, Jun-Sun Hwang
  • Patent number: 9040405
    Abstract: A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tom Hasche, Sven Beyer, Gerhard Lembach, Alexander Ebermann
  • Publication number: 20150137273
    Abstract: A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan ZHANG, Xiuyu CAI, Hoon KIM
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 9034710
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 9034746
    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
  • Patent number: 9035397
    Abstract: A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Aileen Li, Jinghua Ni, David Han
  • Patent number: 9029255
    Abstract: A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: May 12, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Yu-Wei Liang, Hai-Han Hung, Pei-Chi Wu