Possessing Plural Conductive Layers (e.g., Polycide) Patents (Class 438/592)
  • Patent number: 11289569
    Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Chieh Chan, Chung-Hui Chen
  • Patent number: 11282938
    Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
  • Patent number: 11282837
    Abstract: A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below 1 nm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2 nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 22, 2022
    Assignee: IMEC vzw
    Inventors: Jacopo Franco, Hiroaki Arimura, Benjamin Kaczer
  • Patent number: 11251283
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Lun Jheng, Chao-Sheng Cheng
  • Patent number: 11242598
    Abstract: Methods of forming thin-film structures including metal carbide material, and structures and devices including the metal carbide material are disclosed. Exemplary structures include metal carbide material formed using two or more different processes (e.g., two or more different precursors), which enables tuning of various metal carbide material properties, including resistivity, current leakage, and work function.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 8, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Petri Raisanen, Michael Givens, Eric James Shero
  • Patent number: 11233134
    Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Wei Chu, Ding-Kang Shih, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 11152213
    Abstract: A method of forming a field effect transistor device is provided. The method includes forming a gate stack on a substrate, and forming a sidewall spacer on the gate stack. The method further includes forming a protective liner on the sidewall spacer, and forming a sacrificial gate cap on the gate stack. The method further includes forming a first dielectric fill layer on the protective liner, and forming a second dielectric fill layer on the first dielectric fill layer. The method further includes forming an opening in the second dielectric fill layer and the first dielectric fill layer that exposes the protective liner and sacrificial gate cap. The method further includes removing the sacrificial gate cap to form a cavity between the gate stack and the second dielectric fill layer, and removing the exposed sacrificial liner.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 11043573
    Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chi-Cheng Hung, Yu-Sheng Wang, Weng-Cheng Chen, Hao-Han Wei, Ming-Ching Chung, Chi-Cherng Jeng
  • Patent number: 11043576
    Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11024631
    Abstract: An integrated circuit device includes a static random access memory (SRAM) array, and the SRAM array includes first to fourth active fins extending parallel to each other in a first direction, a first gate line overlapping the second to fourth active fins, a second gate line spaced apart from the first gate line in the first direction and overlapping the first to third active fins, a third gate line spaced apart from the first gate line in the first direction and overlapping the fourth active fin, a fourth gate line spaced apart from the second gate line in the first direction and overlapping the first active fin, a first field isolation layer contacting one end of the second active fin, and a second field isolation layer contacting one end of the third active fin. The first to fourth gate lines extend in a second direction intersecting the first direction.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Cheol Jeong, Hag Ju Cho
  • Patent number: 10923573
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 10903112
    Abstract: A process of smoothing a top surface of a bit line metal of a memory structure decreases resistance of a bit line stack. The process includes depositing a titanium layer of approximately 30 angstroms to 50 angstroms on a polysilicon layer on a substrate, depositing a first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on the titanium layer, annealing the substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing a second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on the first titanium nitride layer after annealing, and depositing a bit line metal layer of ruthenium on the second titanium nitride layer.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: January 26, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, Jianxin Lei, Sanjay Natarajan, In Seok Hwang, Nobuyuki Sasaki
  • Patent number: 10872770
    Abstract: The present disclosure relates to a bridging asymmetric haloalkynyl dicobalt hexacarbonyl precursors, and ultra high purity versions thereof, methods of making, and methods of using these bridging asymmetric haloalkynyl dicobalt hexacarbonyl precursors in a vapor deposition process. One aspect of the disclosure relates to an ultrahigh purity bridging asymmetric haloalkynyl dicobalt hexacarbonyl precursor of the formula Co2(CO)6(R3C?CR4), where R3 and R4 are different organic moieties and R4 is more electronegative or more electron withdrawing compared to R3.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 22, 2020
    Assignee: Entegris, Inc.
    Inventors: Sangbum Han, Seobong Chang, Jaeeon Park, Bryan Clark Hendrix, Thomas H. Baum
  • Patent number: 10868011
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: December 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Patent number: 10854520
    Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Chun-Hsien Lin, Wei-Hao Huang, Kai-Teng Cheng
  • Patent number: 10811408
    Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation layer. A word line structure is in a trench formed in an upper portion of the substrate. The word line structure includes a gate insulation pattern covering an inner surface of the trench. A gate electrode pattern is on the gate insulation pattern. A first work function pattern is between the gate insulation pattern and the gate electrode pattern. A second work function pattern is on the first work function pattern and extends along a side surface of the gate electrode pattern. The first work function pattern has a top surface at a level below that of a bottom surface of the gate electrode pattern. The first work function pattern has a work function greater than that of the second work function pattern.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoungwon Seo, Wonsok Lee, Min Hee Cho, Hyun-Sook Byun
  • Patent number: 10790363
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Patent number: 10770360
    Abstract: A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 8, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10741560
    Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10566245
    Abstract: A method of fabricating a gate all around semiconductor device is provided.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Yong Kwon, Oh Seong Kwon
  • Patent number: 10535568
    Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han Tsao, Chii-Ming Wu, Cheng-Yuan Tsai, Yi-Huan Chen
  • Patent number: 10535552
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Patent number: 10522650
    Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Ching-Hwanq Su
  • Patent number: 10418287
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, multiple trenches extending through the interlayer dielectric layer to the semiconductor substrate and having a first trench of a PMOS device and a second trench of an NMOS device, and a high-k dielectric layer on sidewalls and a bottom of the trenches. The method also includes forming a semiconductor layer filling the trenches, removing the semiconductor layer in the first trench, forming a PMOS work function adjustment layer in the first trench and a metal electrode layer on the PMOS work function adjustment layer in the first trench, removing the semiconductor layer in the second trench, and forming an NMOS work function adjustment layer in the second trench and a metal electrode layer on the NMOS work function adjustment layer in the second trench.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 17, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jiaqi Yang, Jie Zhao
  • Patent number: 10361281
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 23, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 10347492
    Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Johanes S. Swenberg, Wei Liu, Houda Graoui
  • Patent number: 10170332
    Abstract: A method and structure for protecting high-mobility materials from exposure to high temperature processes includes providing a substrate having at least one fin extending therefrom. The at least one fin includes a dummy channel and source/drain regions. A dummy gate stack is formed over the dummy channel. A first inter-layer dielectric (ILD) layer is formed on the substrate including the fin. The first ILD layer is planarized to expose the dummy gate stack. After planarizing the first ILD layer, the dummy gate stack and the dummy channel are removed to form a recess, and a high-mobility material channel region is formed in the recess. After forming the high-mobility material channel region, contact openings are formed within a second ILD layer overlying the source/drain regions, and a low Schottky barrier height (SBH) material is formed over the source/drain regions.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10141416
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
  • Patent number: 10135027
    Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 20, 2018
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 10115804
    Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 30, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Guilei Wang, Junfeng Li, Jinbiao Liu, Chao Zhao
  • Patent number: 9972697
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 15, 2018
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 9947756
    Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Li, Chih-Hao Chang, Sheng-Yu Chang, Jen-Hsiang Lu, Jyun-Yang Shen
  • Patent number: 9941387
    Abstract: A semiconductor device may include the following elements: a fin member including a first doped portion, a second doped portion, and a semiconductor portion positioned between the first doped portion and the second doped portion; a composite structure including a conductor and an insulator positioned between the conductor and the semiconductor portion in a first direction; a first spacer having a first dielectric constant and positioned close to the second doped portion; a second spacer having a second dielectric constant and positioned close to the first doped portion; and a third spacer having a third dielectric constant. The second spacer is positioned between the third spacer and the fin member in the first direction. The composite structure is positioned between the first spacer and the second spacer. The first dielectric constant is less than at least one of the second dielectric constant and the third dielectric constant.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: April 10, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Hai Yang Zhang, Zhe Zheng
  • Patent number: 9793513
    Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 17, 2017
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 9786668
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 9773800
    Abstract: The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Chen, Tzu-Ping Chen
  • Patent number: 9748234
    Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
  • Patent number: 9728409
    Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a stacked metal nitride film including a first metal nitride film and a second metal nitride film on a substrate by alternately performing steps (a) and (b) a plurality of times, wherein the step (a) includes alternately supplying: a first metal source containing a first halogen element and a metal element; and a nitrogen-containing source to the substrate a plurality of times to form the first metal nitride film, and the step (b) includes alternately supplying: a second metal source containing a second halogen element different from the first halogen element and the metal element; and the nitrogen-containing source to the substrate a plurality of times to form the second metal nitride film.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: August 8, 2017
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Harada, Kimihiko Nakatani, Hiroshi Ashihara
  • Patent number: 9716044
    Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Chi Chang, Chun-Li Lin, Kai-Shiung Hsu, Ming-Shiou Kuo, Wen-Long Lee, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 9634006
    Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
  • Patent number: 9583400
    Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 9548361
    Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 17, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 9490140
    Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Yong Go, Eun Young Lee, Jung Geun Jee, Eun Yeoung Choi, Jin Gyun Kim, Hun Hyeong Lim
  • Patent number: 9397009
    Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Patent number: 9385047
    Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 5, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Pushkar Ranade, Bruce McWilliams
  • Patent number: 9379012
    Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 9362419
    Abstract: A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance device, a conductive line arranged in a current direction is formed over an impurity region, and a resistance value of the resistance device is precisely adjusted by adjusting a level of a voltage applied to the conductive line. The variable resistance device includes a first impurity region formed in a substrate, a second impurity region formed in the substrate and arranged parallel to the first impurity region, a conductive line formed over the first impurity region, and electrode terminals formed at both longitudinal ends of the second impurity region to be coupled to the second impurity region.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 7, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hyung Jin Park
  • Patent number: 9349731
    Abstract: A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Je-Don Kim
  • Patent number: 9324707
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Patent number: 9312324
    Abstract: Embodiments of the invention provide an organic thin film transistor, an organic thin film transistor array substrate and a display device. The organic thin film transistor comprises a transparent substrate; source and drain electrodes formed on the transparent substrate; an active layer formed on the transparent substrate by an organic semiconductor material and disposed between the source and drain electrodes; a gate insulating layer formed on the active layer; a gate electrode formed on the gate insulating layer; and first and second banks disposed on the transparent substrate, inner sides of the first and second banks being covered by the source and drain electrodes, respectively.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 12, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ze Liu