Abstract: A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: Disclosed is a method for fabricating a mold. The mold is used for protective caps which will be applied to a wafer. The method comprises the steps of fabricating first and second cooperating mold halves from a semiconductor material using lithography. The first half and second half, when brought together define mold cavities for the wafer scale protective caps.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory cell also includes a shallow trench isolation (STI) region having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. The memory cell further includes a second insulating layer formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region. Arrays, memory devices, and systems are further included in the scope of the present invention.

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract: Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.

Abstract: A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.

Abstract: Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract: A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory circuits. In one aspect, the protective mask is formed over a substantial area of the Peripheral region. In another aspect, the protective mask is formed over a substantial area of an active part of the peripheral region.

Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline-silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.

Abstract: Methods for fabricating improved floating gate memory cells are provided. A substrate and a first insulating layer are fabricated, where the first insulating layer is formed on the substrate. A shallow trench isolation (STI) region is fabricated having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. A second insulating layer is formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region.

Abstract: An EEPROM device having voltage limiting charge pumping circuitry includes charge pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer. A process for fabricating the device is also provided.

Abstract: A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respect to an edge of the gate electrode in a gate length direction to improve efficiency of electric charge injection into the memory function body. A storage state in the memory function body is found by detecting a amount of current between the source/drain regions, which current changes depending on the amount of the electric charge retained in the charge retention portion.

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: A method of forming a floating gate of a memory cell is provided. A substrate having at least a trench is provided. Next, a tunnel oxide layer is formed on a surface of the trench. Next, a conductive layer is filled in the trench. Next, two-step etching process is carried out to form a first floating gate and a second floating gate having a top corner with sharp edge over the sidewalls of the trench.

Abstract: A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

Abstract: Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.

Abstract: Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.

Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

Abstract: Disclosed is a method of forming a floating gate in a date flash memory device on which first and second polysilicon films are stacked. After the first polysilicon film is formed, a SiH4 gas is introduced to decompose SiH4 and SiO2 into Si and H2 and Si and O2. A N2 anneal process is then implemented so that the decomposed H2 gas and O2 gas react to a N2 gas and are then outgassed. Next, a SiH4 gas and a PH3 gas are introduced to form the second polysilicon film. A native oxide film within the interface of the first polysilicon film and the second polysilicon film is removed to improve characteristics of the data flash memory device.

Abstract: The invention includes a method of making a programmable memory device. At least one floating gate layer is formed over a semiconductor substrate. A dielectric material is formed over the at least one floating gate layer, and a mass consisting essentially of W is formed over the dielectric material. The mass has a pair of opposing sidewalls. A first layer is formed over the mass and along the sidewalls of the mass, and a second layer is formed over the first layer. The second layer extends over the mass and along the sidewalls of the mass, and has a different composition than the first layer. After the second layer is formed, the first and second layers are anisotropically etched to form sidewall spacers extending along the sidewalls of the mass.

Abstract: Methods of fabricating nonvolatile memory devices are disclosed. A disclosed method comprises forming a trench isolation layer on a substrate; forming an oxide layer and a polysilicon layer; forming a sacrificial layer on the polysilicon layer; forming a photoresist pattern on the sacrificial layer; performing an etching process using the photoresist pattern as a mask and, at the same time, attaching polymers on sidewalls of the etched sacrificial layer to form polymer layers, the polymers being generated from the etching of the sacrificial layer; and forming a floating gate and a tunnel oxide by removing part of the polysilicon layer and the oxide layer using the polymer layers and the photoresist pattern as a mask. The disclosed method can increase the width of a floating gate by using polymer layers in fabricating a two-bit type cell, thereby ensuring a higher coupling ratio compared to the coupling ratio of a conventional two-bit type cell.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.

Abstract: Heavily concentrated impurities are selectively introduced into an exposed region of an oxide film. The exposed region of the oxide film where the impurities are introduced is selectively etched so that a surface of the semiconductor substrate is exposed An oxidizing process is performed and a second oxide film is formed on the first oxide film and the exposed surface of the semiconductor substrate. A polysilicon layer is formed as the floating gate.

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).

Abstract: A metal oxide semiconductor (MOS) capacitor formed according to a process in which Fermi level enhanced oxidation is suppressed by the introduction of nitrogen impurities into an N-doped impurity region is formed to utilize the N-doped impurity region as a lower electrode and includes a capacitor dielectric having a reduced thickness with respect to other portions of the thermal oxide film formed over N-doped impurity regions. The capacitor is highly linear and includes a high capacitance density. The process used to form the capacitor includes thermally oxidizing a substrate such that an oxide film is formed to include multiple thicknesses including an enhanced oxide growth rate producing an oxide film of increased thickness in N-doped impurity regions and a section within nitrogen-doped impurity portions of the N-doped impurity region in which the enhanced oxidation growth is suppressed and the film formed in this region includes a desirably reduced thickness.

Abstract: A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.

Abstract: A memory device may include a semiconductor substrate, an oxide layer defining spaced apart active areas in the semiconductor substrate, and a floating gate region on each respective active area. The floating gate region may have sidewalls that are slanted with respect to a surface of the semiconductor substrate. Moreover, the memory device may also include a plug in the oxide layer.

Abstract: A method for forming a floating gate electrode within a split gate field effect transistor device provides for isotropically processing a blanket isotropically processable material layer having a patterned mask layer formed thereover to form a patterned isotropically processed material layer which encroaches beneath the patterned mask layer. The patterned isotropically processed material layer may then be employed as a mask for forming a floating gate electrode from a blanket floating gate electrode material layer. The method provides for forming adjacent floating gate electrodes with less than minimally photolithographically resolvable separation.

Abstract: An object of the present invention is to provide a semiconductor apparatus and a method of manufacturing the same, in which dispersion of a threshold voltage Vth of a transistor at every transistor is reduced to remove generation of fixed charges in a gate insulation film and a surface level to stabilize the operation of the semiconductor apparatus. A semiconductor apparatus having a MIS transistor (1), wherein a gate electrode (4) of said MIS transistor (1), which mainly contributes to the operation of a circuit, is continuously formed to a position above a bypass film (8) made of an insulation film through which a leak current is able to easily flow as compared with a gate insulation film (7) of said MIS transistor (1) under the same voltage.

Abstract: The present invention generally relates to provide a fabrication method of a flash memory with L-shaped floating gate. The present invention utilizes a dielectric spacer on a surface of a semiconductor substrate to form a L-shaped poly spacer, which is so called the L-shaped floating gate. The respective inside portion of L-shaped floating gate is gibbous and to form a tip structure. Then, an isolating dielectric layer and a control gate are formed thereon. The control gate is covering the gibbous tip structure of the L-shaped floating gate to complete a flash memory device. The present invention is provided with a channel length, which is stably and easily controlled, and a tip structure for point discharging. Hence, the present invention can enhance the isolating effect between the control gate and the floating gate to achieve the purpose of repeating control the fabrication of the semiconductor devices.

Abstract: In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.

Abstract: Resist residues, which is formed in a process of forming Al interconnections, are removed through use of a single chemical. A chemical which contains an organic acid or a salt thereof and water and which has a pH below 8 is used as a treatment for removing resist or resist residues. The chemical may be used in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching of an Al interconnection; in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching a hole reaching an Al interconnection in an dielectric layer; in a process in which Cu is exposed on the surface of a semiconductor wafer after dry-etching of a Cu interconnection or etching of an interlayer dielectric film laid on a Cu interconnection; and in a process in which metal material such as W, WN, Ti, or TiN; poly-Si; SiN; and SiO2 are exposed on the surface of a wafer after etching of a metal gate.

Abstract: A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second interconnect are configured on a semiconductor substrate. A conductive silicon is formed between the first interconnect and the second interconnect. The conductive silicon is anodically etched in a hydrofluoric-acid-containing electrolyte to convert the conductive silicon into porous silicon. The porous silicon is subsequently oxidized to form porous silicon oxide. With a dielectric constant of between 1.1 and 4, the porous silicon oxide has a lower dielectric constant than customary silicon oxide with 4.

Abstract: The density of a deposited silicon nitride layer is increased by laser thermal annealing in N2, thereby increasing etch selectivity with respect to an overlying oxide and, hence, avoiding damage to underlying silicide layers and gates. Embodiments include laser thermal annealing a silicon nitride layer deposited as an etch stop layer, e.g., in fabricating EEPROMs, to increase its density by up to about 8%, thereby increasing its etch selectivity with respect to an overlying BPSG layer to about {fraction (1/12)} to about {fraction (1/14)}.

Abstract: A method for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The new method produces significantly larger tunneling currents for a given voltage than attained in prior work. The new method is advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs). These FLOTOX transistors are candidates for replacing the low power operation transistors found in DRAMs.

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers.

Abstract: The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed on the pad oxide layer. A masking layer, the pad oxide layer and the semiconductor substrate are patterned to form a trench therein. A gap-filling material is refilled into the trench and over the semiconductor substrate. A portion of the gap-filling material is removed to an upper surface of the masking layer. Next step is to remove the masking layer. A first conductive layer is formed along the surface of the substrate, then removing a portion of the first conductive layer to expose an upper surface of the gap-filling material. An inter polysilicon dielectric layer is formed on the first conductive layer and a second conductive layer is formed on the inter polysilicon dielectric layer.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: There is disclosed a flash memory cell and method of manufacturing the same, in which the circular hole is formed in the insulating film formed on the silicon substrate, the floating gate having a cylindrical shape is formed within the hole and the control gate is formed within the floating gate. Therefore, the source used as a current supply and the silicon substrate may be formed integratedly, and also the process of forming a device separation film can be omitted, thus allowing manufacturing an ultra high integration nonvolatile memory device.

Abstract: A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.