Abstract: Gate electrodes in an inverter section and a transfer section are formed only on element areas, and connected to each other by means of local interconnection layers. As a result, a memory cell of a very small size but a large capacity can be formed without considering a gate fringe or shortening phenomenon problem.

Abstract: A method of manufacturing a semiconductor device having the memory region which has a MONOS type memory cell and a logic circuit region which has a peripheral circuit, including the following steps. A stopper layer and a predetermined region of a first conductive layer within the memory region are patterned, but a stopper layer and a first conductive layer within the logic circuit region are not pattered. Side-wall shaped control gates are formed at least on both sides of the first conductive layer within the memory region with an ONO film interposed. The first conductive layer within the logic circuit region is patterned to form a gate electrode of a MOS transistor. Surfaces of gate electrodes and source or drain regions of the non-volatile memory device and the MOS transistor are silicided. After a second insulating layer is formed, the second insulating layer is polished so that the stopper layer within the memory region is exposed and the gate electrode within the logic circuit region is not exposed.

Abstract: Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

Abstract: The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and a second dielectric are formed in order on the surface of a semiconductor substrate. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around projective sides of the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. Subsequently, the first dielectric is removed. A poly spacer is thus completed. The poly spacer is used as a floating gate to complete a flash memory. A channel length of stability and easy control and tips useful for point discharge can thus be obtained so that repetitive control of fabrication of semiconductor devices can be achieved.

Abstract: A floating gate with sharp corner is disclosed. Wherein the sharp level of the sharp corners is control by the deposition thickness of the conductive spacers. The method comprises forming a first dielectric layer on the semiconductor substrate as a gate dielectric. A first conductive layer is formed on the first dielectric layer, and a second dielectric layer is then formed thereon. The second dielectric layer and the first conductive layer are next patterned. Subsequently, conductive spacers with sharp corners are created by well know anisotropical etching. A tunneling dielectric layer is then formed on the surface of a floating gate consisting of the spacers and patterned structure. A second conductive layer is formed on the tunneling dielectric layer as a control gate.

Abstract: A semiconductor device having reduced interconnect delay and increased interconnect reliability and a method of manufacturing the same are provided. A plurality of interconnects 12a through 12f are formed on a base insulating layer 10 with different interconnect pitches P1 through P3. Next, an adhesion inhibiting layer inhibiting adhesion to an interlayer insulating layer 16 formed on the interconnects is formed in the space between adjacent interconnects of a smaller interconnect pitch in which space the interconnect delay is predicted to exceed a predetermined value due to interconnect design. In a formed semiconductor device 18, gaps of a small dielectric constant are formed in the spaces between interconnects of the smaller interconnect pitches (parts C), while an insulating film is buried selectively in the spaces between interconnects of the larger interconnect pitches (parts A and B).

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of silicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: A method of forming an electrically erasable non-volatile memory cell array. Each memory cell includes a floating gate, a block of insulation material over the floating gate, and a control gate disposed laterally adjacent to and over the floating gate. The insulation material block is formed with a planarized upper surface (using a dummy poly layer as a planarization etch stop). The control gate is formed with a planarized upper surface (using the insulation material block upper surface as a planarization etch stop).

Abstract: An exemplary embodiment relates to a method of finFET patterning. The method can include patterning a fin structure above a substrate, forming amorphous carbon spacers along lateral sidewalls of the fin structure, depositing an oxide layer and polishing the oxide layer to expose top portions of the fin structure and the amorphous carbon spacers, removing amorphous carbon spacers, and depositing polysilicon where the amorphous carbon spacers were located.

Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0≦y<1.

Abstract: A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, VT. Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired VT into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.

Abstract: A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.

Abstract: A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers.

Abstract: A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and an oxide layer are deposited in order on all areas. Subsequently, an etched-back using the nitride layer a stopping layer is achieved. After that the nitride layer is removed thereby, forming a gate hollow region. After the pad oxide layer is removed, an oxynitride layer is regrown to be as the gate oxide. Thereafter, a silicon is deposited on all areas and refills in the gate hollow region. A planarization process is again performed using the oxide layer as an etch-stopping layer. Subsequently, the oxide layer is removed. S/D/G ion implanted into the polysilicon layer and the silicon layer. Then, the nitride spacers are removed to form dual recessed spaces.

Abstract: A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.

Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

Abstract: A process for fabricating a flash memory cell with increased floating gate to control gate overlap, has been developed. The process features forming the active device region of the flash memory cell in a narrow space of a semiconductor substrate, located between STI regions. The increased overlap is achieved via formation of a floating gate structure comprised with vertical conductive spacers, extending upwards from the periphery of an underlying floating gate base structure. Novel process sequences are used to simultaneously form the vertical conductive spacers and the floating gate base structure.

Abstract: A method for fabricating a MOSFET device using a dual salicide formation procedure has been developed. The process features a first salicide formation procedure used to create a thick metal silicide component for a composite gate structure, with the composite gate structure in turn comprised with the overlying thick metal silicide shape, on an underlying polysilicon shape. The first salicide formation procedure also results in the formation of metal silicide protrusions, extending from the edges of the composite gate structure, overlying adjacent portions of an insulator layer. A novel feature of this invention is the use of the metal silicide protrusions as an etch mask, allowing definition of insulator spacers on the sides of the composite gate structure, to be defined from the underlying insulator layer. A second salicide formation procedure is subsequently employed to form a thin metal silicide layer only on a heavily doped source/drain region.

Abstract: A semiconductor device and a fabrication method thereof that can improve performance and reliability by restricting the generation of a hot carrier effect is disclosed. Such a semiconductor device includes: a semiconductor substrate; a gate insulating layer formed on the semiconductor substrate; a-gate structure including a first gate electrode formed on the gate insulating layer and a second gate electrode formed on the first gate electrode; and conductive structures, e.g., sidewall spacers formed at the sides of the gate, electrically insulated from the first gate electrode, and electrically connected to the second gate electrode. Such a method for fabricating the semiconductor device includes: sequentially forming a gate insulating layer, a first gate electrode and a second gate electrode on a semiconductor substrate; re-oxidizing the gate insulating layer; and forming conductive spacers at the sides, respectively, of the first gate electrode and the second gate electrode.

Abstract: A method of eliminating weakness caused by high-density plasma (HDP) dielectric layer is provided. Before forming the HDP dielectric layer, a hot thermal oxide (HTO) layer is previously formed on the semiconductor substrate to serve as a buffer layer. The HTO layer eliminates the defect between the HDP dielectric layer and a cap nitride layer and releases the stress therebetween, and thereby preventing bit line leakage issue.

Abstract: A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Abstract: A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.

Abstract: Disclosed is a method for forming a gate electrode of a semiconductor device, the method comprises the steps of: stacking a gate oxide film, a doped first silicon film, a diffusion preventing film, a metal film having a high melting point and a mask insulating film on a semiconductor substrate; forming a gate electrode by patterning a resultant stack structure; forming a second silicon film on an entire surface of a resultant structure; forming an oxidation preventing film on an entire surface of a resultant structure; forming a spacer on a side wall of the gate electrode by anisotrophically etching the oxidation preventing film and the second silicon film; and forming a gate reoxide film on the semiconductor substrate by oxidizing the semiconductor substrate.

Abstract: The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the claimed invention relates to a method of fabricating the semiconductor device in which parts of a gate electrode at the ends of a channel are lightly doped compared to the center part of the gate electrode, thereby eliminating a hump on a subthreshold current slope. To achieve the objects of the claimed invention, there is provided a semiconductor device that includes a semiconductor substrate divided into an isolation region and an active region. A gate oxide film is formed on a first upper surface of the active region. A gate electrode is formed on a second upper surface of the gate oxide film, the gate electrode having a first part and a second part. The first part is more lightly doped with impurities than the second part. A channel is formed in an upper end of the active region proximate the gate electrode.

Abstract: The present invention includes forming a first oxide layer as a sacrificial dielectric layer on a semiconductor substrate. A nitride layer is formed on the sacrificial dielectric layer. Then, the sacrificial dielectric layer and the nitride layer are patterned to form an opening. Next, a second oxide layer is formed on the nitride layer and along a surface of the opening. Side wall spacers are created by etching. Then, a gate dielectric layer is formed on the exposed semiconductor substrate. A first polysilicon layer is deposited on the nitride layer. Subsequently, the first polysilicon layer is polished by CMP, followed by removing the nitride layer, the spacers and the sacrificial dielectric layer. A tunneling dielectric layer and a control gate are respectively formed on a surface of the floating gate.

Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

Abstract: A polycide gate structure and a method of forming the polycide gate. A substrate having a gate dielectric layer, a polysilicon layer, a silicide layer and an insulation layer thereon is provided. The polysilicon layer is above the gate dielectric layer, the silicide layer is above the polysilicon layer, and the insulation layer is above the silicide layer. A patterned photoresist layer is formed over the insulation layer. Using the photoresist layer as a mask, an anisotropic etching operation is carried out to remove the exposed insulation layer. Again using the photoresist layer as a mask, a first type of plasma is used to carry out a first anisotropic etching operation to remove the exposed silicide layer. A metallic oxide layer is formed on the sidewalls of the silicide layer by the oxidation of a portion of the retained silicide layer. Using the photoresist layer as a mask, a second type of plasma is used to carry out a second anisotropic etching operation to remove the exposed polysilicon layer.

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer.

Abstract: A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

Abstract: The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the present invention, in which the first conductive gate layer is etched to form a steep-gate structure or a taper-gate structure. The metal layer is encapsulated by a second masking dielectric layer formed on the top and a first dielectric spacer formed on both sides, no interaction would occur between the metal layer and the first conductive gate layer, a highly-conductive nature of the metal layer for gate interconnection can be preserved. A thick silicide layer is formed by a two-step self-aligned silicidation process and a conductive barrier-metal layer is formed to eliminate the interaction between the thick silicide layer and the first conductive gate layer, a highly conductive nature of the thick silicide layer for gate interconnection can be obtained.

Abstract: Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

Abstract: Integrated transistors and other semiconductor elements are formed on a substrate. Spacers are applied for the purpose of producing LDD regions. A layer of polysilicon is first deposited in full-surface coverage and then removed except for spacers remaining on gate structures. The layer of polysilicon is utilized for the purpose of producing further integrated components and, for this purpose, is covered by an auxiliary layer and the latter in turn by an auxiliary mask. During the etching of the polysilicon layer, the structures covered by the auxiliary mask are preserved and can be utilized for further integrated components. The etching which is necessary for removing the spacers is effected selectively such that remaining structures of the auxiliary layer and thus of the underlying layer of polysilicon are not attacked. The components produced in addition are preserved.

Abstract: A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the side walls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer (which is predominately coextensive with t

Abstract: Transistor and method for fabricating the same, which can form a channel length shorter than a lithography limit and adjust a substrate impurity concentration variably, the method including the steps of (1) depositing an insulating film on a semiconductor substrate and forming a trench to expose the semiconductor substrate, (2) forming two side gates at sides of the trench, (3) forming a main gate over the semiconductor substrate between the side gates, and (4) removing the insulating film, and using the main gate and the side gates as masks in forming source/drain impurity regions in the semiconductor substrate on sides of the side gates.

Abstract: The surface of a silicon substrate is sputter-etched so that silicon clusters sputtered out form a silicon film on a side wall spacer. Then, a metal film of cobalt, titanium or the like is built up on the entire surface. Thereafter, silicidizing process is carried out to form metal silicide layers on a diffusion layer and the side wall spacer. Then, an inter-layer insulation film 14 is formed and is photo-etched to provide the inter-layer insulation film with a contact hole 15 overlapping the side wall spacer.

Abstract: A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is formed. Then, the first spacer insulation layer is etched to cover the side walls of the gate electrode. A conductive spacer film is subsequently formed on the resultant structure and is over-etched to form a conductive spacer that covers the first spacer insulation layer. In this step, the gate electrode is partially consumed to make the top of the first spacer insulation layer higher than the gate electrode. Also, an upper portion of the first spacer insulation layer is not comparatively etched due to an etching selectivity. This structure avoids shorts between the conductive spacer and the gate electrode. A second spacer insulation layer is then formed on the conductive spacer.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

Abstract: A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon.

Abstract: A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors.

Abstract: A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide.

Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.