Ii-vi Compound Semiconductor Patents (Class 438/603)
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Patent number: 7071087Abstract: A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1?x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1?x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.Type: GrantFiled: June 3, 2004Date of Patent: July 4, 2006Assignee: Witty Mate CorporationInventors: Tsung-Hsi Yang, Chung-Liang Lee, Chu-Shou Yang, Guangli Luo, Wu-Ching Chou, Chun-Yen Chang, Tsung-Yeh Yang
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Patent number: 7045451Abstract: Methods of preparing Group IVA and Group VIA organometallic compounds, particularly Group IVA organometallic compounds, are provided. Such manufacturing methods employ an amine and/or phosphine catalyst in a transalkylation step and may be performed in a batch, semi-continuous or continuous manner.Type: GrantFiled: April 2, 2004Date of Patent: May 16, 2006Assignee: Rohm and Haas Electronic Materials LLCInventor: Deodatta Vinayak Shenai-Khatkhate
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Patent number: 7012016Abstract: The present invention provides a method for growing group-III nitride semiconductor heteroepitaxial structures on a silicon (111) substrate by using a coincidently matched multiple-layer buffer that can be grown on the Si(111) substrate. The coincidently matched multiple-layer buffer comprises a single-crystal silicon nitride (Si3N4) layer that is formed in a controlled manner by introducing reactive nitrogen plasma or ammonia to the Si(111) substrate at a suitably high temperature. Then, an AlN buffer layer or other group-III nitride buffer layer is grown epitaxially on the single-crystal silicon nitride layer. Thereafter, the GaN epitaxial layer or group-III semiconductor heteroepitaxial structure can be grown on the coincidently matched multiple-layer buffer.Type: GrantFiled: November 18, 2003Date of Patent: March 14, 2006Inventor: Shangjr Gwo
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Patent number: 6927155Abstract: In the process for producing low-defect semiconductor layers based on III-V nitride semiconductor material, a substrate (1) made from a material which is not based on III-V nitride semiconductors is provided, and then a mask layer (2) is applied to the substrate in order to form unmasked regions (2c) and masked regions (2a, 2b) on the substrate. Then, starting from the unmasked regions (2c) of the substrate (1), the III-V nitride semiconductor layer (3) is grown. To avoid the formation of stress-induced cracks during the cooling phase from the growth temperature to room temperature, the mask layer (2) is formed on the substrate (1) in such a manner that some of the masked regions (2b) are wide enough to prevent the III-V nitride semiconductor layer (3) from growing together over these wide masked regions (2b), whereas the III-V nitride semiconductor layer does grow together only over the other, narrow masked regions (2a).Type: GrantFiled: September 2, 2002Date of Patent: August 9, 2005Assignee: Osram Opto Semiconductors GmbHInventors: Hans-Juergen Lugauer, Stefan Bader
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Patent number: 6920167Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.Type: GrantFiled: September 18, 2003Date of Patent: July 19, 2005Assignee: Sony CorporationInventors: Nozomu Hoshi, Hiroki Nagasaki
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Patent number: 6893950Abstract: A process for the production of contacts for electrically operated II/VI semiconductor structures (for example laser diodes). The contact materials palladium and gold hitherto used in relation to electrically operated II/VI semiconductor lasers are distinguished by a relatively great, not purely ohmic specific contact resistance in relation to the II/VI cover layer. The consequentially necessary higher operating voltages result in the unnecessary generation of heat and thus substantially accelerate degradation of the entire laser structure. That effect causes a limitation in terms of the service life of II/VI semiconductor laser diodes. The invention permits the operation of semiconductor laser diodes with lower operating voltages. The II/VI semiconductor laser diodes produced with our invention are distinguished by a longer service life. That permits inter alia commercial use of semiconductor laser diodes in the blue-green spectral range.Type: GrantFiled: November 24, 2003Date of Patent: May 17, 2005Assignee: Technische Universitaet BerlinInventors: Matthias Strassburg, Oliver Schulz, Udo W. Pohl, Dieter Bimberg
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Patent number: 6861342Abstract: An underlayer made of a III-V semiconductor compound is formed on a given substrate, and a CrSb compound is epitaxially grown on the underlayer by means of MBE method to fabricate a zinc blend type CrSb compound.Type: GrantFiled: June 18, 2002Date of Patent: March 1, 2005Assignee: Tohoku UniversityInventors: Hideo Ohno, Fumihiro Matsukura
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Patent number: 6852614Abstract: A method of making a semiconductor comprises depositing a group II-group VI compound onto a substrate in the presence of nitrogen using sputtering to produce a nitrogen-doped semiconductor. This method can be used for making a photovoltaic cell using sputtering to apply a back contact layer of group II-group VI compound to a substrate in the presence of nitrogen, the back coating layer being doped with nitrogen. A semiconductor comprising a group II-group VI compound doped with nitrogen, and a photovoltaic cell comprising a substrate on which is deposited a layer of a group II-group VI compound doped with nitrogen, are also included.Type: GrantFiled: March 23, 2001Date of Patent: February 8, 2005Assignee: University of MaineInventors: Alvin D. Compaan, Kent J. Price, Xianda Ma, Konstantin Makhratchev
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Patent number: 6846686Abstract: A semiconductor light-emitting device, including a first substrate of a first conductivity type, a first bonding layer provided on the first substrate and consisting essentially of a GaP material of the first conductivity type, a second bonding layer provided on the first bonding layer, coincident with the first bonding layer in the planar direction of the crystal, having the first conductivity type, and consisting essentially of a material represented by a formula InxGayP, where 0?x, y?1, and x+y=1, and a light-emitting layer comprising a first cladding layer, an active layer, and a second cladding layer, which are successively provided on the second bonding layer, each of the active layer and first and second cladding layers consisting essentially of a material represented by a formula InxGayAlzP, where x+y+z=1, and 0?x, y, z?1.Type: GrantFiled: May 5, 2003Date of Patent: January 25, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Saeki, Hideto Sugawara, Yukio Watanabe, Tamotsu Jitosho
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Patent number: 6835660Abstract: In a method of manufacturing a semiconductor device of the invention, a substrate insulating film 102 is formed on a semiconductor substrate 100, a barrier layer 104 is formed on the substrate insulating film, an Al—Cu interconnection layer 106 is formed on the barrier layer by sputtering under a condition that the nitrogen concentration in the atmosphere in the sputtering deposition chamber is higher than 12 ppm but lower than 1000 ppm, and then an anti-reflective film 108 is formed on the Al—Cu interconnection layer.Type: GrantFiled: October 31, 2003Date of Patent: December 28, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Tetsuo Usami
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Publication number: 20040219726Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.Type: ApplicationFiled: May 26, 2004Publication date: November 4, 2004Applicant: AmberWave Systems CorporationInventor: Eugene A. Fitzgerald
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Patent number: 6784074Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.Type: GrantFiled: June 6, 2003Date of Patent: August 31, 2004Assignee: NSC-Nanosemiconductor GmbHInventors: Vitaly Shchukin, Nikolai Ledentsov
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Patent number: 6734033Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.Type: GrantFiled: June 10, 2003Date of Patent: May 11, 2004Assignee: Cree, Inc.Inventors: David Todd Emerson, Amber Christine Abare, Michael John Bergmann
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Patent number: 6727167Abstract: A method of making a transparent electrode for a light-emitting diode includes depositing metal on a top surface of a semiconductor structure, and defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal, the mask having at least one opening so that the first region is covered by the mask and a second region is aligned with the at least one opening in the mask. The method also includes removing metal aligned with the at least one opening in the mask in the second region to form the first electrode overlying the first region of the semiconductor structure and so as to reveal the top surface of the semiconductor structure in the second region.Type: GrantFiled: October 12, 2001Date of Patent: April 27, 2004Assignee: Emcore CorporationInventor: Mark Gottfried
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Patent number: 6693339Abstract: A semiconductor component includes a first semiconductor region (110, 210) having a first conductivity type and a second semiconductor region (120, 220) above the first semiconductor region and having a second conductivity type. The semiconductor component further comprises a third semiconductor region (130, 230) above the second semiconductor region and having the first conductivity type, a fourth semiconductor region (140, 240) above the third semiconductor region and having the second conductivity type, a fifth semiconductor region (150, 250) above the third semiconductor region and having the first conductivity type, a sixth semiconductor region (160, 260) substantially enclosed within the fifth semiconductor region and having the second conductivity type, and a seventh semiconductor region (170, 270) above the first semiconductor region and having the second conductivity type.Type: GrantFiled: March 14, 2003Date of Patent: February 17, 2004Assignee: Motorola, Inc.Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Patent number: 6673641Abstract: A process for the production of contacts for electrically operated II/VI semiconductor structures (for example laser diodes). The contact materials palladium and gold hitherto used in relation to electrically operated II/VI semiconductor lasers are distinguished by a relatively great, not purely ohmic specific contact resistance in relation to the II/VI cover layer. The consequentially necessary higher operating voltages result in the unnecessary generation of heat and thus substantially accelerate degradation of the entire laser structure. That effect causes a limitation in terms of the service life of II/VI semiconductor laser diodes. The invention permits the operation of semiconductor laser diodes with lower operating voltages. The II/VI semiconductor laser diodes produced with our invention are distinguished by a longer service life. That permits inter alia commercial use of semiconductor laser diodes in the blue-green spectral range.Type: GrantFiled: April 24, 2002Date of Patent: January 6, 2004Assignee: Technische Universitaet BerlinInventors: Matthias Strassburg, Oliver Schulz, Udo W. Pohl, Dieter Bimberg
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Patent number: 6664570Abstract: A p-type contact electrode device in a ZnSe-based II-VI compound semiconductor, which electrode device uses, as a contact layer, a BeTe layer having a high p-type doping and a low lattice mismatching with a GaAs substrate to prevent oxidation in air. The device 2 includes a contact layer 5 composed of p-BeTe and a cap layer 4 is composed of p-ZnSe. The cap layer 4 is positioned on the contact layer 5 and an electrode 3 sits atop the cap layer. Preferably, the thickness of the cap layer is 30 to 70 Å and the electrode is composed of gold or gold is dispersed in the cap layer.Type: GrantFiled: March 27, 2000Date of Patent: December 16, 2003Assignees: NGK Insulators, Ltd.Inventors: Takafumi Yao, Meoung-Whan Cho
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Patent number: 6638846Abstract: A ZnO based oxide semiconductor layer is grown on a sapphire substrate 1 by supplying, for example, raw materials made of Zn and O constituting ZnO and a p-type dopant material made of N without supplying an n-type dopant material (a-step). By stopping the supply of the material of O and further supplying an n-type dopant material made of Ga, the semiconductor layer is doped with the p-type dopant and the n-type dopant, thereby forming a p-type ZnO layer (2a) (b-step). By repeating the steps (a) and (b) plural times, a p-type ZnO based oxide semiconductor layer is grown. As a result, N to be the p-type dopant can be doped in a stable carrier concentration also during high temperature growth in which a residual carrier concentration can be reduced, and the carrier concentration of the p-type layer made of the ZnO based oxide semiconductor can be increased sufficiently.Type: GrantFiled: September 13, 2001Date of Patent: October 28, 2003Assignee: National Institute of Advanced Industrial Science and Technology and Rohm Co., Ltd.Inventors: Kakuya Iwata, Paul Fons, Koji Matsubara, Akimasa Yamada, Shigeru Niki, Ken Nakahara
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Patent number: 6593213Abstract: Systems and methods are described for synthesis of films, coatings or layers using electrostatic fields. A method includes applying an electrostatic field across a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.Type: GrantFiled: September 20, 2001Date of Patent: July 15, 2003Assignee: Heliovolt CorporationInventor: Billy J. Stanbery
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Patent number: 6555457Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.Type: GrantFiled: April 7, 2000Date of Patent: April 29, 2003Assignee: Triquint Technology Holding Co.Inventors: Gustav E. Derkits, Jr., William R. Heffner, Padman Parayanthal, Patrick J. Carroll, Ranjani C. Muthiah
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Patent number: 6468890Abstract: The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer (110), which adjoins the semiconductor region and is made of a material having a first and a second material component. A silicide formed from the first material component and the silicon of the silicon carbide and a carbide formed from the second material component and the carbon of the silicon carbide are contained in a junction region between the semiconductor region and the ohmic contact layer. The silicide and carbide formation take place at maximum 1000° C.Type: GrantFiled: March 2, 2001Date of Patent: October 22, 2002Assignee: Siced Electronics Development GmbH & Co. KGInventors: Wolfgang Bartsch, Reinhold Schörner, Dietrich Stephani
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Patent number: 6465273Abstract: A light emitting device includes an LED chip fixed to an electrode body via a conductive layer of In or an In alloy. The conductive layer is in ohmic-contact with an n-type ZnSe crystal substrate of the LED chip. To make the device, In or an In alloy is melted on the electrode body, the ZnSe substrate is placed directly on the melted In or In alloy and then subjected to at least one of vibration and pressure to achieve a good bond and ohmic contact between the In or In alloy and the ZnSe substrate.Type: GrantFiled: May 4, 2000Date of Patent: October 15, 2002Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideki Matsubara, Koji Katayama, Akihiko Saegusa
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Patent number: 6461952Abstract: A method for preparing a barium fluorotitanate (BaTiF6) powder and depositing a barium titanate (BaTiO3) thin film on a silicon wafer is disclosed. The method includes steps of a) producing a barium fluorotitanate powder by mixing a hexafluorotitanic acid solution and a barium nitrate solution at a low temperature, b) dissolving the barium fluorotitanate powder into water and mixing with a boric acid solution, and c) immersing a silicon wafer into the mixture at a low temperature to grow a barium titanate thin film on the silicon wafer.Type: GrantFiled: December 8, 2000Date of Patent: October 8, 2002Assignee: National Science CouncilInventors: Ming-Kwei Lee, Hsin-Chih Liao
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Patent number: 6429111Abstract: The electrode structure of the invention includes a p-type AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, x+y≦1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.Type: GrantFiled: December 20, 2000Date of Patent: August 6, 2002Assignee: Sharp Kabushiki KaishaInventor: Nobuaki Teraguchi
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Patent number: 6399473Abstract: A II-VI semiconductor component is produced with an active layer sequence having at least one II-VI semiconductor layer containing Se and/or S on a substrate. First, an Se-free II-VI interlayer based on BeTe is grown epitaxially on the substrate in an essentially Se-free and S-free first epitaxy chamber. The active layer sequence is then grown epitaxially on the Se-free II-VI semiconductor layer.Type: GrantFiled: January 10, 2000Date of Patent: June 4, 2002Assignee: Osram Opto Semiconductors GmbH & Co. oHGInventors: Frank Fischer, Matthias Keller, Thomas Litz, Gottfried Landwehr, Hans-Jürgen Lugauer, Andreas Waag, Markus Keim
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Patent number: 6376273Abstract: A II-VI semiconductor device includes a stack of semiconductor layers. An ohmic contact is provided that electrically couples to the stack. The ohmic contact has an oxidation rate when exposed to an oxidizing substance. A passivation capping layer overlies the ohmic contact and has an oxidation rate that is less than the oxidation rate of the ohmic contact.Type: GrantFiled: June 8, 1998Date of Patent: April 23, 2002Assignee: 3M Innovative Properties CompanyInventors: Fen-Ren Chien, Michael A. Haase, Thomas J. Miller
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Patent number: 6355545Abstract: The present invention provides a method for wiring, which plugs conductive material sufficiently into a via hole produced in dielectronics (hereinafter, referred to as “a via hole”) and prevents generating a void. The via hole is made through a via hole patterning step and a cleaning step. At a surface treatment step, substance having chemical affinity (active site) is adsorbed to the surface of the via hole. Next, an electron donative layer is made by depositing substance having an electron donative characteristic on the active sites acting as cores at an electron donative layer formation step. Then, the wiring material is plugged at a via hole plug step.Type: GrantFiled: March 31, 2000Date of Patent: March 12, 2002Assignee: Semiconductor Leading Edge Technologies, Inc.Inventor: Takayuki Ohba
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Publication number: 20020028570Abstract: Multi-metallic films are prepared from multi-metallic mixtures of metalloamide compounds. The mixtures are subjected to vaporization to form a multi-metallic vapor having defined and controllable stoichiometry. The multi-metallic vapor is then transferred to a chemical vapor deposition chamber, with or without the presence of a reactant gas, to form the multi-metallic film. Multi-metallic nitride, oxide, sulfide, boride, silicide, germanide, phosphide, arsenide, selenide, telluride, etc. films may be prepared by appropriate choice of metalloamide compounds and reactant gas(es).Type: ApplicationFiled: August 29, 2001Publication date: March 7, 2002Inventor: Brian A. Vaartstra
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Patent number: 6326294Abstract: A method of fabricating on ohmic metal electrode. The p-type ohmic metal electrode according to the present invention employs Ru and RuOx as the cover layer in lieu of conventional Au, in order to effectively prevent penetration by contaminants in the air, such as oxygen, carbon, and H2O, and to form a stable metal-Ga intermetallic phase at the junction between the contact layer and the nitride compound semiconductor. The n-type ohmic metal electrode according to the present invention employs Ru as the diffusion barrier in lieu of conventional Ni or Pt, in order to effectively form a metal-nitride phase such as titanium nitride that contributes to superior ohmic characteristics during the heating process, without destruction of the junction. According to the present invention, it is possible to fabricate devices having superior electrical, optical, and thermal characteristics compared with conventional devices.Type: GrantFiled: April 24, 2001Date of Patent: December 4, 2001Assignee: Kwangju Institute of Science and TechnologyInventors: Ja Soon Jang, Tae Yeon Seong, Seong Ju Park
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Publication number: 20010034115Abstract: A method for forming a p-type semiconductor film comprises the steps of: providing on a substrate a group II-VI compound semiconductor film which is doped with a p-type impurity and comprises either MgxZn1-xO (0≦X≦1) or CdxZn1-xO (0≦X≦1) and activating the p-type impurity by annealing the doped semiconductor film.Type: ApplicationFiled: April 19, 2001Publication date: October 25, 2001Applicant: Murata Manufacturing Co., Ltd.Inventors: Michio Kadota, Yasuhiro Negoro, Toshinori Miura
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Patent number: 6281035Abstract: A method of making a low-resistance electrical contact between a p-CdTe layer and outer contact layers by ion beam processing comprising: a) placing a CdS/CdTe device into a chamber and evacuating the chamber; b) orienting the p-CdTe side of the CdS/CdTe layer so that it faces apparatus capable of generating Ar atoms and ions of preferred energy and directionality; c) introducing Ar and igniting the area of apparatus capable of generating Ar atoms and ions of preferred energy and directionality in a manner so that during ion exposure, the source-to-substrate distance is maintained such that it is less than the mean-free path or diffusion length of the Ar atoms and ions at the vacuum pressure; d) allowing exposure of the p-CdTe side of the device to said ion beam for a period less than about 5 minutes; and e) imparting movement to the substrate to control the real uniformity of the ion-beam exposure on the p-CdTe side of the device.Type: GrantFiled: September 25, 1997Date of Patent: August 28, 2001Assignee: Midwest Research InstituteInventor: Timothy A. Gessert
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Patent number: 6251701Abstract: An all dry method for producing solar cells is provided comprising first heat-annealing a II-VI semiconductor; enhancing the conductivity and grain size of the annealed layer; modifying the surface and depositing a tellurium layer onto the enhanced layer; and then depositing copper onto the tellurium layer so as to produce a copper tellurium compound on the layer.Type: GrantFiled: March 1, 2000Date of Patent: June 26, 2001Assignee: The United States of America as represented by the United States Department of EnergyInventor: Brian E. McCandless
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Publication number: 20010003057Abstract: A II-VI semiconductor device includes a stack of semiconductor layers. An ohmic contact is provided that electrically couples to the stack. The ohmic contact has an oxidation rate when exposed to an oxidizing substance. A passivation capping layer overlies the ohmic contact and has an oxidation rate that is less than the oxidation rate of the ohmic contact.Type: ApplicationFiled: June 8, 1998Publication date: June 7, 2001Inventors: FEN-REN CHIEN, MICHAEL A. HAASE, THOMAS J. MILLER
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Publication number: 20010001079Abstract: The electrode structure of the invention includes a p-type AlxGayIn1−x−yN (0≦ x< 1, 0≦ y≦ 1, x+ y≦ 1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.Type: ApplicationFiled: December 20, 2000Publication date: May 10, 2001Inventor: Nobuaki Teraguchi
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Patent number: 6204560Abstract: As will be described in more detail hereinafter, there is disclosed herein a titanium nitride diffusion barrier layer and associated method for use in non-silicon semiconductor technologies. In one aspect of the invention, a semiconductor device includes a non-silicon active surface. The improvement comprises an ohmic contact serving to form an external electrical connection to the non-silicon active surface in which the ohmic contact includes at least one layer consisting essentially of titanium nitride. In another aspect of the invention, a semiconductor ridge waveguide laser is disclosed which includes a semiconductor substrate and an active layer disposed on the substrate. A cladding layer is supported partially on the substrate and partially on the active layer. The cladding layer includes a ridge portion disposed in a confronting relationship with the active region.Type: GrantFiled: April 20, 1998Date of Patent: March 20, 2001Assignee: Uniphase Laser Enterprise AGInventors: Andreas Daetwyler, Urs Deutsch, Christoph Harder, Wilhelm Heuberger, Eberhard Latta, Abram Jakubowicz, Albertus Oosenbrug, William Patrick, Peter Roentgen, Erica Williams
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Patent number: 6103604Abstract: A transparent electrical conductor which provides relatively high electrical conductivity and transmittance in the visible/near-infrared (VNIR), relative to known transparent electrical conductors, such as tin-doped indium oxide (ITO). In one embodiment of the invention, the transparent electrical conductor is formed from a plurality of quantum wells formed between the interfaces of three layers of lattice-matched, wide band gap materials, such as AlGaN and GaN. In an alternative embodiment of the invention, a material with a band gap much larger than known materials used for such transparent electrical conductors, such as ITO, is selected. Both embodiments of the invention may be formed on a transparent substrate and provide relatively better transmittance in the VNIR at sheet electrical resistances of four or less ohms/square than known materials, such as tin-doped indium oxide (ITO).Type: GrantFiled: February 10, 1997Date of Patent: August 15, 2000Assignee: TRW Inc.Inventors: William M. Bruno, Maurice P. Bianchi
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Patent number: 6083818Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF.sub.2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.Type: GrantFiled: December 18, 1998Date of Patent: July 4, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael F. Stumborg, Francisco Santiago, Tak Kin Chu, Kevin A. Boulais
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Patent number: 6033929Abstract: A II-VI group compound semiconductor device includes a semiconductor substrate, a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer formed on the semiconductor substrate, and an electrode layer formed on the semiconductor layer, the electrode layer containing an additive element of Cd or Te and a metal which can form a eutectic alloy with the additive element, thus achieving an electrode layer having a small contact resistance, especially an electrode layer with an ohmic contact.Type: GrantFiled: March 22, 1996Date of Patent: March 7, 2000Assignee: Sharp Kabushiki KaishaInventors: Masanori Murakami, Yasuo Koide, Nobuaki Teraguchi
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Patent number: 5966629Abstract: The electrode structure of the invention includes a p-type Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.Type: GrantFiled: July 15, 1997Date of Patent: October 12, 1999Assignee: Sharp Kabushiki KaishaInventor: Nobuaki Teraguchi
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Patent number: 5924002Abstract: A semiconductor device having an ohmic electrode having a satisfactory ohmic contact to an n-type GaAs can be obtained by heat treatment at low temperature. A method of manufacturing the semiconductor device having the ohmic electrode includes two processes. In the first process, a metal layer containing Ni, Sn and AuGe is formed on one main surface of the n-type GaAs. In the second process, the n-type GaAs is subjected to a heat treatment at a temperature which is equal to or higher than 190 C. and equal to or lower than 300 C. Thus, the ohmic electrode is formed on the one main surface of the n-type GaAs.Type: GrantFiled: December 19, 1995Date of Patent: July 13, 1999Assignee: Sony CorporationInventors: Tsuyoshi Tojyo, Futoshi Hiei
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Patent number: 5909632Abstract: A method of improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising:depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurim-containing II-VI semiconductor, but thin enough to minimize affects of series resistance;depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; anddepositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact.Type: GrantFiled: September 25, 1997Date of Patent: June 1, 1999Assignee: Midwest Research InstituteInventor: Timothy A. Gessert
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Patent number: 5786269Abstract: A II-VI group compound semiconductor device having a p-type Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) semiconductor layer, on which an electrode layer is formed with at least metallic nitride layer lying between the semiconductor layer and the electrode layer.Type: GrantFiled: September 24, 1996Date of Patent: July 28, 1998Assignee: Sharp Kabushiki KaishaInventors: Masanori Murakami, Yasuo Koide, Nobuaki Teraguchi, Yoshitaka Tomomura
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Patent number: 5780322Abstract: A method for growing a II-VI compound semiconductor layer containing Cd, such as Zn.sub.1-x Cd.sub.x Se, by a molecular beam epitaxy method is disclosed. During the growth, the ratio of the intensity of molecular beams of a group VI element to the intensity of molecular beams of a group II element in terms of intensities of molecular beams actually irradiated onto a substrate, namely, the substantial VI/II ratio, is controlled preferably in the range from 0.7 to 1.3, to increase the Cd incorporating efficiency into the grown layer sufficiently high.Type: GrantFiled: September 27, 1996Date of Patent: July 14, 1998Assignee: Sony CorporationInventors: Koshi Tamamura, Hironori Tsukamoto, Masao Ikeda
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Patent number: 5773085Abstract: One kind of element belonging to I group or II group and one kind of binary compound including one kind of element belonging to III group and one kind of element selected from the group consisting of S, Se, Te and O are evaporated respectively by means of a vacuum vapor deposition method or molecular beam epitaxial method to produce a ternary compound semiconductor material having a low vapor pressure, and the thus produced ternary compound semiconductor material is deposited on a substrate to form a ternary compound semiconductor thin film. Particularly, when a phosphor thin film for electroluminescence emitting blue light is to be grown, an element Sr and a binary compound Ga.sub.2 S.sub.3 are respectively evaporated by the vacuum evaporation method or molecular beam epitaxial method to deposit a ternary compound semiconductor material SrGa.sub.2 S.sub.Type: GrantFiled: June 12, 1996Date of Patent: June 30, 1998Assignee: Nippon Hoso KyokaiInventors: Yoji Inoue, Katsu Tanaka, Shinji Okamoto, Kikuo Kobayashi