To Compound Semiconductor Patents (Class 438/602)
  • Patent number: 10249793
    Abstract: A light emitting diode includes an active region configured to emit light, a composite electrical contact layer, and a transparent electron blocking hole transport layer (TEBHTL). The composite electrical contact layer includes tow materials. At least one of the two materials is a metal configured to reflect a portion of the emitted light. The TEBHTL is arranged between the composite electrical contact layer and the active region. The TEBHTL has a thickness that extends at least a majority of a distance between the active region and the composite electrical contact layer. The TEBHTL has a band-gap greater than a band-gap of light emitting portions of the active region. The band-gap of the TEBHTL decreases as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: April 2, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: John E. Northrup, Christopher L. Chua
  • Patent number: 10242879
    Abstract: Provided herein are atomic layer deposition (ALD) methods of depositing cobalt in a feature. The methods involve two-step surface treatments during an ALD cycle, with one step involving the reaction of a co-reactant gas with an adsorbed cobalt precursor and the other step involving a growth-inhibiting reactant gas on the cobalt surface. The growth-inhibiting reactant gas significantly lowers cobalt growth rate, producing a highly conformal cobalt film. The described ALD processes enable improved controllability in film nucleation, step coverage, and morphology by the separate surface treatment and low process temperature. The methods are applicable to a variety of feature fill applications including the fabrication of metal gate/contact fill in front end of line (FEOL) processes as well as via/line fill in back end of line (BEOL) processes.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Jeong-Seok Na, Raashina Humayun
  • Patent number: 9882089
    Abstract: A light emitting diode includes an active region configured to emit light, a composite electrical contact layer, and a transparent electron blocking hole transport layer (TEBHTL). The composite electrical contact layer includes tow materials. At least one of the two materials is a metal configured to reflect a portion of the emitted light. The TEBHTL is arranged between the composite electrical contact layer and the active region. The TEBHTL has a thickness that extends at least a majority of a distance between the active region and the composite electrical contact layer. The TEBHTL has a band-gap greater than a band-gap of light emitting portions of the active region. The band-gap of the TEBHTL decreases as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 30, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: John E. Northrup, Christopher L. Chua
  • Patent number: 9685566
    Abstract: A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: June 20, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Chikamori, Yasuhiko Nishio, Naoki Yutani
  • Patent number: 9570359
    Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-seung Yang, Mohammad Rakib Uddin, Myoung-jae Lee, Sang-moon Lee, Sung-hun Lee, Seong-ho Cho
  • Patent number: 9478629
    Abstract: In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 25, 2016
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Martin Domeij, Benedetto Buono
  • Patent number: 9406829
    Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 2, 2016
    Assignee: First Solar, Inc.
    Inventors: Pratima Addepalli, Benyamin Buller, Markus Gloeckler, Akhlesh Gupta, David Hwang, Andrei Los, Rick Powell, Rui Shao, Gang Xiong, Ming Lun Yu, San Yu, Zhibo Zhao
  • Patent number: 9269814
    Abstract: The present disclosure relates to a structure and method for fin isolation in bulk FinFETs. A sacrificial portion is formed between the actual fin and the substrate, which gets selectively removed at a later stage of processing to reveal a cavity which extends all the way under the fin. This helps prevent source/drain leakage as there is no path for current flow between the fin and bulk substrate. Furthermore, this method of formation helps in precise control of fin-height in bulk FinFETs.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Rung Hsu
  • Patent number: 9263635
    Abstract: A semiconductor structure includes a silicon substrate, a buffer layer, a nitride-based epitaxial structure layer and multiple discontinuous strain-releasing layers. The buffer layer is disposed on the silicon substrate. The nitride-based epitaxial structure layer is disposed on the buffer layer. The discontinuous strain-releasing layers are disposed between the silicon substrate and the nitride-based epitaxial structure layer, wherein a material of the discontinuous strain-releasing layers is silicon nitride.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: February 16, 2016
    Assignee: Genesis Photonics Inc.
    Inventors: Sheng-Han Tu, Chi-Feng Huang
  • Patent number: 9136398
    Abstract: In one aspect of the present invention, the semiconductor device is a bipolar magnetic junction transistor (MJT), and includes a first non-magnetic semiconductor layer, a second non-magnetic semiconductor layer, and a magnetic semiconductor layer. The first non-magnetic semiconductor layer has majority charge carriers of a first polarity. The second non-magnetic semiconductor layer is disposed adjacent to the first non-magnetic semiconductor layer such that a first junction is formed at a first interface region between the first non-magnetic semiconductor layer and the second non-magnetic semiconductor layer. The magnetic semiconductor layer has majority charge carriers of the first polarity, and is disposed adjacent to the second non-magnetic semiconductor layer such that a second junction is formed at a second interface region between the second non-magnetic semiconductor layer and the magnetic semiconductor layer.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: September 15, 2015
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Bruce W. Wessels, Nikhil Rangaraju, John A. Peters
  • Patent number: 9099578
    Abstract: A semiconductor-to-metal interface with ohmic contact is provided. The interface includes a semiconductor material, a metal layer, and a silicon carbide layer disposed between the semiconductor material and the metal layer. The silicon carbide layer causes the formation of a semiconductor-to-metal interface with ohmic contact. Applications include forming a photovoltaic device with ohmic contact by disposing a layer of silicon carbide over the photovoltaic material before depositing a bottom electrode layer of metal to complete the bottom of a photovoltaic cell.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 4, 2015
    Assignee: Nusola, Inc.
    Inventors: Atsushi Yamaguchi, Jose Briceno
  • Patent number: 9076854
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 7, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20150132939
    Abstract: A method is provided for forming a semiconductor device. According to one embodiment, the method includes providing a substrate having a Ge-containing film thereon, identifying a first plasma processing recipe that uses a metal chloride precursor to deposit a first metal layer on the Ge-containing film at a higher rate than the Ge-containing film is etched by the metal chloride precursor, identifying a second plasma processing recipe that uses the metal chloride precursor to etch the Ge-containing film at a higher rate than a second metal layer is deposited on the Ge-containing film by the metal chloride precursor, performing the first plasma processing recipe to deposit the first metal layer on the Ge-containing film, and performing the second plasma processing recipe to deposit the second metal layer on the first metal layer, and where the second metal layer is deposited at a higher rate than the first metal layer.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 14, 2015
    Inventors: Toshio Hasegawa, Hideaki Yamasaki
  • Publication number: 20150123149
    Abstract: A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Publication number: 20150093890
    Abstract: A metal precursor and a method comprising decomposing a metal precursor on an integrated circuit device; and forming a metal from the metal precursor, wherein the metal precursor is selected from the group consisting of (i) a Co2(CO)6(R1C?CR2), wherein R1 and R2 are individually selected from a straight or branched monovalent hydrocarbon group have one to six carbon atoms that may be interrupted and substituted; (ii) a mononuclear cobalt carbonyl nitrosyl; (iii) a cobalt carbonyl bonded to one of a boron, indium, germanium and tin moiety; (iv) a cobalt carbonyl bonded to a mononuclear or binuclear allyl; and (v) a cobalt (II) complex comprising nitrogen-based supporting ligands.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: James M. Blackwell, Scott B. Clendenning, John J. Plombon, Patricio E. Romero
  • Publication number: 20150079781
    Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventors: Jun KAWAI, Norihito TOKURA, Kazuhiko SUGIURA
  • Publication number: 20150064898
    Abstract: A first metal layer (3) is formed on a back face of a silicon carbide substrate (1) to a degree such that the first metal layer (3) does not fully cover the back face of the silicon carbide substrate. Many holes (4) are formed on the back face of the silicon carbide substrate (1) by dry-etching the back face of the silicon carbide substrate (1) using the first metal layer (3) as a mask therefor. A second metal layer constituting an ohmic contact is formed on the first metal layer (3) and the back face of the silicon carbide substrate (1) including inner surfaces of the many holes (4).
    Type: Application
    Filed: March 14, 2013
    Publication date: March 5, 2015
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masahide Goto, Kenji Fukuda, Noriyuki Iwamuro
  • Patent number: 8962468
    Abstract: Systems and methods for semiconductor wafer processing include irradiating a surface of a semiconductor wafer with a laser beam of sufficient energy to alter a band gap of semiconductor material thereby melting a portion of the wafer to generate a graphitic layer area. A metal layer is then depositing on the surface to create ohmic contacts at the area that where melted by the laser.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 24, 2015
    Assignee: United Silicon Carbide, Inc.
    Inventor: John L. Hostetler
  • Patent number: 8940579
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignees: Northwestern University, Polyera Corporation
    Inventors: Antonio Facchetti, Tobin J. Marks, Mercouri G. Kanatzidis, Myung-Gil Kim, William Christopher Sheets, He Yan, Yu Xia
  • Publication number: 20150024586
    Abstract: In the method for producing a monocrystalline metal-semiconductor compound on the surface of a semiconducting functional layer, initially a supply layer comprising the metal is applied to the functional layer. Thereafter, the reaction between the metal and the functional layer is triggered by way of annealing. The supply layer ends at no greater than a layer thickness of 5 nm from the surface of the functional layer, or it transitions at no greater than this layer thickness into a region in which the metal diffuses more slowly than in the region that directly adjoins the functional layer. This measure advantageously allows diffusion flow of the metal into the functional layer to be prevented. This depends precisely on whether the metal-semiconductor compound is monocrystalline.
    Type: Application
    Filed: February 16, 2013
    Publication date: January 22, 2015
    Inventors: Qing-Tai Zhao, Lars Knoll, Siegfried Mantl
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8916462
    Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 23, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii
  • Patent number: 8916939
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hong Yu, Huang Liu
  • Patent number: 8900985
    Abstract: A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Patent number: 8889491
    Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, John A. Fitzsimmons, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8877549
    Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C., with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 4, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jeffrey F. Roeder, Thomas H. Baum, Bryan C. Hendrix, Gregory T. Stauf, Chongying Xu, William Hunks, Tianniu Chen, Matthias Stender
  • Patent number: 8846518
    Abstract: A multilayer construction is disclosed. The multilayer construction includes a -II-VI semiconductor layer (110)x and a Si3N4 layer (120) disposed directly on the II-VI semiconductor layer. To improve the adhesion of the Si3N4 layer (120) a native oxide on the II-VI semiconductor layer is removed.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: September 30, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Jun-Ying Zhang, Michael A. Haase, Todd A. Ballen, Terry L. Smith
  • Patent number: 8828748
    Abstract: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 9, 2014
    Assignee: Infineon Technologies AG
    Inventor: Sajan Marokkey
  • Patent number: 8802552
    Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Patent number: 8785316
    Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Soitec
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8785315
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Patent number: 8778753
    Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
  • Patent number: 8765584
    Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 1, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshitaka Kadowaki, Tatsunori Toyota
  • Patent number: 8753985
    Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8741686
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 8735195
    Abstract: Disclosed is a method of manufacturing a ZnO-based semiconductor device having at least p-type ZnO-based semiconductor layer, which includes a step of forming a contact metal layer on the p-type ZnO-based semiconductor layer wherein the contact metal layer contains at least one of Ni and Cu; and a step of performing heat treatment of the contact metal layer and the p-type ZnO-based semiconductor layer under an oxygen-free atmosphere to form a mixture layer including elements of the p-type ZnO-based semiconductor layer and the contact metal layer at a boundary region therebetween while maintaining a metal phase layer on a surface of the contact metal layer.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 27, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Naochika Horio
  • Patent number: 8728923
    Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 20, 2014
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Tetsuji Kondou, Kazuhiko Sugiura, Nobuyuki Kato
  • Patent number: 8716121
    Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1-x-y)Si(x)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 6, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Masahiro Sugimoto, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Publication number: 20140084345
    Abstract: A compound semiconductor device includes: a compound semiconductor stacked structure; a source electrode and a drain electrode formed separately from each other above the compound semiconductor stacked structure; a gate electrode formed between the source electrode and the drain electrode above the compound semiconductor stacked structure; and a passivation film formed above the compound semiconductor stacked structure and made of an insulating material containing Al, in which the passivation film is in a non-contact state with the compound semiconductor stacked structure under the source electrode and the drain electrode.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Toshihiro Ohki, YUUICHI SATOU
  • Patent number: 8679894
    Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C., with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jeffrey F. Roeder, Thomas H. Baum, Bryan C. Hendrix, Gregory T. Stauf, Chongying Xu, William Hunks, Tianniu Chen, Matthias Stender
  • Publication number: 20140061674
    Abstract: In some aspects of the invention, a layer containing titanium and nickel is formed on an SiC substrate. A nickel silicide layer containing titanium carbide can be formed by heating. A carbon layer precipitated is removed by reverse sputtering. Thus, separation of an electrode of a metal layer formed on nickel silicide in a subsequent step is suppressed. The effect of preventing the separation can be further improved when the relation between the amount of precipitated carbon and the amount of carbon in titanium carbide in the surface of nickel silicide from which the carbon layer has not yet been removed satisfies a predetermined condition.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 6, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Fumikazu IMAI
  • Publication number: 20140061912
    Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).
    Type: Application
    Filed: March 16, 2012
    Publication date: March 6, 2014
    Inventor: Walt A. De Heer
  • Publication number: 20140051241
    Abstract: A surface of a silicon carbide substrate on which a graphite layer is formed is covered with a metal layer which can form carbide. Then, the silicon carbide substrate is annealed to cause reaction between a metal in the metal layer which can form carbide and carbon in the graphite layer so as to change the graphite layer between the metal layer which can form carbide and the silicon carbide substrate to a metal carbide layer. Thus, the graphite layer is removed. The adhesion between the metal layer which can form carbide and the silicon carbide substrate can be improved so that separation of the metal layer which can form carbide can be suppressed. Graphite deposits can be suppressed due to the removal of the graphite layer so that separation of a wiring metal film formed on a surface of the metal layer which can form carbide can be suppressed.
    Type: Application
    Filed: April 6, 2012
    Publication date: February 20, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Takashi Tsuji, Fumikazu Imai
  • Patent number: 8652949
    Abstract: A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 18, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Patent number: 8623752
    Abstract: An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: January 7, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Hideto Tamaso
  • Patent number: 8563088
    Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 22, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Kevin Calzia, David Mosley, David L. Thorsen, Charles R. Szmanda
  • Patent number: 8564129
    Abstract: Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10?6 ohms·cm2.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: Phononic Devices, Inc.
    Inventors: Robert Joseph Therrien, Jason D. Reed, Jaime A. Rumsey, Allen L. Gray
  • Patent number: 8519482
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: August 27, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hong Yu, Huang Liu
  • Patent number: 8507364
    Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: August 13, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka University
    Inventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
  • Publication number: 20130143398
    Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.
    Type: Application
    Filed: September 11, 2012
    Publication date: June 6, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii