Ii-vi Compound Semiconductor Patents (Class 438/603)
  • Patent number: 9443759
    Abstract: A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: September 13, 2016
    Assignee: AMS AG
    Inventors: Rainer Minixhofer, Ewald Stückler, Martin Schrems, Günther Koppitsch, Jochen Kraft, Jordi Teva
  • Patent number: 8961745
    Abstract: The plant is suitable to produce a semiconductor film (8) having a desired thickness and consisting substantially of a compound including at least one element for each of the groups 11, 13, and 16 of the periodic classification of elements. The plant comprises an outer case (1) embedding a chamber (2) divided into one deposition zone (2a) and one evaporation zone (2b), which are separated by a screen (3) interrupted by at least one cylindrical transfer member provided with actuation means rotating about its axis (5). To the deposition zone (2a) a magnetron device (7) is associated, for the deposition by sputtering of at least one element for each of the groups 11 and 13 on the side surface (?) of the cylindrical member that is in the deposition zone (2a). To the evaporation zone (2b) a cell (10) for the evaporation of at least one element of the group 16 is associated, and such an evaporation zone (2b) houses a substrate (8a) on which the film (8) is produced.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 24, 2015
    Assignee: VOLTASOLAR S.r.l.
    Inventors: Maurizio Filippo Acciarri, Simona Olga Binetti, Leonida Miglio, Maurilio Meschia, Raffaele Moneta, Stefano Marchionna
  • Patent number: 8962496
    Abstract: The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 ?m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: February 24, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas Jouanneau, Yann Bogumilowicz
  • Patent number: 8859412
    Abstract: Optoelectronic devices, such as light-emitting diodes, laser diodes, image sensors, optical detectors, etc., made by depositing (growing) one or more epitaxial semiconductor layers on a monocrystalline lamellar/layered substrate so that each layer has a wurtzite crystal structure. In some embodiments, the layers are deposited and then one or more lamellas of the starting substrate are removed from the rest of the substrate. In one subset of such embodiments, the removed lamella(s) is/are partially or entirely removed. In other embodiments, one or more lamellas of the starting substrate are removed prior to depositing the one or more wurtzite-crystal-structure-containing layer(s).
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: October 14, 2014
    Assignee: VerLASE Technologies LLC
    Inventor: Ajaykumar R. Jain
  • Patent number: 8846518
    Abstract: A multilayer construction is disclosed. The multilayer construction includes a -II-VI semiconductor layer (110)x and a Si3N4 layer (120) disposed directly on the II-VI semiconductor layer. To improve the adhesion of the Si3N4 layer (120) a native oxide on the II-VI semiconductor layer is removed.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: September 30, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Jun-Ying Zhang, Michael A. Haase, Todd A. Ballen, Terry L. Smith
  • Patent number: 8772150
    Abstract: Disclosed herein is a method of forming a p-type zinc oxide thin film. A zinc oxide layer and an antimony oxide layer are alternately stacked one above another on a substrate, forming a superlattice layer. The superlattice layer is modified into a p-type zinc oxide thin film by annealing. Upon annealing, zinc atoms of the zinc oxide layer are diffused into the antimony oxide layer and antimony atoms of the antimony oxide layer are diffused into the zinc oxide layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 8, 2014
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Seong Ju Park, Yong Seok Choi, Jang Won Kang
  • Patent number: 8764903
    Abstract: The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 1, 2014
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts
  • Patent number: 8685848
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yoichiro Tarui
  • Patent number: 8673401
    Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 18, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Patent number: 8618411
    Abstract: A photovoltaic cell is made by coating a metal foil substrate with cadmium telluride powder, moving the powder coated foil across a cold plate or series of cooled rollers to prevent the substrate from melting, while melting the cadmium telluride powder by passing the powder coated foil under a microwave energy source. This forms a thin film of cadmium telluride on the foil. The cadmium telluride coated foil is then coated with cadmium sulfide powder, which is melted by passing the powder coated foil under a microwave energy source, thereby creating a P-N junction, and the cadmium sulfide layer is coated with indium, which is fused to the cadmium sulfide layer by microwave heating.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: December 31, 2013
    Inventor: David M. Schwartz
  • Patent number: 8580126
    Abstract: An exemplary method for a producing a piezoelectric vibrating piece having at least one mesa step includes forming a metal film on a main surface of a piezoelectric wafer. A through-groove is formed through the thickness of the wafer to form a plan profile of a desired piezoelectric substrate. A film of photoresist is formed on the surface of the metal film. A resist is applied, exposed, and formed into a resist pattern that defines a first mesa step along at least a portion of the plan profile. In regions not protected by the metal film, the piezoelectric substrate is etched to a defined depth to form a mesa step. The denuded edge surface of the metal film is edge-etched. A second mesa step, inboard of the first mesa step, can be formed by repeating the edge-etching and substrate-etching steps using the metal film as an etch protective film.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 12, 2013
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Hiroyuki Sasaki, Kenji Shimao, Manabu Ishikawa
  • Patent number: 8564129
    Abstract: Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10?6 ohms·cm2.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: Phononic Devices, Inc.
    Inventors: Robert Joseph Therrien, Jason D. Reed, Jaime A. Rumsey, Allen L. Gray
  • Patent number: 8476105
    Abstract: In one aspect of the present invention, a method is provided. The method includes disposing a substantially amorphous cadmium tin oxide layer on a support; and thermally processing the substantially amorphous cadmium tin oxide layer in an atmosphere substantially free of cadmium from an external source to form a transparent layer, wherein the transparent layer has an electrical resistivity less than about 2×10?4 Ohm-cm. Method of making a photovoltaic device is also provided.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 2, 2013
    Assignee: General Electric Company
    Inventors: Holly Ann Blaydes, George Theodore Dalakos, David William Vernooy, Allan Robert Northrup, Juan Carlos Rojo, Peter Joel Meschter, Hongying Peng, Hongbo Cao, Yangang Andrew Xi, Robert Dwayne Gossman, Anping Zhang
  • Patent number: 8395184
    Abstract: A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: March 12, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Masaaki Sakuta
  • Patent number: 8372485
    Abstract: A gallium ink is provided, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; wherein the gallium ink is a stable dispersion. Also provided are methods of preparing the gallium ink and for using the gallium ink in the preparation of semiconductor films (e.g., in the deposition of a CIGS layer for use in photovoltaic devices).
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 12, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Patent number: 8119513
    Abstract: A method for making a cadmium sulfide layer is provided. The method includes a number of steps including providing a substrate and disposing a layer containing cadmium on the substrate followed by sulfurization of the cadmium-containing layer.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: February 21, 2012
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, Scott Feldman-Peabody, Robert Dwayne Gossman
  • Publication number: 20120028409
    Abstract: Thin film photovoltaic devices are generally provided. The device can include a transparent conductive oxide layer on a glass substrate, an n-type thin film layer on the transparent conductive layer, and a p-type thin film layer on the n-type layer. The n-type thin film layer and the p-type thin film layer form a p-n junction. An anisotropic conductive layer is applied on the p-type thin film layer, and includes a polymeric binder and a plurality of conductive particles. A metal contact layer can then be positioned on the anisotropic conductive layer.
    Type: Application
    Filed: August 27, 2010
    Publication date: February 2, 2012
    Applicant: PrimeStar Solar, Inc.
    Inventors: Tammy Jane Lucas, Robert Dwayne Gossman, Scott Daniel Feldman-Peabody
  • Patent number: 8093618
    Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: January 10, 2012
    Assignees: Seoul Opto Device Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jong Lam Lee, Sang Han Lee
  • Publication number: 20110308593
    Abstract: A layer including modified cadmium telluride and unmodified cadmium telluride disposed within the cadmium telluride layer. The modified area includes a concentration of telluride that is greater than the concentration of telluride in the unmodified cadmium telluride area. The modified area also includes a hexagonal close packed crystal structure. A method for modifying a cadmium telluride layer and a thin film device are also disclosed.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 22, 2011
    Applicant: PRIMESTAR SOLAR
    Inventor: Jonathan M. FREY
  • Patent number: 8067297
    Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: November 29, 2011
    Assignee: ASM America, Inc.
    Inventor: Michael A. Todd
  • Patent number: 8043937
    Abstract: It is an object to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide. The method for manufacturing a semiconductor device includes the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate and a base substrate with insulating layers interposed between the silicon substrate and the base substrate; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed between the base substrate and the stacked layer; and removing the silicon layer to expose a surface of the silicon carbide layer.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toru Takayama
  • Patent number: 7939454
    Abstract: A method for packaging solar cell module. The method includes providing a first substrate member and forming a plurality of thin film photovoltaic cells overlying the surface region of the first substrate member. A first connector member and a second connector member having a second thickness are operably coupled to each of the plurality of thin film photovoltaic cells. A first spacer element and a second spacer element overly portions of the surface region of the first substrate member. The method provides a laminating material overlying the plurality of thin film photovoltaic cells, the spacer elements, and the connector members. A second substrate member overlies the laminating material. A lamination process is performed to form the solar cell module by maintaining a spatial gap occupied by the laminating material between an upper surface regions of the connector members and the second substrate member using the spacer elements.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: May 10, 2011
    Assignee: Stion Corporation
    Inventor: Chester A. Farris, III
  • Patent number: 7923368
    Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: April 12, 2011
    Assignee: Innovalight, Inc.
    Inventors: Mason Terry, Homer Antoniadis, Dmitry Poplavskyy, Maxim Kelman
  • Patent number: 7897489
    Abstract: A method of selectively attaching a capping agent to an H-passivated Si or Ge surface is disclosed. The method includes providing the H-passivated Si or Ge surface, the H-passivated Si or Ge surface including a set of covalently bonded Si or Ge atoms and a set of surface substitutional atoms, wherein the set of surface substitutional atoms includes at least one of boron atoms, aluminum atoms, gallium atoms, indium atoms, tin atoms, lead atoms, phosphorus atoms, arsenic atoms, sulfur atoms, and bismuth atoms. The method also includes exposing the set of surface functional atoms to a set of capping agents, each capping agent of the set of capping agents having a set of functional groups bonded to a pair of carbon atoms, wherein the pair of carbon atoms includes at least one pi orbital bond, and further wherein a covalent bond is formed between at least some surface substitutional atoms of the set of surface substitutional atoms and at least some capping agents of the set of capping agents.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 1, 2011
    Assignee: Innovalight, Inc.
    Inventor: Elena Rogojina
  • Patent number: 7888256
    Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 15, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Giovanni Abagnale, Dario Salinas, Sebastiano Ravesi
  • Patent number: 7863178
    Abstract: The present invention relates to an AlGaInN based optical device fabricated by a new p-type AlGaInN:Mg growth method and method for manufacturing the same, including a p-type nitride semiconductor layer that is grown using both NH3 and a hydrazine based source as a nitrogen precursor, thereby an additional subsequent annealing process for extracting hydrogen is not necessary and thus the process is simple and an active layer can be prevented from being thermally damaged by subsequent annealing.
    Type: Grant
    Filed: August 21, 2004
    Date of Patent: January 4, 2011
    Assignees: Epivalley Co., Ltd., Samsung LED Co., Ltd.
    Inventors: Tae-Kyung Yoo, Joong Seo Park, Eun Hyun Park
  • Patent number: 7847297
    Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: December 7, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Jeffrey N Miller, David P Bour, Virginia M Robbins, Steven D Lester
  • Patent number: 7825020
    Abstract: Disclosed herein is a method of manufacturing a semiconductor device that includes forming a metal catalytic pattern on a semiconductor substrate; etching the semiconductor substrate using the metal catalytic pattern as an etching mask to form a recess; forming an insulating layer over a structure including the recess, the metal catalytic pattern, and the semiconductor substrate; patterning the insulating layer to cross over the metal catalytic pattern and to expose a predetermined portion of the metal catalytic pattern; and growing a nano wire using the exposed predetermined portion of the metal catalytic pattern.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hyun Lee
  • Patent number: 7795125
    Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: September 14, 2010
    Assignee: Nanosys, Inc.
    Inventors: Mihai A. Buretea, Jian Chen, Calvin Y. H. Chow, Chunming Niu, Yaoling Pan, J. Wallace Parce, Linda T. Romano, David P. Stumbo
  • Patent number: 7749805
    Abstract: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 6, 2010
    Assignee: Qimonda AG
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Patent number: 7691353
    Abstract: Low dielectric constant group II-VI compounds, such as zinc oxide, and fabrication methods are disclosed. Low dielectric constant insulator materials are fabricated by doping zinc oxide with at least one mole % p-type dopant ion. Low dielectric constant zinc oxide insulator materials are fabricated by doping zinc oxide with silicon having a concentration of at least 1017 atoms/cm3. Low dielectric zinc oxide insulator materials are fabricated by doping zinc oxide with a dopant ion having a concentration of at least about 1018 atoms/cm3, followed by heating to a temperature which converts the zinc oxide to an insulator. The temperature varies depending upon the choice of dopant. For arsenic, the temperature is at least about 450° C.; for antimony, the temperature is at least about 650° C. The dielectric constant of zinc oxide semiconductor is lowered by doping zinc oxide with a dopant ion at a concentration at least about 1018 to about 1019 atoms/cm3.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: April 6, 2010
    Inventors: Robert H. Burgener, II, Roger L. Felix, Gary M. Renlund
  • Patent number: 7682857
    Abstract: A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer, the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by ion implantation; removing the through film after the ion implantation; and selectively removing the capping layer using a chemical solution.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: March 23, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihiko Hanamaki, Takehiro Nishida, Makoto Takada, Kenichi Ono
  • Patent number: 7569470
    Abstract: A method of preparing an array of conducting or semi-conducting nanowires may include forming a vicinal surface of stepped atomic terraces on a substrate, and depositing a fractional layer of dopant material to form nanostripes having a width less than the width of the atomic terraces. Diffusion of the atoms of the dopant nanostripes into the substrate may form the nanowires.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: August 4, 2009
    Assignee: The Provost Fellows And Scholars Of The College Of The Holy And Undivided Trinity Of Queen Elizabeth Near Dublin
    Inventors: Sergio Fernandez-Ceballos, Giuseppe Manai, Igor Vasilievich Shvets
  • Patent number: 7553746
    Abstract: A method for manufacturing electrodes on a semiconducting material of type II-VI or on a compound of this material. The electrodes are preferably in gold or platinum and are formed by electrochemical deposition of gold or platinum from a solution of gold or platinum chloride in pure hydrochloric acid.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: June 30, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Gérard Petroz
  • Publication number: 20090134405
    Abstract: A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher than either the first impurity concentration or the third impurity concentration.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 28, 2009
    Inventors: Chiharu OTA, Johji Nishio, Takashi Shinohe
  • Patent number: 7531423
    Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 12, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman, Haining Yang
  • Patent number: 7531440
    Abstract: A semiconductor laser device includes an n-type cladding layer 103 made of n?type (Al0.3Ga0.7)0.5In0.5P, an undoped active layer 104 and a first p-type cladding layer 105 made of p?type (Al0.3Ga0.7)0.5In0.5P. These layers are successively stacked in bottom-to-top order. The active layer 104 has a multi-quantum well structure composed of a first optical guide layer of undoped Al0.4Ga0.6As, a layered structure in which well layers of undoped GaAs and barrier layers of undoped Al0.4Ga0.6As are alternately formed, and a second optical guide layer of undoped Al0.4Ga0.6As. The first optical guide layer, the layered structure and the second optical guide layer are successively stacked in bottom-to-top order.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: May 12, 2009
    Assignee: Panasonic Corporation
    Inventor: Tsutomu Ukai
  • Patent number: 7498230
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: March 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7485560
    Abstract: An amorphous silicon (Si) film is taken to form a metal silicide of Si—Al(aluminum) under a high temperature. Al atoms is diffused into the amorphous Si film for forming the metal silicide of Si—Al as nucleus site. Then through heating and annealing, a microcrystalline or nano-crystalline silicon thin film is obtained. The whole process is only one process and is done in only one reacting chamber.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: February 3, 2009
    Assignee: Atomic Energy Council - Institute of Nuclear Energy Research
    Inventors: Tsun-Neng Yang, Shan-Ming Lan
  • Patent number: 7468315
    Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into an electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: December 23, 2008
    Assignee: Nanosys, Inc.
    Inventors: Mihai A. Buretea, Jian Chen, Calvin Y. H. Chow, Chunming Niu, Yaoling Pan, J. Wallace Parce, Linda T. Romano, David P. Stumbo
  • Patent number: 7384834
    Abstract: A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: June 10, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiro Mitsuda, Mitsuharu Honda, Akira Iizuka
  • Patent number: 7382021
    Abstract: A transistor includes one or more channel taps containing a stack consisting at least in part of a semiconductor an interfacial III-VI layered compound and a conductor. The III-VI compound consists primarily of atoms from Groups IIIA-B and from Group VIA of the Periodic Table of the Elements in an approximate 1:1 ratio. These materials may be formed as layers of covalently bonded elements from Groups IIIA-B and covalently bonded Group VIA elements, adjacent and respective planes of which may be bonded by Van der Waals forces (e.g., to form a single bilayer consisting of a single plane of atoms from Groups IIIA-B and a single plane of Group VIA atoms). One particular III-VI material from which the interfacial layer is made, especially for p-channel transistors, is GaSe. Other III-VI compounds, whether pure compounds or alloys of pure compounds, may also be used.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: June 3, 2008
    Assignee: Acorn Technologies, Inc.
    Inventors: Carl Faulkner, Daniel J. Connelly, Daniel E. Grupp
  • Patent number: 7297625
    Abstract: A method of manufacturing a group III-V crystal is made available by which good-quality group III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. A method of manufacturing a group III-V crystal, characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Additionally, a method of manufacturing a group III-V crystal, characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: November 20, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Publication number: 20070243703
    Abstract: A method of making a semiconductor device includes providing a laminate substrate made by bonding a II-VI or III-V semiconductor laminate film to a support substrate, and preparing the laminate film to enable growth of a II-VI or III-V semiconductor device layer on the laminate substrate.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 18, 2007
    Inventors: Thomas Pinnington, Sean Olson, James M. Zahler, Charles Tsai
  • Patent number: 7250360
    Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: July 31, 2007
    Assignee: Cornell Research Foundation, Inc.
    Inventors: James R. Shealy, Joseph A. Smart
  • Patent number: 7179727
    Abstract: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: February 20, 2007
    Assignee: AdvanceSis Limited
    Inventors: Adam Daniel Capewell, Timothy John Grasby, Evan Hubert Cresswell Parker, Terence Whall
  • Patent number: 7091120
    Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into an electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: August 15, 2006
    Assignee: Nanosys, Inc.
    Inventors: Mihai Buretea, Jian Chen, Calvin Chow, Chunming Niu, Yaoling Pan, J. Wallace Parce, Linda T. Romano, David Stumbo
  • Patent number: 7087474
    Abstract: A method of manufacturing a semiconductor device having a field effect transistor with improved current driving performance (increase of drain current) includes the steps of ion implanting a group IV element from the main surface to the inside of a silicon layer serving as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer serving as a semiconductor substrate so as to form a semiconductor region which is aligned with the gate electrode.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 8, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiro Mitsuda, Mitsuharu Honda, Akira Iizuka
  • Patent number: 7071087
    Abstract: A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1?x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1?x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: July 4, 2006
    Assignee: Witty Mate Corporation
    Inventors: Tsung-Hsi Yang, Chung-Liang Lee, Chu-Shou Yang, Guangli Luo, Wu-Ching Chou, Chun-Yen Chang, Tsung-Yeh Yang
  • Patent number: RE43725
    Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: October 9, 2012
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, Amber Christine Abare, Michael John Bergmann