Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract: An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material.

Abstract: Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner.

Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.

Abstract: A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.

Abstract: In forming a TiN film on a base material (10) by a MOCVD method, a space between a showerhead (3) and a trapping member (5) is heated by a heater (2) up to a temperature at which TDMAT is thermally decomposed, or higher. Next, source gas containing TDMAT, and so on are emitted from the showerhead (3) into a chamber (1). As a result, the TDMAT emitted into the chamber (1) is thermally decomposed into TiN, carbon, and hydrocarbon by the heater (2) in the space between the showerhead (3) and the trapping member (5). Then, the TiN, carbon, and hydrocarbon move toward the base material (10). Then, the carbon and hydrocarbon are trapped by the trapping member (5). On the other hand, the TiN passes through the trapping member (5) without being trapped to reach the base material (10). As a result, a TiN film containing neither carbon nor hydrocarbon grows on a surface of the base material (10).

Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

Abstract: Certain embodiments disclosed herein relate to the formation of multi-component oxide heterostructures (MCOH) using surface nucleation to pattern the atomic layer deposition (ALD) of perovskite material followed by patterned etch and metallization to produce ultra-high density MCOH nano-electronic devices. Applications include ultra-high density MCOH memory and logic, as well as electronic functionality based on single electrons, for example a novel flash memory cell Floating-Gate (FG) transistor with LaAlO3 as a gate tunneling dielectric. Other types of memory devices (DIMMS, DRAM, and DDR) made with patterned ALD of LaAlO3 as a gate dielectric are also possible.

Abstract: A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.

Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi3, CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

Abstract: A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.

Abstract: The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.

Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

Abstract: A layer having a barrier function and catalytic power and excelling in formation uniformity and coverage of an ultrathin film, a pretreatment technique making it possible to form an ultrafine wiring and form a thin seed layer of uniform film thickness and a substrate including a thin seed layer formed with a uniform film thickness by electroless plating by using the aforementioned technique. A substrate in which an alloy film of one or more metal elements, having a barrier function and a metal element or metal elements, having catalytic power with respect to electroless plating is formed by chemical vapor deposition (CVD) on a base to a film thickness of 0.5 nm to 5 nm with a content ratio of the one or more metal element having a barrier function from 5 to 90 at. %.

Abstract: A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract: According to one embodiment, after forming transistors on a semiconductor substrate, a stopper layer and an interlayer insulating film are formed. Then, a contact hole is formed in the interlayer insulating film and a copper film is formed on the interlayer insulating film to bury the inside of the contact hole with copper. After that, the copper film on the interlayer insulating film is removed by low-pressure CMP polishing or ECMP polishing to planarize a surface thereof to form plugs. Thereafter, a barrier metal, a lower electrode, a ferroelectric film, and an upper electrode are formed. In this manner, a semiconductor device (FeRAM) having a ferroelectric capacitor is formed.

Abstract: A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

Abstract: The invention discloses a method for forming a contact hole structure, including: providing a substrate, the substrate having a surface where a metal layer is formed; forming on the surface of the substrate a dielectric layer covering the metal layer; etching the dielectric layer to form a contact hole exposing the metal layer; forming a barrier layer on sidewalls of the contact hole and an exposed surface of the metal layer; removing the barrier layer on the surface of the metal layer by sputtering, and performing sputtering on the metal layer; and, filling the contact hole with an electrically conductive material. The invention protects the dielectric layer from being damaged and improves the quality of the formation of the contact hole, and the sputtering performed on the metal layer and the subsequent filling of the contact hole with the electrically conductive material may use the same apparatus, which reduces processing steps and improves efficiency.

Abstract: A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer.

Abstract: An image sensor having a backside illumination structure can include a photo diode unit in a first wafer, where the photo diode unit includes photo diodes and transfer gate transistors coupled to respective ones of the photo diodes. A wiring line unit can be included on a second wafer that is bonded to the photo diode unit, where the wiring line unit includes wiring lines and transistors configured to process signals provided by the photo diode unit and configured to control the photo diode unit. A supporting substrate is bonded to the wiring line unit and a filter unit is located under the first wafer.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: A semiconductor device enables a barrier layer to fully acquire a barriering property against the diffusion of Cu from a wiring main body and the diffusion of Si from an insulating film, enhances the adhesiveness of the barrier layer and the insulating film and excels in reliability of operation over a long period of time. In this invention, a semiconductor device provided on an insulating film with a wiring includes the insulating film containing silicon, a wiring main body formed of copper in a groove-like opening disposed in the insulating film, and a barrier layer formed between the wiring main body and the insulating film and made of an oxide containing Cu and Si and Mn.

Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.

Abstract: An adhesive flexible barrier film comprises a substrate and a barrier layer disposed on the substrate. The barrier layer is formed from a barrier composition comprising an organosilicon compound. The adhesive flexible barrier film also comprises an adhesive layer disposed on the barrier layer and formed from an adhesive composition. A method of forming the adhesive flexible barrier film comprises the steps of disposing the barrier composition on the substrate to form the barrier layer, disposing the adhesive composition on the barrier layer to form the adhesive layer, and curing the barrier layer and the adhesive layer. The adhesive flexible barrier film may be utilized in organic electronic devices.

Abstract: Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.

Abstract: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.

Abstract: By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.

Abstract: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device including forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350° C. to 400° C. for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150° C. to 300° C. for a time duration between about 24 to about 400 hours.

Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

Abstract: Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.

Abstract: Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.

Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner.

Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: The manufacturing method of the high performance metal-oxide-metal according to the present invention resolves the problems of implementing high capacitance in the metal-oxide-metal region by the steps of filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and fulfilling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor. Using the present method, high-k material and low-k material within the same film layer are realized. High-k material region is used as MOM to achieve high capacitor c, thereby reducing the area used by chips and further improving the electrics performance.

Abstract: The present invention relates to a manufacturing method for a semiconductor device, the method includes a process for forming an interlayer film on a substrate, a process for forming an opening in the interlayer, a process for forming a conductive layer which fills the opening, and a process for forming a cap film on the surface of the conductive layer. In the process for forming the cap film, a reduction process for the surface of the conductive layer and the forming of the film are performed simultaneously.

Abstract: A method of manufacturing a semiconductor device, includes: (a) obtaining a surface of a polishing target, wherein an insulating film and a metal film are exposed; and (b) polishing the surface having the exposed insulating film and the exposed metal film. The step (b) includes; (b1) polishing the surface in a condition with high frictional force, and (b2) polishing the surface in a condition with usual frictional force lower than the high frictional force after the step (b1).

Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.

Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.

Abstract: In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.

Abstract: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.

Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

Abstract: A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.