At Least One Layer Forms A Diffusion Barrier Patents (Class 438/653)
  • Patent number: 12040228
    Abstract: A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: July 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Satoshi Wakatsuki, Tomohisa Iino, Naomi Fukumaki, Misuzu Sato, Masakatsu Takeuchi
  • Patent number: 12037682
    Abstract: A method of forming a structure of a substrate is provided including a tungsten-containing layer including a nucleation layer and a fill layer. The method includes disposing a nucleation layer along sidewalls of the opening, wherein nucleation layer includes boron and tungsten. Disposing the fill layer over the nucleation layer within the opening, wherein a tungsten-containing layer includes a resistivity of about 16 ??·cm or less, wherein a tungsten-containing layer has a thickness of about 200 ? to about 600 ?, and wherein a tungsten-containing layer thickness is half a width of the tungsten-containing layer disposed within the opening between opposing sidewall portions of the opening.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: July 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Peiqi Wang, Cheng Cheng, Kai Wu, Insu Ha, Sang Jin Lee
  • Patent number: 12040224
    Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yunfei Li, Ji Feng, Guohai Zhang, Ching Hwa Tey
  • Patent number: 12033893
    Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
  • Patent number: 12020982
    Abstract: A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 25, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Steven C. H. Hung, Srinivas D. Nemani, Yixiong Yang, Susmit Singha Roy, Nikolaos Bekiaris
  • Patent number: 11984354
    Abstract: A method for forming a self-forming barrier in a feature of a substrate is provided, including the following operations: depositing a metallic liner in the feature of the substrate, the metallic liner being deposited over a dielectric of the substrate; depositing a zinc-containing precursor over the metallic liner; performing a thermal soak of the substrate; repeating the depositing of the zinc-containing precursor and the thermal soak of the substrate for a predefined number of cycles; wherein the method forms a zinc-containing barrier layer at an interface between the metallic liner and the dielectric.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 14, 2024
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Dries Dictus, Yezdi Dordi
  • Patent number: 11984355
    Abstract: A method includes providing a semiconductor structure including a dielectric layer having an opening exposing a top surface of a metal layer. A bottom via is selectively deposited in the opening and over the metal layer. A barrier layer is deposited over the bottom via and in contact with the dielectric layer at a sidewall of the opening. A top via is formed in the opening, in contact with the barrier layer, and over the bottom via. The top via is separated from the dielectric layer by the barrier layer.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kuan Ho, Chia-Tien Wu
  • Patent number: 11978698
    Abstract: A method for forming the packaging structure includes: providing a substrate; forming a plurality of mutually independent conductive wires on the substrate, wherein a trench is provided between adjacent conductive wires; oxidizing side walls of each of the conductive wires to form a barrier layer; and forming a solder mask at least filling the trench.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zengyan Fan
  • Patent number: 11972974
    Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Patent number: 11967523
    Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, alcohol, ester, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Xiangjin Xie, Kevin Kashefi
  • Patent number: 11967625
    Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, the substrate serving as a drain region in the MOSFET device, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 23, 2024
    Assignee: SHANGHAI BRIGHT POWER SEMICONDUCTOR CO., LTD.
    Inventor: Shuming Xu
  • Patent number: 11962016
    Abstract: A film and a manufacturing process thereof, including a base layer, where each of front and back sides of the base layer is provided with a bonding layer, a functional layer, and a protective layer in sequence; the functional layer is composed of a first composite copper layer and/or a second composite copper layer; the first composite copper layer is formed by repeating copper coating on a surface of the bonding layer 2 to 500 times; and the second composite copper layer is formed by repeating copper coating on a surface of the bonding layer 2 to 500 times. The film has low cost, simple process, and prominent appearance performance, and the present disclosure belongs to the technical field of energy storage unit materials.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 16, 2024
    Assignee: SHENZHEN YUANZI TECHNOLOGY CO., LTD.
    Inventor: Ding Wei
  • Patent number: 11961732
    Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Lee, Chung-Chiang Wu, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee
  • Patent number: 11948900
    Abstract: A bonded body according to an embodiment includes a substrate, a metal member, and a bonding layer. The bonding layer is provided between the substrate and the metal member. The bonding layer includes a first particle including carbon, a first region including a metal, and a second region including titanium. The second region is provided between the first particle and the first region. A concentration of titanium in the second region is greater than a concentration of titanium in the first region.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 2, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Maki Yonetsu, Seiichi Suenaga, Sachiko Fujisawa, Takayuki Naba
  • Patent number: 11929282
    Abstract: The method for preparing the semiconductor structure includes: providing a substrate; successively arranging a first conductive material layer, a barrier material layer, a second conductive material layer and a first dielectric material layer on the substrate stacked onto one another; forming a supporting layer on the first dielectric material layer, in which the supporting layer includes a plurality of supporting pattern structures spaced apart from each other, and a first trench is provided between two adjacent supporting pattern structures; forming a second dielectric layer, in which the second dielectric layer fills the first trench; etching the second dielectric layer, the first dielectric material layer, the second conductive material layer, the barrier material layer and the first conductive material layer to form a bit line array; and forming a bit line protective layer.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhaopei Cui, Jingwen Lu
  • Patent number: 11930635
    Abstract: The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhongming Liu, Jia Fang
  • Patent number: 11923290
    Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Siddharth Chouksey, Gilbert Dewey, Nazila Haratipour, Mengcheng Lu, Jitendra Kumar Jha, Jack T. Kavalieros, Matthew V. Metz, Scott B Clendenning, Eric Charles Mattson
  • Patent number: 11923243
    Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
  • Patent number: 11923291
    Abstract: A semiconductor device includes a first substrate, a logical circuit, a first insulating film, a wiring, a plug, and a first layer containing a metal oxide or a metal nitride. The logical circuit is disposed on the first substrate. The first insulating film is disposed above the logical circuit. The wiring includes a first film disposed in the first insulating film, the first film extending in a first direction along an upper surface of the first substrate, and the first film containing a metal, and a first metal layer disposed in the first insulating film via the first film. The plug is disposed under the wiring, extends in a second direction that intersects the first direction, and is electrically connected to the wiring. The first layer is provided between an upper end of the plug and a bottom end of the wiring.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Atsushi Kato
  • Patent number: 11915938
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a metal nitride film substantially not containing a silicon atom on a substrate by sequentially repeating: (a) supplying a metal-containing gas and a reducing gas, which contains silicon and hydrogen and does not contain a halogen, to the substrate in a process chamber by setting an internal pressure of the process chamber to a value which falls within a range of 130 Pa to less than 3,990 Pa during at least the supply of the reducing gas, wherein (a) includes a timing of simultaneously supplying the metal-containing gas and the reducing gas; (b) removing the metal-containing gas and the reducing gas that remain in the process chamber; (c) supplying a nitrogen-containing gas to the substrate; and (d) removing the nitrogen-containing gas remaining in the process chamber.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Arito Ogawa, Atsuro Seino
  • Patent number: 11913107
    Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate can includes selectively etching from a substrate disposed in the PVD chamber an exposed first layer of material, covering an underlying second layer of material, and adjacent to an exposed third layer of material, using both process gas ions and metal ions formed from a target of the PVD chamber, in an amount sufficient to expose the second layer of material while simultaneously depositing a layer of metal onto the third layer of material; and subsequently depositing metal from the target onto the second layer of material.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 27, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yueh Sheng Ow, Yuichi Wada, Junqi Wei, Kang Zhang, Kelvin Boh
  • Patent number: 11916126
    Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
  • Patent number: 11908737
    Abstract: There is provided a technique that performs: (a) forming a first metal film by supplying a plurality of times a first metal-containing gas and a first reducing gas without being mixed with each other to a substrate having a concave portion in a surface of the substrate; and (b) forming a second metal film on the first metal film by supplying a plurality of times at least a second metal-containing gas and a second reducing gas different from the first reducing gas without being mixed with each other or by simultaneously supplying at least a second metal-containing gas and a second reducing gas different from the first reducing gas, to the substrate.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 20, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Arito Ogawa
  • Patent number: 11898081
    Abstract: A ruthenium-etching solution for carrying out an etching process on ruthenium. The etching solution includes orthoperiodic acid and ammonia, in which a pH is 8 or higher and 10 or lower. A method for manufacturing the ruthenium-etching solution, a method for processing an object to be processed including carrying out an etching process on an object to be processed including ruthenium using the ruthenium-etching solution, and a method for manufacturing a ruthenium-containing wiring.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 13, 2024
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Takuya Ohhashi, Yukihisa Wada
  • Patent number: 11887850
    Abstract: Provided are a method of forming a carbon layer and a method of forming an interconnect structure. The method of forming a carbon layer includes providing a substrate including first and second material layers, forming a surface treatment layer on at least one of the first and second material layers, and selectively forming a carbon layer on one of the first material layer and the second material layer. The carbon layer has an sp2 bonding structure.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: January 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin Shin, Keunwook Shin
  • Patent number: 11887943
    Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11887961
    Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Paul Frank, Thomas Heinelt, Oliver Schilling, Sven Schmidbauer, Frank Wagner
  • Patent number: 11881431
    Abstract: A capping layer is on top of a substrate. A first low-k dielectric layer is on top of the capping layer. One or more trenches are within the first low-k dielectric layer. Each of the one or more trenches have a same depth. Each trench of the one or more trenches include a barrier layer on top of the first low-k dielectric layer, a liner layer and a metal layer on top of the liner layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: January 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • Patent number: 11876051
    Abstract: The present application discloses a conductive layer stack, a semiconductor device and methods for fabricating the conductive layer stack and the semiconductor device. The conductive layer stack includes an intervening layer comprising tungsten silicide and positioned on an under-layer; a filler layer comprising tungsten and positioned on the intervening layer. The under-layer comprises titanium nitride and comprises a columnar grain structure. A thickness of the intervening layer is greater than about 4.1 nm.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Che-Hsien Liao, Yueh Hsu
  • Patent number: 11869775
    Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 9, 2024
    Inventors: Seokhyun Lee, Kyoung Lim Suk, Ae-Nee Jang, Jaegwon Jang
  • Patent number: 11854881
    Abstract: Embodiments of the present application relate to a method for manufacturing a semiconductor structure, includes: forming a contact metal layer on a silicon substrate; performing a plasma treatment process, and forming an oxygen isolation layer on a surface of the contact metal layer; and performing a silicidation reaction process, and converting the contact metal layer into a metal silicide layer.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Biao Zhang
  • Patent number: 11854965
    Abstract: Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • Patent number: 11854876
    Abstract: Systems and methods are described for depositing a TiN liner layer and a cobalt seed layer on a semiconductor wafer in a cobalt metallization process. In some embodiments the wafer is cooled after deposition of the TiN liner layer and/or the cobalt seed layer. In some embodiments the TiN liner layer and cobalt seed layer are deposited in process modules that are part of a semiconductor processing apparatus that also includes one or more modules for cooling the substrate. In some embodiments the cobalt seed layer may comprise a mixture of TiN and cobalt, a nanolaminate of TiN and cobalt layers or a graded TiN/Co layer.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: December 26, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Chiyu Zhu, Shinya Iwashita, Jan Willem Maes, Jiyeon Kim
  • Patent number: 11854871
    Abstract: A semiconductor device that includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a conductive feature over the semiconductor substrate and buried in the dielectric layer, and a metal plug over the conductive feature and buried in the dielectric layer, where the dielectric layer has a hydrophobic sidewall facing the metal plug.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal A. Khaderbad, Akira Mineji
  • Patent number: 11856756
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mengdan Zhan
  • Patent number: 11848360
    Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yoshitaka Nakamura, Devesh Dadhich Shreeram, Yi Fang Lee, Scott E. Sills, Jerome A. Imonigie, Kaustubh Shrimali
  • Patent number: 11834738
    Abstract: A sputtering apparatus including a chamber, a gas supply configured to supply the chamber with a first gas and a second inert gas, the first inert gas and the second inert gas having a first evaporation point and second evaporation point, respectively, a plurality of sputter guns in an upper portion of the chamber, a chuck in a lower portion of the chamber and facing the sputter guns, the chuck configured to accommodate a substrate thereon, and a cooling unit connected to a lower portion of the chuck, the cooling unit configured to cool the chuck to a temperature less than the first evaporation point and greater than the second evaporation point, and a method of fabricating a magnetic memory device may be provided.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonmyoung Lee, Whankyun Kim, Eunsun Noh, Jeong-heon Park, Junho Jeong
  • Patent number: 11837663
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
  • Patent number: 11825647
    Abstract: The present disclosure provides a semiconductor device with an air gap for reducing parasitic capacitance between conductive features. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate; a bit line structure disposed over and electrically connected to the first source/drain region; a capacitor contact disposed over and electrically connected to the second source/drain region; a first spacer structure sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure comprises an air gap; and a second spacer structure disposed over the first spacer structure, wherein the air gap is covered by the second spacer structure.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: November 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Patent number: 11823891
    Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 21, 2023
    Assignee: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Tsung-Te Chiu, Kechuang Lin, Houng-Chi Wei, Chia-Chu Kuo, Bing-Han Chuang
  • Patent number: 11818968
    Abstract: Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Tao D. Nguyen, John Mark Meldrim, Aaron K. Belsher
  • Patent number: 11810819
    Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 11810960
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Li Wang, Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Tzer-Min Shen, Pinyen Lin
  • Patent number: 11810857
    Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 11810843
    Abstract: A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: November 7, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11804378
    Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Raghuveer R Patlolla, Donald F Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
  • Patent number: 11800824
    Abstract: Methods of forming a stack without damaging underlying layers are discussed. The encapsulation layer and dielectric layer are highly conformal, have low etch rates, and good hermeticity. These films may be used to protect chalcogen materials in PCRAM devices or any substrates sensitive to oxygen or moisture. Some embodiments utilize a two-step process comprising a first ALD process to form an encapsulation layer and oxidation process to form a dielectric layer.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Maribel Maldonado-Garcia, Cong Trinh, Mihaela A. Balseanu
  • Patent number: 11791396
    Abstract: A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Julien Frougier, Chanro Park
  • Patent number: 11776895
    Abstract: A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: RE49820
    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: January 30, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin