At Least One Layer Forms A Diffusion Barrier Patents (Class 438/653)
  • Patent number: 11322348
    Abstract: A multi-function equipment implements a method of fabricating a thin film. The multi-function equipment according to the invention includes a reaction chamber, a plasma source, a plasma source power generating unit, a bias electrode, an AC (Alternating Current) voltage generating unit, a DC (Direct current) bias generating unit, a metal chuck, a first precursor supply source, a second precursor supply source, a carrier gas supply source, an oxygen supply source, a nitrogen supply source, an inert gas supply source, an automatic pressure controller, and a vacuum pump.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 3, 2022
    Inventor: Miin-Jang Chen
  • Patent number: 11315926
    Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deokhan Bae, Sungmin Kim, Juhun Park, Yuri Lee, Yoonyoung Jung, Sooyeon Hong
  • Patent number: 11309265
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsun Huang, Po-Han Wang, Ing-Ju Lee, Chao-Lung Chen, Cheng-Ming Wu
  • Patent number: 11302867
    Abstract: A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, Ta2O5, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 12, 2022
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Youqing Tang, Zhigang Zhang
  • Patent number: 11282742
    Abstract: A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Patent number: 11244859
    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for forming interconnects using a conductive spacer configured to prevent a short between a via and an adjacent line. In a non-limiting embodiment of the invention, a first conductive line and a second conductive line are formed in a metallization layer. A conductive spacer is formed on the first conductive line and a conductive via is formed on a surface of the conductive spacer. The conductive via is positioned such that the conductive spacer is between the first conductive line and the conductive via. A height of the conductive spacer is selected to provide a predetermined distance from the conductive via to the second conductive line. The predetermined distance from the conductive via to the second conductive line is sufficient to prevent a short between the conductive via and the second conductive line.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Cornelius Brown Peethala, Christopher J. Penny, Nicholas Anthony Lanzillo, Lawrence A. Clevenger
  • Patent number: 11217672
    Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee
  • Patent number: 11217673
    Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deokhan Bae, Sungmin Kim, Juhun Park, Yoonyoung Jung
  • Patent number: 11152259
    Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali Gregoire
  • Patent number: 11088099
    Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: August 10, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 10957779
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Patent number: 10950450
    Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan Srinivasan, Abhijit Basu Mallick, Nicolas Breil
  • Patent number: 10916430
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A source electrode and a drain electrode of a channel-etched transistor are each made to have a stacked-layer structure including a first conductive layer and a second conductive layer. A silicide that contains a metal element contained in the second conductive layer and nitrogen is formed to be in contact with a top surface and a side surface of the second conductive layer. Before etching of the first conductive layer, the silicide is formed by exposing the second conductive layer to an atmosphere containing silane, and plasma treatment is performed in a nitrogen atmosphere without exposure to the air.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Hamochi, Yasutaka Nakazawa, Masami Jintyou, Yukinori Shima
  • Patent number: 10910339
    Abstract: A flip chip bonding method includes obtaining a die including a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer. The curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwail Jin, Yongwon Choi, Myung-Sung Kang, Yeongseok Kim, Wonkeun Kim
  • Patent number: 10903115
    Abstract: Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Conal Murray, Chih-Chao Yang
  • Patent number: 10903421
    Abstract: A method for manufacturing a semiconductor memory device includes forming a bottom electrode on a bottom contact layer, and forming a dielectric layer covering sides of the bottom electrode. In the method, a switching element layer is deposited on the dielectric layer and the bottom electrode, a top electrode layer is deposited on the switching element layer, and a hardmask layer is deposited on the top electrode layer. The switching element, top electrode and hardmask layers are patterned into a pillar on the bottom electrode. The method further includes forming a spacer layer on the dielectric layer on sides of the pillar, and forming a metal layer on the dielectric layer adjacent the spacer layer and around the pillar.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dexin Kong, Juntao Li, Takashi Ando, Kangguo Cheng
  • Patent number: 10886482
    Abstract: A flexible display panel, a manufacturing method thereof and a display device are provided. The flexible display panel includes: a flexible substrate, a first metal layer formed on the substrate, an insulation layer overlying the first metal layer, and a second metal layer disposed on the insulation layer, wherein a plurality of via holes are provided in the insulation layer, the inner wall of each via hole is covered by a stress buffer layer and the second metal layer is formed on the stress buffer layer and connected to the first metal layer through the via holes.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: January 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuai Zhang, Xiaolong Li, Yueping Zuo, Shantao Chen, Qiuhua Meng, Ming Liu
  • Patent number: 10879070
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen
  • Patent number: 10838311
    Abstract: A coating and developing apparatus includes: a processing block having a plurality of substrate transport areas vertically stacked and partitioned from each other; a processing module provided in each of the plurality of substrate transport areas; a transport mechanism configured to transport a substrate between the transport block and the processing module; a temperature adjustment module configured to adjust a temperature of the substrate before the substrate is transported to at least one processing module among the plurality of the processing modules; a temperature sensor configured to detect an atmospheric temperature of at least one substrate transport area; and a temperature controller configured to change the temperature of the substrate in the temperature adjustment module based on the atmospheric temperature detected by the temperature sensor.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keigo Nakano, Koji Takayanagi, Masashi Tsuchiyama
  • Patent number: 10777453
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10741497
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact and interconnect structures and methods of manufacture. The structure includes: a single damascene contact structure in electrical contact with a contact of a source region or drain region; and a single damascene interconnect structure in a wiring layer and in direct electrical contact with the single damascene contact structure.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jim Shih-Chun Liang
  • Patent number: 10707100
    Abstract: A substrate processing method includes: selectively forming a first film on a surface of a substrate disposed in a processing container by plasma enhanced vapor deposition (PECVD); and forming a second film by atomic layer deposition (ALD) in a region of the substrate where the first film does not exist. The second film is formed by repeatedly performing a sequence including: forming a precursor layer on the surface of the substrate; purging an interior of the processing container after forming of the precursor; converting the precursor layer into the second film; and purging a space in the processing container after the converting. A plasma processing apparatus performing the method is also provided.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Toru Hisamatsu
  • Patent number: 10586707
    Abstract: Embodiments of the disclosure relate to selective metal silicide deposition methods. In one embodiment, a substrate having a silicon containing surface is heated and the silicon containing surface is hydrogen terminated. The substrate is exposed to sequential cycles of a MoF6 precursor and a Si2H6 precursor which is followed by an additional Si2H6 overdose exposure to selectively deposit a MoSix material comprising MoSi2 on the silicon containing surface of the substrate. Methods described herein also provide for selective native oxide removal which enables removal of native oxide material without etching bulk oxide materials.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 10, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Raymond Hung, Namsung Kim, Srinivas D. Nemani, Ellie Y. Yieh, Jong Choi, Christopher Ahles, Andrew Kummel
  • Patent number: 10580645
    Abstract: Methods for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. One or more silicon nitride deposition cycle comprise a sequential plasma pretreatment phase in which the substrate is sequentially exposed to a hydrogen plasma and then to a nitrogen plasma in the absence of hydrogen plasma, and a deposition phase in which the substrate is exposed to a silicon precursor. In some embodiments a silicon hydrohalide precursors is used for depositing the silicon nitride. The silicon nitride films may have a high side-wall conformality and in some embodiments the silicon nitride film may be thicker at the bottom of the sidewall than at the top of the sidewall in a trench structure. In gap fill processes, the silicon nitride deposition processes can reduce or eliminate voids and seams.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 3, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Shinya Ueda, Taishi Ebisudani, Toshiya Suzuki
  • Patent number: 10522361
    Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 31, 2019
    Assignee: National Tsing Hua University
    Inventors: Zheng-Yong Liang, Chao-Hui Yeh, Jui-Hsiung Liu, Po-Wen Chiu
  • Patent number: 10515803
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen
  • Patent number: 10475796
    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias individually having an upper horizontal perimeter. The conductive vias individually have an upper horizontal perimeter. Masking material is formed directly above the conductive vias. An opening is formed in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Sanh D. Tang
  • Patent number: 10403500
    Abstract: Provided herein is a method for manufacturing a semiconductor device. The method may include: forming a stack including at least one first material layer and at least one second material layer which are alternately stacked; forming first holes through which the at least one first material layer is exposed; forming etch stop patterns in the respective first holes; forming at least one slit passing through the stack; replacing the at least one first material layer with at least one third material layer through the at least one slit; and forming first contact plugs in the respective first holes, the first contact plugs passing through the etch stop patterns and coupled with the at least one third material layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10373823
    Abstract: In an embodiment, a method includes depositing a silicon matrix on a substrate; exposing the silicon matrix to a first wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber; exposing the silicon matrix to a second wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber, wherein the second wavelength or wavelength range includes a wavelength lower than any wavelength in the first wavelength or wavelength range; exposing the silicon matrix to a third wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber, wherein the third wavelength or wavelength range includes a wavelength lower than any wavelength in the first wavelength or wavelength range and second wavelength or wavelength range; and a repeat exposure of any wavelength range. In some embodiments, a healing operation comprising a deposition operation, a reactive cure, a thermal cure, or a combination thereof may be performed.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Atashi Basu, Pramit Manna, Khokan C. Paul, Diwakar N. Kedlaya
  • Patent number: 10340183
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qiang Fang, Shafaat Ahmed, Zhiguo Sun, Jiehui Shu, Dinesh R. Koli, Wei-Tsu Tseng
  • Patent number: 10340223
    Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 10269705
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yu Cheng, Shih-Kang Tien, Ching-Kun Huang
  • Patent number: 10262865
    Abstract: An example method for manufacturing a semiconductor device includes forming a nitride, carbide, or metal film on a substrate in a chamber using PE-ALD, Pulse-PE-CVD or PE-CVD, purging an interior of the chamber, forming an oxide film on the substrate in the chamber using PE-ALD, Pulse-PE-CVD or PE-CVD, and supplying a reducing gas into the chamber to create a reduction atmosphere and purging the interior of the chamber. The forming of the nitride film, carbide, or metal, purging, forming an oxide film, and supplying the reducing gas may be repeated a plurality of times.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: April 16, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Atsuki Fukazawa, Toshihisa Nozawa
  • Patent number: 10256171
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10233543
    Abstract: The present disclosure relates to a semiconductor processing apparatus. The processing chamber includes a chamber body and lid defining an interior volume, a substrate support disposed in the interior volume and a showerhead assembly disposed between the lid and the substrate support. The showerhead assembly includes a faceplate configured to deliver a process gas to a processing region defined between the showerhead assembly and the substrate support and a underplate positioned above the faceplate, defining a first plenum between the lid and the underplate, the having multiple zones, wherein each zone has a plurality of openings that are configured to pass an amount of inert gas from the first plenum into a second plenum defined between the faceplate and the underplate, in fluid communication with the plurality of openings of each zone such that the inert gas mixes with the process gas before exiting the showerhead assembly.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Sanjeev Baluja, Sam H. Kim, Tuan Anh Nguyen
  • Patent number: 10177307
    Abstract: Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghoon Bak, Myoungsu Son, Boyoung Seo
  • Patent number: 10157787
    Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 18, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jin Hee Park, Tae Hong Ha, Sang-Hyeob Lee, Thomas Jongwan Kwon, Jaesoo Ahn, Xianmin Tang, Er-Xuan Ping, Sree Kesapragada
  • Patent number: 10109490
    Abstract: Methods for forming interconnects that include cobalt. An interconnect opening is formed in a dielectric layer that penetrates from a top surface of the dielectric layer into the dielectric layer. A first cobalt layer is formed at a bottom of the interconnect opening and partially fills the interconnect opening. A second cobalt layer is selectively deposited on the first cobalt layer and grows upwardly from the first cobalt layer at the bottom of the interconnect opening.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sean X. Lin, Xunyuan Zhang
  • Patent number: 10079210
    Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Electroics Co., Ltd.
    Inventors: Do-sun Lee, Do-hyun Lee, Chul-sung Kim, Sang-jin Hyun, Joon-gon Lee
  • Patent number: 10062564
    Abstract: According to one embodiment of the invention, a method is provided for selective surface deposition. In one example, the method includes providing a substrate containing a first material having a first surface and a second material having a second surface, forming a modified first surface and a modified second surface by exposing the first surface and the second surface to hydrogen gas excited by a plasma source, and selectively depositing a film on the modified second surface but not on the modified first surface.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 28, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 10014212
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 3, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 9984926
    Abstract: A semiconductor device manufacturing method includes providing a wafer, which includes a semiconductor substrate, a semiconductor device located on the semiconductor substrate, an interlayer dielectric layer covering the semiconductor device, and a through hole penetrating through the interlayer dielectric layer and a portion of the semiconductor substrate. A metal layer is formed inside the through hole and on a surface of the interlayer dielectric layer. A first planarization process is conducted to remove a portion of the metal layer on the surface of the interlayer dielectric layer. The method also includes conducting an annealing alloy treatment and conducting a second planarization process to completely remove the metal layer on the surface of the interlayer dielectric layer. The manufacturing methods can slowly release stress of the wafer and effectively prevent cracks in silicon vias, thereby reducing TSV leakage problems, thus improving the reliability and yield of the devices.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xiaotian Ma, Yan Gao, Liang Wang
  • Patent number: 9984887
    Abstract: A method of manufacturing a semiconductor device includes: forming a film on a substrate by time-divisionally and sequentially performing: (a) supplying a precursor gas to the substrate and causing precursor molecules, which are contained in the precursor gas and which contains a main element and ligands, to be adsorbed onto the substrate; (b) supplying a compound containing an electron withdrawing group to the substrate onto which the precursor molecules are adsorbed, and causing the compound containing the electron withdrawing group to be adsorbed to the ligands contained in the precursor molecules; and (c) supplying a reaction gas to the substrate onto which the precursor molecules and the compound containing the electron withdrawing group are adsorbed, causing the ligands and the compound containing the electron withdrawing group to be desorbed from the substrate, and causing the main element contained in the precursor molecules to react with the reaction gas.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Motomu Degai
  • Patent number: 9960080
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 1, 2018
    Assignee: IMEC vzw
    Inventor: Eric Beyne
  • Patent number: 9941283
    Abstract: A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the substrate, covering the first fin-type pattern and including a first trench, the first trench intersecting the first fin-type pattern, a first gate electrode on the first fin-type pattern, filling the first trench, an upper surface of the first gate electrode being coplanar with an upper surface of the first interlayer insulating layer, a capping layer extending along the upper surface of the first interlayer insulating layer and along the upper surface of the first gate electrode, and a second interlayer insulating layer on the capping layer, the second interlayer insulating layer including a material different from that of the capping layer.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju-Youn Kim
  • Patent number: 9941367
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 9887229
    Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 6, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chia-Ming Cheng
  • Patent number: 9842805
    Abstract: Techniques for forming Cu interconnects in a dielectric are provided. In one aspect, a method of forming a Cu interconnect structure includes: forming at least one trench in a dielectric; depositing a metal liner into the trench; depositing a Mn-containing seed layer on the metal liner within the trench; annealing the Mn-containing seed layer under conditions sufficient to diffuse Mn from the Mn-containing seed layer to an interface between the dielectric and the metal liner forming a barrier layer between the dielectric and the metal liner; and depositing Cu into the trench to form the Cu interconnect, wherein the Cu is deposited into the trench after the annealing is performed. The metal liner may optionally be reflowed such that it is thicker at a bottom of the trench than along sidewalls of the trench. A Cu interconnect structure is also provided.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Chih-Chao Yang
  • Patent number: 9818704
    Abstract: A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Yao Wang, Ying-Han Chiou, Ling-Sung Wang
  • Patent number: RE47630
    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin