At Least One Layer Forms A Diffusion Barrier Patents (Class 438/653)
  • Patent number: 12293971
    Abstract: Embodiments of the present application provide a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes: providing a substrate, a dielectric layer on the substrate, the dielectric layer having a trench; forming a metallic copper layer filling the trench; forming a contact layer on an upper surface of the metallic copper layer, a material of the contact layer containing cuprous ions; and forming a barrier layer on an upper surface of the contact layer, a material of the barrier layer containing a same element as the material of the contact layer. The embodiments of the present application help improve a contact effect between the metallic copper layer and the barrier layer.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: May 6, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhongdi Tang
  • Patent number: 12274051
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include an array of memory cells and a transistor located on a periphery of the array of memory cells. A number of data lines are shown coupled to memory cells in the array, wherein the number of data lines extend over a first metal gate of a transistor in the periphery of the array, where the number of data lines are formed from a second metal, and form a direct interface with the first metal gate.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hyucksoo Yang, Jongpyo Kim, Byung Yoon Kim
  • Patent number: 12272659
    Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: April 8, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi Xu, Yu Lei, Zhimin Qi, Aixi Zhang, Xianyuan Zhao, Wei Lei, Xingyao Gao, Shirish A. Pethe, Tao Huang, Xiang Chang, Patrick Po-Chun Li, Geraldine Vasquez, Dien-yeh Wu, Rongjun Wang
  • Patent number: 12261117
    Abstract: A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 25, 2025
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaharu Yamaji, Taichi Karino, Hitoshi Sumida, Hideaki Itoh
  • Patent number: 12261130
    Abstract: A semiconductor device may include first wiring lines, a plurality of second wiring lines located over the first wiring lines, an interlayer insulating layer comprising a first portion, the first portion located in a gap between second wiring lines that neighbor each other in the first direction and a first auxiliary wiring line electrically coupling the first wiring lines.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 25, 2025
    Assignee: SK hynix Inc.
    Inventor: Yeo Jin Jeong
  • Patent number: 12255144
    Abstract: A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Chih-Chien Chi, Ming-Hsing Tsai
  • Patent number: 12255139
    Abstract: A semiconductor device including a first insulating structure on a substrate and including a first etch stop layer and a first interlayer insulating layer on the first etch stop layer, a second insulating structure on the first insulating structure and including a second etch stop layer and a second interlayer insulating layer on the second etch stop layer, a conductive line penetrating through the second insulating structure, and extending in a first direction parallel to an upper surface of the substrate, and a plurality of contacts penetrating through the first insulating structure and connected to the conductive line may be provided. The conductive line may include a protrusion extending below the second insulating structure and penetrating through the first interlayer insulating layer to be in contact with the first etch stop layer.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: March 18, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Anthony Dongick Lee, Sangcheol Na, Kichul Park, Sungyup Jung, Youngwoo Cho
  • Patent number: 12243779
    Abstract: A method for manufacturing a semiconductor structure, including: providing a base; forming a Through Silicon Via (TSV) in the base, with a depth of the TSV being less than a thickness of the base; and forming a liner layer on a sidewall and the bottom of the TSV, and forming a conductive layer in the TSV, the liner layer including a polish-stop layer.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: March 4, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Shuangshuang Wu, Tzung-Han Lee
  • Patent number: 12237384
    Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a gate structure and a self-aligned contact structure. The substrate includes a source region and a drain region; the gate structure is formed on the substrate and are located between the source region and the drain region; and the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure sequentially connected in a direction perpendicular to the substrate, the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: February 25, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 12237224
    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • Patent number: 12237217
    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 12225706
    Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming a first insulating layer covering the substrate, and patterning the first insulating layer to form a plurality of vias and a plurality of isolation structures that are alternatingly distributed; forming conductive contact plugs in the vias respectively, where the conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover outer walls of the isolation structures and extend along the outer walls to surfaces of the isolation structures distal from the substrate; and forming a passivation layer covering side walls and surfaces of the conductive contact plugs.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: February 11, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhengqing Sun, Xing Jin
  • Patent number: 12218182
    Abstract: Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: February 4, 2025
    Assignee: SK hynix Inc.
    Inventors: Kwan Woo Do, Wan Joo Maeng, Jeong Yeop Lee, Ki Vin Im
  • Patent number: 12205900
    Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: January 21, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Jivaan Kishore Jhothiraman, Rutuparna Narulkar, Chandra S. Tiwari
  • Patent number: 12205893
    Abstract: A method for forming a semiconductor structure includes: providing a substrate, and forming a dielectric layer and a mask layer, where the mask layer is arranged with a first opening; forming a first barrier layer on a sidewall of the first opening, where the first barrier layer surrounds and forms a second opening; forming a second barrier layer filling the second opening; removing the first barrier layer and the second barrier layer by a first etching process until the first barrier layer or the second barrier layer is completely removed; and removing the dielectric layer exposed by the first opening and part of the substrate exposed by the first opening to form a bit-line contact opening.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 21, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tianlei Mu
  • Patent number: 12205909
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: January 21, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai
  • Patent number: 12205901
    Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jheng-Hong Jiang, Chia-Wei Liu, Shing-Huang Wu
  • Patent number: 12198979
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Patent number: 12199124
    Abstract: An imaging device includes a semiconductor substrate and pixels. Each of the pixels includes a first capacitive element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one selected from the group consisting of the first electrode and the second electrode has a first electrical contact point electrically connected to a first electrical element and a second electrical contact point electrically connected to a second electrical element different from the first electrical element. The first capacitive element includes at least one trench portion having a trench shape.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: January 14, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuuko Tomekawa, Yoshihiro Sato
  • Patent number: 12183628
    Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuan-Wei Huang, Yi-Nien Su, Yu-Yu Chen, Jyu-Horng Shieh
  • Patent number: 12173413
    Abstract: Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 24, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Amrita B. Mullick, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 12170246
    Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Patent number: 12167612
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 10, 2024
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Patent number: 12159846
    Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 3, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Allen Faust, Robert Martin Higgins, Anagha Shashishekhar Kulkarni, Jonathan Philip Davis, Sudtida Lavangkul, Andrew Frank Burnett
  • Patent number: 12148831
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Meng-Chun Chang
  • Patent number: 12148657
    Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Yi-Tang Chen, Da-Wei Lin
  • Patent number: 12148810
    Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
  • Patent number: 12148660
    Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: November 19, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Roey Shaviv, Suketu Arun Parikh, Feng Chen, Lu Chen
  • Patent number: 12142521
    Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Tung-Ying Lee, Yu-Chao Lin
  • Patent number: 12142516
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: November 12, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Nicholas V. LiCausi, Guillaume Bouche, Lars W. Liebmann
  • Patent number: 12136545
    Abstract: Described herein is a technique capable of forming a film so as to fill an inside of a recess provided on a surface of a substrate. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) forming a film by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a gas to a substrate in a process chamber; and (a-2) vacuum-exhausting an inner atmosphere of the process chamber; and (b) generating a predetermined temperature difference between a front surface of the substrate and a back surface of the substrate at a predetermined timing during (a).
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 5, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Takashi Yahata, Toshiyuki Kikuchi
  • Patent number: 12132016
    Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 12119226
    Abstract: A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: October 15, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yexiao Yu, Zhongming Liu, Jia Fang
  • Patent number: 12119302
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having plurality of contacts, a plurality of composite plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the substrate; and a plurality of air gaps positioned above the substrate. At least one of the plurality of composite plugs includes a protection liner having a U-shaped profile and a metal plug in the protection liner, and the protection liner is in direct contact with one of the plurality of contacts.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: October 15, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: 12107004
    Abstract: A semiconductor structure including a self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion is provided. The semiconductor structure includes a substrate and a first dielectric layer on the substrate. A contact structure is embedded in the first dielectric layer and includes a conductive line. The semiconductor structure further includes a self-assembled monolayer on the conductive line, and a second dielectric layer on the first dielectric layer and the conductive line. The self-assembled monolayer is chemically bonded to the conductive line and the second dielectric layer.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Patent number: 12104260
    Abstract: A method for producing a semiconductor element and a chemical solution to be used in the method for producing a semiconductor element, the method including dry-etching or chemically-mechanically polishing a ruthenium-containing layer located as an uppermost layer of a substrate; and bringing a surface of the substrate into contact with a chemical solution thereby satisfactorily cleaning and removing a ruthenium residue formed on the surface of the substrate; and a chemical solution to be suitably used in the method for producing a semiconductor element.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 1, 2024
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yukihisa Wada, Kazuhiro Takahashi
  • Patent number: 12107050
    Abstract: Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: October 1, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh
  • Patent number: 12087624
    Abstract: A dielectric layer is located on top of and in contact with a substrate. A conductive line located within the dialectic layer. A barrier layer on top of an in contact with the dielectric layer. The barrier layer is below the conductive line. A liner layer on top of and in contact with the barrier layer and below and in contact with the conductive line. A metal liner on top of and in contact with the conductive line. A capping layer on top of and in contact with the dielectric layer, the barrier layer, the liner layer, and the metal liner.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: September 10, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • Patent number: 12087685
    Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: September 10, 2024
    Assignee: Tessera LLC
    Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
  • Patent number: 12080648
    Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Yang Cao, Akm Shaestagir Chowdhury, Jeff Grunes
  • Patent number: 12080454
    Abstract: An integrated circuit includes a thin film resistor body that is formed over a dielectric layer. An interfacial layer is formed on the thin film resistor body and resistor heads are formed on the interfacial layer. The thin film resistor body includes nickel chromium aluminum (NiCrAl) and the resistor heads include titanium tungsten (TiW).
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: September 3, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gernot Manfred Bauer, Kai-Alexander Schachtschneider
  • Patent number: 12080598
    Abstract: A method for preparing a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate; forming a first conductive plug in the first dielectric layer; forming a polysilicon layer covering the first dielectric layer and the first conductive plug; transforming a portion of the polysilicon layer into a silicide portion; forming a second conductive plug directly over the silicide portion; and forming a second dielectric layer surrounding the second conductive plug.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: September 3, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Cheng Liao
  • Patent number: 12077852
    Abstract: Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at. % of boron in the doped-boron material.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 3, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Aykut Aydin, Rui Cheng, Karthik Janakiraman
  • Patent number: 12074023
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: August 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
  • Patent number: 12068194
    Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Pang Kuo, Ya-Lien Lee, Chieh-Yi Shen
  • Patent number: 12057416
    Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: August 6, 2024
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Mitsuhiko Sakai
  • Patent number: 12057344
    Abstract: A method includes forming a gate stack over a substrate and a gate spacer on a sidewall of the gate stack; forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region; forming a protective layer over the gate stack and in contact with a top surface of the gate spacer; removing the first interlayer dielectric layer after forming the protective layer; forming an etch stop layer over the protective layer; forming a second interlayer dielectric layer over the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form an opening that exposes a top surface of the protective layer; and forming a contact plug in the opening.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Wai-Yi Lien, Yu-Ming Lin
  • Patent number: 12054845
    Abstract: A metal coated article includes a platinum-group metal region adjacent a refractory metal region, which is adjacent a substrate comprising an inorganic material. A refractory metal carbide layer is adjacent the substrate and the refractory metal layer is adjacent the refractory metal carbide layer. The platinum-group metal region comprises a refractory metal/platinum-group metal layer and a platinum-group metal layer. Related methods are also disclosed.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: August 6, 2024
    Assignee: Battelle Energy Alliance, LLC
    Inventor: Prabhat K. Tripathy
  • Patent number: 12051659
    Abstract: Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsun Huang, Po-Han Wang, Ing-Ju Lee, Chao-Lung Chen, Cheng-Ming Wu
  • Patent number: 12037682
    Abstract: A method of forming a structure of a substrate is provided including a tungsten-containing layer including a nucleation layer and a fill layer. The method includes disposing a nucleation layer along sidewalls of the opening, wherein nucleation layer includes boron and tungsten. Disposing the fill layer over the nucleation layer within the opening, wherein a tungsten-containing layer includes a resistivity of about 16 ??·cm or less, wherein a tungsten-containing layer has a thickness of about 200 ? to about 600 ?, and wherein a tungsten-containing layer thickness is half a width of the tungsten-containing layer disposed within the opening between opposing sidewall portions of the opening.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: July 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Peiqi Wang, Cheng Cheng, Kai Wu, Insu Ha, Sang Jin Lee