At Least One Layer Forms A Diffusion Barrier Patents (Class 438/653)
  • Patent number: 10403500
    Abstract: Provided herein is a method for manufacturing a semiconductor device. The method may include: forming a stack including at least one first material layer and at least one second material layer which are alternately stacked; forming first holes through which the at least one first material layer is exposed; forming etch stop patterns in the respective first holes; forming at least one slit passing through the stack; replacing the at least one first material layer with at least one third material layer through the at least one slit; and forming first contact plugs in the respective first holes, the first contact plugs passing through the etch stop patterns and coupled with the at least one third material layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10373823
    Abstract: In an embodiment, a method includes depositing a silicon matrix on a substrate; exposing the silicon matrix to a first wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber; exposing the silicon matrix to a second wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber, wherein the second wavelength or wavelength range includes a wavelength lower than any wavelength in the first wavelength or wavelength range; exposing the silicon matrix to a third wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber, wherein the third wavelength or wavelength range includes a wavelength lower than any wavelength in the first wavelength or wavelength range and second wavelength or wavelength range; and a repeat exposure of any wavelength range. In some embodiments, a healing operation comprising a deposition operation, a reactive cure, a thermal cure, or a combination thereof may be performed.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Atashi Basu, Pramit Manna, Khokan C. Paul, Diwakar N. Kedlaya
  • Patent number: 10340183
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qiang Fang, Shafaat Ahmed, Zhiguo Sun, Jiehui Shu, Dinesh R. Koli, Wei-Tsu Tseng
  • Patent number: 10340223
    Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 10269705
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yu Cheng, Shih-Kang Tien, Ching-Kun Huang
  • Patent number: 10262865
    Abstract: An example method for manufacturing a semiconductor device includes forming a nitride, carbide, or metal film on a substrate in a chamber using PE-ALD, Pulse-PE-CVD or PE-CVD, purging an interior of the chamber, forming an oxide film on the substrate in the chamber using PE-ALD, Pulse-PE-CVD or PE-CVD, and supplying a reducing gas into the chamber to create a reduction atmosphere and purging the interior of the chamber. The forming of the nitride film, carbide, or metal, purging, forming an oxide film, and supplying the reducing gas may be repeated a plurality of times.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: April 16, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Atsuki Fukazawa, Toshihisa Nozawa
  • Patent number: 10256171
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10233543
    Abstract: The present disclosure relates to a semiconductor processing apparatus. The processing chamber includes a chamber body and lid defining an interior volume, a substrate support disposed in the interior volume and a showerhead assembly disposed between the lid and the substrate support. The showerhead assembly includes a faceplate configured to deliver a process gas to a processing region defined between the showerhead assembly and the substrate support and a underplate positioned above the faceplate, defining a first plenum between the lid and the underplate, the having multiple zones, wherein each zone has a plurality of openings that are configured to pass an amount of inert gas from the first plenum into a second plenum defined between the faceplate and the underplate, in fluid communication with the plurality of openings of each zone such that the inert gas mixes with the process gas before exiting the showerhead assembly.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Sanjeev Baluja, Sam H. Kim, Tuan Anh Nguyen
  • Patent number: 10177307
    Abstract: Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghoon Bak, Myoungsu Son, Boyoung Seo
  • Patent number: 10157787
    Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 18, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jin Hee Park, Tae Hong Ha, Sang-Hyeob Lee, Thomas Jongwan Kwon, Jaesoo Ahn, Xianmin Tang, Er-Xuan Ping, Sree Kesapragada
  • Patent number: 10109490
    Abstract: Methods for forming interconnects that include cobalt. An interconnect opening is formed in a dielectric layer that penetrates from a top surface of the dielectric layer into the dielectric layer. A first cobalt layer is formed at a bottom of the interconnect opening and partially fills the interconnect opening. A second cobalt layer is selectively deposited on the first cobalt layer and grows upwardly from the first cobalt layer at the bottom of the interconnect opening.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sean X. Lin, Xunyuan Zhang
  • Patent number: 10079210
    Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Electroics Co., Ltd.
    Inventors: Do-sun Lee, Do-hyun Lee, Chul-sung Kim, Sang-jin Hyun, Joon-gon Lee
  • Patent number: 10062564
    Abstract: According to one embodiment of the invention, a method is provided for selective surface deposition. In one example, the method includes providing a substrate containing a first material having a first surface and a second material having a second surface, forming a modified first surface and a modified second surface by exposing the first surface and the second surface to hydrogen gas excited by a plasma source, and selectively depositing a film on the modified second surface but not on the modified first surface.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 28, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 10014212
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 3, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 9984926
    Abstract: A semiconductor device manufacturing method includes providing a wafer, which includes a semiconductor substrate, a semiconductor device located on the semiconductor substrate, an interlayer dielectric layer covering the semiconductor device, and a through hole penetrating through the interlayer dielectric layer and a portion of the semiconductor substrate. A metal layer is formed inside the through hole and on a surface of the interlayer dielectric layer. A first planarization process is conducted to remove a portion of the metal layer on the surface of the interlayer dielectric layer. The method also includes conducting an annealing alloy treatment and conducting a second planarization process to completely remove the metal layer on the surface of the interlayer dielectric layer. The manufacturing methods can slowly release stress of the wafer and effectively prevent cracks in silicon vias, thereby reducing TSV leakage problems, thus improving the reliability and yield of the devices.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xiaotian Ma, Yan Gao, Liang Wang
  • Patent number: 9984887
    Abstract: A method of manufacturing a semiconductor device includes: forming a film on a substrate by time-divisionally and sequentially performing: (a) supplying a precursor gas to the substrate and causing precursor molecules, which are contained in the precursor gas and which contains a main element and ligands, to be adsorbed onto the substrate; (b) supplying a compound containing an electron withdrawing group to the substrate onto which the precursor molecules are adsorbed, and causing the compound containing the electron withdrawing group to be adsorbed to the ligands contained in the precursor molecules; and (c) supplying a reaction gas to the substrate onto which the precursor molecules and the compound containing the electron withdrawing group are adsorbed, causing the ligands and the compound containing the electron withdrawing group to be desorbed from the substrate, and causing the main element contained in the precursor molecules to react with the reaction gas.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Motomu Degai
  • Patent number: 9960080
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 1, 2018
    Assignee: IMEC vzw
    Inventor: Eric Beyne
  • Patent number: 9941283
    Abstract: A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the substrate, covering the first fin-type pattern and including a first trench, the first trench intersecting the first fin-type pattern, a first gate electrode on the first fin-type pattern, filling the first trench, an upper surface of the first gate electrode being coplanar with an upper surface of the first interlayer insulating layer, a capping layer extending along the upper surface of the first interlayer insulating layer and along the upper surface of the first gate electrode, and a second interlayer insulating layer on the capping layer, the second interlayer insulating layer including a material different from that of the capping layer.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju-Youn Kim
  • Patent number: 9941367
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 9887229
    Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 6, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chia-Ming Cheng
  • Patent number: 9842805
    Abstract: Techniques for forming Cu interconnects in a dielectric are provided. In one aspect, a method of forming a Cu interconnect structure includes: forming at least one trench in a dielectric; depositing a metal liner into the trench; depositing a Mn-containing seed layer on the metal liner within the trench; annealing the Mn-containing seed layer under conditions sufficient to diffuse Mn from the Mn-containing seed layer to an interface between the dielectric and the metal liner forming a barrier layer between the dielectric and the metal liner; and depositing Cu into the trench to form the Cu interconnect, wherein the Cu is deposited into the trench after the annealing is performed. The metal liner may optionally be reflowed such that it is thicker at a bottom of the trench than along sidewalls of the trench. A Cu interconnect structure is also provided.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Chih-Chao Yang
  • Patent number: 9818704
    Abstract: A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Yao Wang, Ying-Han Chiou, Ling-Sung Wang
  • Patent number: 9793193
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 9748137
    Abstract: Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. Methods may also involve using a remote plasma source to generate the nitrogen-based plasma. Methods also involve annealing the substrate.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: August 29, 2017
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Jeong-Seok Na, Raihan Tarafdar, Raashina Humayun, Michal Danek
  • Patent number: 9695347
    Abstract: Provided is a slurry composition for chemical mechanical polishing (CMP) of a metal. The slurry composition comprises a copolymer whose average molecular weight is from about 600,000 to about 1,300,000 and whose monomers are acrylic acid and acrylamide in a molar ratio of about 1:30 to about 30:1. The slurry composition exhibits a non-Prestonian behavior to achieve minimized dishing and attain a high degree of planarization.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: July 4, 2017
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Homer Chou, Won Lae Kim, Jong Il Noh, In Kyung Lee, Tae Young Lee
  • Patent number: 9653347
    Abstract: After forming source/drain contact structures within an interlevel dielectric (ILD) layer to contact source/drain regions of a field effect transistor (FET), the ILD layer is recessed to expose upper portions of the source/drain contact structures. A sacrificial layer is then formed on a remaining portion of the ILD layer to laterally surround the upper portions of the source/drain contact structures. An interconnect conductor portion is subsequently formed to contact the source/drain contact structures by subtractive patterning of a metal layer that is formed on the sacrificial layer. Next, the sacrificial layer is removed, leaving a void between the interconnect conductor portion and the remaining portion of the ILD layer. A interconnect liner layer is then formed on a top surface and sidewalls of the interconnect conductor portion and on the remaining portion of the ILD layer. The interconnect liner layer encloses an air gap surrounding the upper portions of the source/drain contact structures.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 9601432
    Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9583338
    Abstract: According to the present disclosure, a film containing a predetermined element, carbon and nitrogen is formed with high controllability of a composition thereof. A method of manufacturing a semiconductor device includes forming a film containing a predetermined element, carbon and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a first processing gas containing the predetermined element and a halogen element to the substrate, supplying a second processing gas composed of three elements of carbon, nitrogen and hydrogen to the substrate, and supplying a third processing gas containing carbon to the substrate.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: February 28, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Tatsuru Matsuoka
  • Patent number: 9530736
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 9502263
    Abstract: Implementations described herein generally relate to methods for depositing etch stop layers, such as AlN layers, using UV assisted CVD. Methods disclosed herein generally include positioning a substrate in a process region of a process chamber; delivering an aluminum-containing precursor to the process region, the aluminum-containing precursor depositing an aluminum species onto the substrate; purging the process region of aluminum-containing precursor using an inert gas; delivering a UV responsive nitrogen-containing precursor to the process region, the UV responsive nitrogen-containing gas being activated using UV radiation to create nitrogen radicals, the nitrogen radicals reacting with the aluminum species to form an AlN layer; and purging the process region of UV responsive nitrogen-containing precursor using an inert gas.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: November 22, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Alexandros T. Demos, Deenesh Padhi
  • Patent number: 9425129
    Abstract: Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes a dopant and at least one trench formed in the substrate; providing an undoped semiconductor layer over a surface of the substrate within the trench; and providing a conductive material on top of dielectric layer in the trench, the conductive material forming the conductive via. The undoped semiconductor layer, having no dopant, reduces a parasitic capacitance between the conductive via and the substrate. The undoped semiconductor layer may also prevent migration of dopant from the substrate into the undoped semiconductor layer, further reducing capacitance in the circuit structure.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Bingwu Liu, Dingyou Zhang
  • Patent number: 9385034
    Abstract: An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Ting-Yu Shen, Yung-Cheng Lu
  • Patent number: 9343364
    Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 17, 2016
    Assignee: SK HYNIX INC.
    Inventor: Byung Wook Bae
  • Patent number: 9343523
    Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: May 17, 2016
    Assignee: Intermolecular, Inc.
    Inventor: Prashant B. Phatak
  • Patent number: 9287133
    Abstract: A method for hard mask layer removal includes dispensing a chemical on a hard mask layer, in which the chemical includes an acidic chemical. The chemical is drained from a chamber after hard mask removal.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Hsueh Changchien, Yu-Ming Lee, Chi-Ming Yang
  • Patent number: 9275894
    Abstract: In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate. The dielectric layer has at least one first trench in the dielectric layer. The method also includes forming a seed layer on a sidewall and a bottom surface of the first trench. The method further includes forming a first conductive layer on the seed layer. The method includes performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive layer. The method also includes forming a third conductive layer on the second conductive layer to fill the first trench.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Feng Lin, Kuan-Chia Chen, Ching-Hua Hsieh
  • Patent number: 9275898
    Abstract: Methods of forming a Co cap on a Cu interconnect in or through an ULK ILD with improved selectivity while protecting an ULK ILD surface are provided. Embodiments include providing a Cu filled via in an ULK ILD; depositing a Co precursor and H2 over the Cu-filled via and the ULK ILD, the Co precursor and H2 forming a Co cap over the Cu-filled via; depositing an UV cured methyl over the Co cap and the ULK ILD; performing an NH3 plasma treatment after depositing the UV cured methyl; and repeating the steps of depositing a Co precursor through performing an NH3 plasma treatment to remove impurities from the Co cap.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Zhiguo Sun, Yang Bum Lee, Huang Liu
  • Patent number: 9209029
    Abstract: An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: December 8, 2015
    Assignee: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Cheng Hu, Lun Zhu, Zhiwei Zhu, Shili Zhang, Wei Zhang
  • Patent number: 9107329
    Abstract: Disclosed herein is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment layer on the first connection pads; forming a protective film on the solder resist layer; forming a second opening for exposing the second connection pads in the protective film and the solder resist layer; and forming a second surface treatment layer on the second connection pads.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 11, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chang Bo Lee, Dae Jo Hong, Cheol Ho Choi
  • Patent number: 9099472
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Patent number: 9058983
    Abstract: In some examples, a process to generate an in-situ hardmask layer on porous dielectric materials using the densifying action of a plasma in conjunction with a sacrificial polymeric filler, the latter which enables control of the hardmask thickness as well as a well-defined interface with the underlying ILD.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Geraud Jean-Michel Dubois, Theo J. Frot, Teddie P. Magbitang, Willi Volksen
  • Publication number: 20150147879
    Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.
    Type: Application
    Filed: September 11, 2014
    Publication date: May 28, 2015
    Inventors: Amit Chatterjee, Geetika Bajaj, Pramit Manna, He Ren, Tapash Chakraborty, Srinivas D. Nemani, Mehul Naik, Robert Jan visser, Abhijit Basu Mallick
  • Publication number: 20150137372
    Abstract: Methods for forming a self-forming barrier layer and the resulting devices are disclosed. Embodiments may include forming a metal line above a substrate, forming a reagent layer above the metal line and the substrate, forming a dielectric layer on the reagent layer, and transforming the reagent layer into a self-forming barrier layer.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Moosung M. CHAE
  • Publication number: 20150137373
    Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Xunyuan Zhang, Xiuyu Cai, Hoon Kim
  • Publication number: 20150137374
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen CHEN, Jeffrey P. GAMBINO, Zhong-Xiang HE, Trevor A. THOMPSON, Eric J. WHITE
  • Patent number: 9034752
    Abstract: Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 9034756
    Abstract: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming Han Lee
  • Publication number: 20150132947
    Abstract: A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 14, 2015
    Inventors: Chao-Hsien Peng, Chi-Liang Kuo, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9029258
    Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Lam Research Corporation
    Inventors: Praveen Reddy Nalla, Novy Sastrawati Tjokro, Artur Kolics, Seshasayee Varadarajan
  • Patent number: RE47630
    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin