At Least One Layer Forms A Diffusion Barrier Patents (Class 438/653)
  • Patent number: 11664271
    Abstract: A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Oscar van der Straten, Joseph F. Maniscalco, Alexander Reznicek, Raghuveer Reddy Patlolla, Theodorus E. Standaert
  • Patent number: 11655537
    Abstract: Methods for filling a substrate feature with a carbon gap fill, while leaving a void, are described. Methods comprise flowing a process gas into a high density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber housing a substrate having at least one feature, the process gas comprising a hydrocarbon reactant, generating a plasma, and depositing a carbon film.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 23, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick
  • Patent number: 11652072
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: May 16, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Tonegawa, Hiroshi Inagawa
  • Patent number: 11646316
    Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: May 9, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deokhan Bae, Sungmin Kim, Juhun Park, Yuri Lee, Yoonyoung Jung, Sooyeon Hong
  • Patent number: 11646199
    Abstract: Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 9, 2023
    Assignees: International Business Machines Corporation, ULVAC. Inc.
    Inventors: John Rozen, Martin Michael Frank, Yohei Ogawa
  • Patent number: 11637179
    Abstract: Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 25, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chanro Park, Juntao Li, Ruilong Xie
  • Patent number: 11631572
    Abstract: In a plasma processing apparatus of an exemplary embodiment, a radio frequency power source generates radio frequency power for plasma generation. A bias power source periodically applies a pulsed negative direct-current voltage to a lower electrode to draw ions into a substrate support. The radio frequency power source supplies the radio frequency power as one or more pulses in a period in which the pulsed negative direct-current voltage is not applied to the lower electrode. The radio frequency power source stops supply of the radio frequency power in a period in which the pulsed negative direct-current voltage is applied to the lower electrode. Each of the one or more pulses has a power level that gradually increases from a point in time of start thereof to a point in time when a peak thereof appears.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: April 18, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Shinji Kubota
  • Patent number: 11626281
    Abstract: A method of depositing nitride films is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing nitride films which utilizes separate reaction and nitridation plasmas. In some embodiments, the nitride films have improved growth per cycle (GPC) relative to films deposited by thermal processes or plasma processes with only a single plasma exposure. In some embodiments, the nitride films have improved film quality relative to films deposited by thermal processes or plasma processes with only a single plasma exposure.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 11, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hanhong Chen, Philip A. Kraus, Joseph AuBuchon
  • Patent number: 11621354
    Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Stephanie Bojarski, Babita Dhayal, Biswajeet Guha, Tahir Ghani
  • Patent number: 11615983
    Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chien-Han Chen, Chien-Chih Chiu, Shih-Yu Chang, Da-Wei Lin, Y.T. Chen
  • Patent number: 11610837
    Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 21, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuesong Rao, Benfu Lin, Bo Li, Chengang Feng, Yudi Setiawan, Yun Ling Tan
  • Patent number: 11605669
    Abstract: The present invention provides a monolithic LED array precursor comprising a plurality of LED structures, an LED device comprising the monolithic LED array, and a method of manufacture thereof. In particular, the present disclosure provides a monolithic LED array having improved light emission.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: March 14, 2023
    Assignee: Plessey Semiconductors Limited
    Inventors: Andrea Pinos, Samir Mezouari
  • Patent number: 11605718
    Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes providing a substrate comprising a first top surface; forming an isolation region in the substrate to surround an active region; implanting a plurality of dopants into the substrate to form a first impurity region, a second impurity region and a third impurity region in the active region; forming a gate trench in the active region; forming a first barrier layer on a portion of a sidewall of the gate trench; forming a first gate material in the gate trench, wherein the first gate material comprises a first member surrounded by the first barrier layer; forming a second barrier layer on the first barrier layer and the first gate material; forming a second gate material on the second barrier layer; and forming a gate insulating material on the second gate material.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 14, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tseng-Fu Lu
  • Patent number: 11587867
    Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: February 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongjin Lee, Kyungwook Kim, Rakhwan Kim, Seungyong Yoo, Eun-Ji Jung
  • Patent number: 11581258
    Abstract: The present disclosure provides a semiconductor device structure with a manganese-containing interconnect structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate, a dielectric layer disposed over the semiconductor substrate, and a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line, and a first manganese-containing layer disposed over the first conductive line. The second interconnect structure includes a second conductive line, and a second manganese-containing layer disposed between the second conductive line and the dielectric layer.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: February 14, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11577491
    Abstract: A metallic lustrous member with radio wave transmissibility is provided, which is capable of being easily produced, while ensuring a structure in which not only chromium or indium but also any of some other metals such as aluminum is formed as a metal layer on a continuous surface of any of various materials, and also an article using the member is provided. A production method for a metallic lustrous member with radio wave transmissibility, which is capable of easily forming, as a metal layer, not only chromium or indium but also any of some other metals such as aluminum, on a continuous surface of any of various materials. The metallic lustrous member comprises a substrate having radio wave transmissibility, and an aluminum layer formed directly on a continuous surface of the substrate. The aluminum layer has a discontinuous region including a plurality of separated segments which are mutually discontinuous.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 14, 2023
    Assignee: NITTO DENKO CORPORATION
    Inventors: Xiaolei Chen, Hironobu Machinaga, Hajime Nishio, Taichi Watanabe, Takahiro Nakai
  • Patent number: 11575017
    Abstract: The present disclosure provides a semiconductor device with void-free contacts and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, a dielectric layer disposed over the source/drain structure, and a conductive contact penetrating through the dielectric layer and the source/drain structure, wherein the conductive contact comprises a conductive layer and a barrier layer covering a sidewall and a bottom surface of the conductive layer. A first thickness of the harrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the bottom surface of the conductive layer.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 7, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Liang-Pin Chou
  • Patent number: 11569372
    Abstract: Semiconductor device including first semiconductor layer of a first conductivity type, second semiconductor layer of a second conductivity type at a surface of the first semiconductor layer, third semiconductor layer of the first conductivity type selectively provided at a surface of the second layer, and gate electrode embedded in a trench via a gate insulating film. The trench penetrates the second and third layers, and reaches the first layer. A thermal oxide film on the third layer has a thickness less than that of the gate insulating film. Also are an interlayer insulating film on the thermal oxide film, barrier metal on an inner surface of a contact hole selectively opened in the thermal oxide film and the interlayer insulating film, metal plug embedded in the contact hole on the barrier metal, and electrode electrically connected to the second and third layers via the barrier metal and the metal plug.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: January 31, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Makoto Shimosawa
  • Patent number: 11562901
    Abstract: A substrate processing method capable of achieving uniform etch selectivity in the entire thickness range of a thin film formed on a stepped structure includes: forming a thin film on a substrate by performing a plurality of cycles including forming at least one layer and applying plasma to the at least one layer under a first process condition; and applying plasma to the thin film under a second process condition different from the first process condition.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 24, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: HeeSung Kang, YoonKi Min, WanGyu Lim, SeokJae Oh, SeongIl Cho
  • Patent number: 11557508
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-Li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 11535930
    Abstract: A sputtering apparatus including a chamber, a gas supply configured to supply the chamber with a first gas and a second inert gas, the first inert gas and the second inert gas having a first evaporation point and second evaporation point, respectively, a plurality of sputter guns in an upper portion of the chamber, a chuck in a lower portion of the chamber and facing the sputter guns, the chuck configured to accommodate a substrate thereon, and a cooling unit connected to a lower portion of the chuck, the cooling unit configured to cool the chuck to a temperature less than the first evaporation point and greater than the second evaporation point, and a method of fabricating a magnetic memory device may be provided.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: December 27, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonmyoung Lee, Whankyun Kim, Eunsun Noh, Jeong-Heon Park, Junho Jeong
  • Patent number: 11538749
    Abstract: The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Kuang-Wei Yang, Ting-Ya Lo, Chi-Lin Teng, Hsiao-Kang Chang, Shau-Lin Shue
  • Patent number: 11532433
    Abstract: Various embodiments to mitigate the contamination of electroplated cobalt-platinum films on substrates are described. In one embodiment, a method of manufacture of a device includes depositing a diffusion barrier over a substrate, depositing a seed layer upon the diffusion barrier, and depositing a cobalt-platinum magnetic layer upon the seed layer. In a second embodiment, a method of manufacture of a device may include depositing a diffusion barrier over a substrate and depositing a cobalt-platinum magnetic layer upon the diffusion barrier. In a third embodiment, a method of manufacture of a device may include depositing an adhesion layer over a substrate, depositing a seed layer upon the adhesion layer, and depositing a cobalt-platinum magnetic layer over the seed layer. Based in part on these methods of manufacture, improvements in the interfaces between the layers can be achieved after annealing with substantial improvements in the magnetic properties of the cobalt-platinum magnetic layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 20, 2022
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: David P. Arnold, Ololade D. Oniku
  • Patent number: 11527760
    Abstract: Provided is an aluminum member for electrodes capable of stably maintaining a low electric resistance state, and a method of producing an aluminum member for electrodes. An aluminum member for electrodes includes an aluminum substrate and an oxide film that is laminated on at least one main surface of the aluminum substrate, and the oxide film has a density of 2.7 to 4.1 g/cm3 and a thickness of 5 nm or less.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: December 13, 2022
    Assignee: FUJIFILM Corporation
    Inventor: Hiroshi Komatsu
  • Patent number: 11527716
    Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Santanu Sarkar, Farrell M. Good
  • Patent number: 11527476
    Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
  • Patent number: 11522045
    Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 6, 2022
    Assignee: TESSERA LLC
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Patent number: 11515256
    Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
  • Patent number: 11515204
    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
  • Patent number: 11476419
    Abstract: A method for manufacturing a semiconductor device includes forming a first pattern structure having a first opening on a lower structure comprising a semiconductor substrate. The first pattern structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer that includes water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngmin Ko, Jonguk Kim, Jaeho Jung, Dongsung Choi
  • Patent number: 11456210
    Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuan-Wei Huang, Yi-Nien Su, Yu-Yu Chen, Jyu-Horng Shieh
  • Patent number: 11430652
    Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ching Lee, Chung-Chiang Wu, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee
  • Patent number: 11404312
    Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
  • Patent number: 11401607
    Abstract: A method for ALD coating of a substrate with a layer containing Ti, Si, N, wherein a reaction gas and then a flushing gas are introduced into a process chamber holding the substrate in a plurality of successive steps, each in one or more cycles, wherein TiN is deposited in a first step with a reaction gas containing Ti and a reaction gas containing N, TiSi is deposited in a second step with a reaction gas containing Ti and a reaction gas containing Si, and in a third step following the second step, TiSiN is deposited with a reaction gas containing Ti, with a reaction gas containing N and with a reaction gas containing Si.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 2, 2022
    Assignee: Eugenus, Inc.
    Inventors: Vinayak Veer Vats, M. Ziaul Karim, Bo Seon Choi
  • Patent number: 11398376
    Abstract: A manufacturing method of an embodiment of a semiconductor device, the manufacturing method includes: heating a second layer of a first member including a first layer, the second layer, and a third layer, in which the first layer includes a support layer, the second layer includes a compound containing carbon and at least one element selected from the group consisting of silicon and metals, the third layer includes a semiconductor layer and/or a wiring layer, and the second layer is located between the first layer and the third layer, and obtaining a second member in which a carbonaceous material layer is formed on a surface of the second layer and/or a carbonaceous material region is formed inside the second layer; and cleaving the second member from the carbonaceous material layer or the carbonaceous material region, and obtaining a third member including the third layer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 26, 2022
    Assignee: Kioxia Corporation
    Inventor: Tatsuo Migita
  • Patent number: 11393719
    Abstract: There is provided a technique that performs: (a) forming a first metal film by supplying a plurality of times a first metal-containing gas and a first reducing gas without being mixed with each other to a substrate having a concave portion in a surface of the substrate; and (b) forming a second metal film on the first metal film by supplying a plurality of times at least a second metal-containing gas and a second reducing gas different from the first reducing gas without being mixed with each other or by simultaneously supplying at least a second metal-containing gas and a second reducing gas different from the first reducing gas, to the substrate.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: July 19, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Arito Ogawa
  • Patent number: 11383478
    Abstract: A metallic lustrous member with electromagnetic wave transmissibility, which is capable of being easily produced even when using not only chromium (Cr) or indium (In) but also any of some other metals such as aluminum (Al), as a material for a metal layer thereof. A metallic lustrous member with electromagnetic wave transmissibility, which is capable of using silver (Ag), zinc (Zn), lead (Pb) or copper (Cu), or an alloy thereof, as a material for a metal layer thereof, in addition to aluminum (Al). The metallic lustrous member with electromagnetic wave transmissibility, comprises an indium oxide-containing layer provided along a surface of a substrate, and a metal layer laminated on the indium oxide-containing layer, wherein the metal layer includes, in at least part thereof, a plurality of portions which are in a discontinuous state.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 12, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Hajime Nishio, Hironobu Machinaga, Xiaolei Chen, Toshihiro Tsurusawa, Manami Kurose
  • Patent number: 11387276
    Abstract: A storage device includes first wiring layers extending in a first direction; second wiring layers extending in a second direction; third wiring layers extending in the second direction; a first memory cell arranged at each cross point of one second wiring layer and one first wiring layer; fourth wiring layers extending in the first direction; and a second memory cell arranged at each cross point of one fourth wiring layer and one third wiring layer. The second wiring layer has a first surface in contact with the third wiring layer and a second surface that has a portion extending in the first direction, the extended portion of the second surface being longer than the first surface in the first direction, the second surface being spaced from the first surface in the third direction.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kotaro Noda, Hiroyuki Ode
  • Patent number: 11362000
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 11362030
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • Patent number: 11335555
    Abstract: Methods of conformally doping three dimensional structures are discussed. Some embodiments utilize conformal silicon films deposited on the structures. The silicon films are doped after deposition to comprise halogen atoms. The structures are then annealed to dope the structures with halogen atoms from the doped silicon films.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: May 17, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Yi Yang, Karthik Janakiraman
  • Patent number: 11322348
    Abstract: A multi-function equipment implements a method of fabricating a thin film. The multi-function equipment according to the invention includes a reaction chamber, a plasma source, a plasma source power generating unit, a bias electrode, an AC (Alternating Current) voltage generating unit, a DC (Direct current) bias generating unit, a metal chuck, a first precursor supply source, a second precursor supply source, a carrier gas supply source, an oxygen supply source, a nitrogen supply source, an inert gas supply source, an automatic pressure controller, and a vacuum pump.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 3, 2022
    Inventor: Miin-Jang Chen
  • Patent number: 11315926
    Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deokhan Bae, Sungmin Kim, Juhun Park, Yuri Lee, Yoonyoung Jung, Sooyeon Hong
  • Patent number: 11309265
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsun Huang, Po-Han Wang, Ing-Ju Lee, Chao-Lung Chen, Cheng-Ming Wu
  • Patent number: 11302867
    Abstract: A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, Ta2O5, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 12, 2022
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Youqing Tang, Zhigang Zhang
  • Patent number: 11282742
    Abstract: A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Patent number: 11244859
    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for forming interconnects using a conductive spacer configured to prevent a short between a via and an adjacent line. In a non-limiting embodiment of the invention, a first conductive line and a second conductive line are formed in a metallization layer. A conductive spacer is formed on the first conductive line and a conductive via is formed on a surface of the conductive spacer. The conductive via is positioned such that the conductive spacer is between the first conductive line and the conductive via. A height of the conductive spacer is selected to provide a predetermined distance from the conductive via to the second conductive line. The predetermined distance from the conductive via to the second conductive line is sufficient to prevent a short between the conductive via and the second conductive line.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Cornelius Brown Peethala, Christopher J. Penny, Nicholas Anthony Lanzillo, Lawrence A. Clevenger
  • Patent number: 11217672
    Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee
  • Patent number: 11217673
    Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deokhan Bae, Sungmin Kim, Juhun Park, Yoonyoung Jung
  • Patent number: 11152259
    Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali Gregoire