Plural Layered Electrode Or Conductor Patents (Class 438/652)
  • Patent number: 10249496
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first mandrel line, a second mandrel line, and a non-mandrel line between the first mandrel line and the second mandrel line are provided. A first sidewall spacer is formed adjacent to a section of the first mandrel line and is arranged between the section of the first mandrel line and the non-mandrel line. A first cut is formed that extends partially across the non-mandrel line adjacent to the first spacer to narrow a section of the non-mandrel line. The section of the first mandrel line is removed selective to the first sidewall spacer to form a second cut. An interconnect is formed using the non-mandrel line. The interconnect includes a narrowed section coinciding with a location of the narrowed section of the non-mandrel line.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Xusheng Yu, John H. Zhang, Xiaoqiang Zhang
  • Patent number: 10209584
    Abstract: A manufacturing method of a metal layer, a functional substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a metal layer includes: forming an insulating layer on a base substrate; forming an etching buffer layer on the insulating layer; patterning the etching buffer layer and the insulating layer to form a plurality of recessed microstructures in the insulating layer; stripping the etching buffer layer; and forming a metal layer on the insulating layer, a surface of the metal layer adjacent to the insulating layer is formed with a plurality of protruded portions which are filled into the plurality of recessed microstructures. The manufacturing method of a metal layer may form a metal layer with anti-reflection effect.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xiaoxiang Zhang, Liping Luo, Mingxuan Liu, Huibin Guo, Zhichao Zhang
  • Patent number: 10100393
    Abstract: A method of non-ablatively laser patterning a multi-layer structure, the multi-layer structure including a substrate, a first layer disposed on the substrate, a second layer disposed on the first layer, and a third layer disposed on the second layer, the method including generating at least one laser pulse having laser parameters selected for non-ablatively changing the conductivity a selected portion of the third layer such that the selected portion becomes non-conductive, and directing the pulse to the multi-layer structure, wherein the conductivity of the first layer is not substantially changed by the pulse.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: October 16, 2018
    Assignee: nLIGHT, Inc.
    Inventors: Adam Dittli, Robert J. Martinsen
  • Patent number: 9941213
    Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a dielectric layer is patterned. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A nitridized ruthenium layer is disposed over the adhesion promoting layer. A cobalt layer disposed over the nitridized ruthenium layer filling the set of features, wherein the cobalt layer is formed using a physical vapor deposition process.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9929006
    Abstract: A silicon chalcogenate precursor comprising the chemical formula of Si(XR1)nR24-n, where X is sulfur, selenium, or tellurium, R1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each R2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Timothy A. Quick, Sumeet C. Pandey, Stefan Uhlenbrock
  • Patent number: 9818813
    Abstract: Embodiments of the present application provide a method for producing an array substrate. The array substrate includes a planarization layer provided on a layer of thin film transistors and a first electrode provided on the planarization layer for a light emitting device. The method includes the steps of: forming a pixel definition layer for placing the first electrode, a via hole for the first electrode and a spacer on the planarization layer by a single patterning process with a single mask. The array substrate is produced by the method provided by the present embodiment, so that the number of the used patterning processes and the number of the used masks are reduced.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: November 14, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Qiyu Shen
  • Patent number: 9754912
    Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Matthias Stecher
  • Patent number: 9636782
    Abstract: Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: May 2, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John U. Knickerbocker, Cornelia Kang-I Tsang
  • Patent number: 9634116
    Abstract: A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Barry P. Linder, Vijay Narayanan
  • Patent number: 9478623
    Abstract: A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Tsai-Jung Ho
  • Patent number: 9466584
    Abstract: A method for manufacturing a semiconductor device includes a first step of forming a first electrode on one main surface side of a semiconductor wafer; a second step of bonding a first film to another main surface side of the semiconductor wafer; a third step of bonding a second film to an outer peripheral portion of the semiconductor wafer by applying pressure to the second film on the semiconductor wafer using a plurality of cylindrical rollers, after the second step; and a fourth step of forming a plating layer on the first electrode on the one main surface side of the semiconductor wafer by a plating process, after the third step.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 11, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji Sakaguchi
  • Patent number: 9441298
    Abstract: Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 13, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Khaled Z. Ahmed, Prabu Gopalraja, Atif Noori, Mei Chang
  • Patent number: 9309598
    Abstract: Methods are described herein for etching metal films which are difficult to volatize. The methods include exposing a metal film to a chlorine-containing precursor (e.g. Cl2). Chlorine is then removed from the substrate processing region. A carbon-and-nitrogen-containing precursor (e.g. TMEDA) is delivered to the substrate processing region to form volatile metal complexes which desorb from the surface of the metal film. The methods presented remove metal while very slowly removing the other exposed materials. A thin metal oxide layer may be present on the surface of the metal layer, in which case a local plasma from hydrogen may be used to remove the oxygen or amorphize the near surface region, which has been found to increase the overall etch rate.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: April 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Jie Liu, Anchuan Wang, Nitin K. Ingle, Jeffrey W. Anthis, Benjamin Schmiege
  • Patent number: 9196615
    Abstract: Under one aspect, a nanotube diode includes: a cathode formed of a semiconductor material; and an anode formed of nanotubes. The cathode and anode are in fixed and direct physical contact, and are constructed and arranged such that sufficient electrical stimulus applied to the cathode and the anode creates a conductive pathway between the cathode and the anode. In some embodiments, the anode includes a non-woven nanotube fabric having a plurality of unaligned nanotubes. The non-woven nanotube fabric may have a thickness, e.g., of 0.5 to 20 nm. Or, the non-woven nanotube fabric may include a block of nanotubes. The nanotubes may include metallic nanotubes and semiconducting nanotubes, and the cathode may include an n-type semiconductor material. A Schottky barrier can form between the n-type semiconductor material and the metallic nanotubes and/or a PN junction can form between the n-type semiconductor material and the semiconducting nanotubes.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: November 24, 2015
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold
  • Patent number: 9153500
    Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi3, CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: October 6, 2015
    Assignee: Fudan University
    Inventors: Qingqing Sun, Lin Chen, Wen Yang, Pengfei Wang, Wei Zhang
  • Patent number: 9136177
    Abstract: Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 15, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
  • Patent number: 9123784
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 1, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • Patent number: 9034710
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Publication number: 20150123131
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 7, 2015
    Applicant: Infineon Technologies AG
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Publication number: 20150126027
    Abstract: A method for manufacturing a semiconductor device includes: forming an insulating film on a substrate where a first conductive film is formed; forming a recess in the insulating film such that the first conductive film is exposed in a portion of the recess; forming a metal oxide film to cover the insulating film and the first conductive film after forming a recess; performing a hydrogen radical treatment of irradiating the substrate with atomic hydrogen after forming a metal oxide film; and forming a second conductive film in the recess.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: Kenji MATSUMOTO, Tatsufumi HAMADA, Kaoru MAEKAWA
  • Publication number: 20150115419
    Abstract: A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a plurality of empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas between each pair of neighboring metal layers.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu MA, Hui-Mei CHOU, Kuo-Ji CHEN
  • Publication number: 20150115412
    Abstract: A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a first conductive layer disposed on the second main surface so that the through hole passes through the semiconductor substrate from the first main surface to the second main surface; forming an insulation film to extend from a bottom portion of the through hole to the first main surface through a side surface of the through hole; coating an organic member on the insulation film on the side surface of the through hole and the first main surface; removing an air bubble in the organic member and between the organic member and the insulation film; and forming a first opening portion in the organic member.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 30, 2015
    Inventor: Akihiko NOMURA
  • Publication number: 20150118842
    Abstract: Methods of fabricating a semiconductor device are described. The method includes forming a patterned oxide layer having a plurality of openings over a substrate, depositing a metal layer in the openings to form metal plugs, depositing a global transformable (GT) layer on the oxide layer and the metal plugs, and depositing a capping layer directly on the GT layer without exposing the GT layer to ambient air. The GT layer on the oxide layer transforms into a dielectric oxide and the GT layer on the metal plugs remains conductive during deposition of the capping layer.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya-Lien Lee
  • Publication number: 20150118821
    Abstract: A method of forming a semiconductor device structure comprises forming a mold template comprising trenches within a mold material. Structures are formed within the trenches of the mold template. A wet removal process is performed to remove the mold template, a liquid material of the wet removal process remaining at least in spaces between adjacent pairs of the structures following the wet removal process. A polymer material is formed at least in the spaces between the adjacent pairs of the structures. At least one dry removal process is performed to remove the polymer material from at least the spaces between the adjacent pairs of the structures. Additional methods of forming a semiconductor device structure, and methods of forming capacitor structures are also described.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Dan B. Millward, J. Neil Greeley
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Publication number: 20150111377
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • Patent number: 9006102
    Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventors: Yu Hong, Liu Huang, Zhao Feng
  • Publication number: 20150097275
    Abstract: A semiconductor device includes a substrate, a substrate-side electrode layer, an intermediate electrode layer, and a front-side electrode layer. The substrate includes a semiconductor layer and a projection portion, the projection portion being formed on a surface of the semiconductor layer. The substrate-side electrode layer is provided on the projection portion. The intermediate electrode layer extends from on a part of the substrate-side electrode layer, which part of the substrate-side electrode layer is located on the projection portion, to just above a region of the substrate in which region the projection portion is not provided. The front-side electrode layer is provided on a surface of the intermediate electrode layer. A Young's modulus E1 of the substrate-side electrode layer, a Young's modulus E2 of the intermediate electrode layer, and a Young's modulus E3 of the front-side electrode layer satisfy a relationship of E3>E1>E2.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 9, 2015
    Inventors: Atsushi IMAI, Yoshiaki KOMINAMI, Takashi USHIJIMA
  • Patent number: 8993397
    Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8987135
    Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: March 24, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc.
    Inventors: Christian Lavoie, Ahmet S. Ozcan, Zhen Zhang, Bin Yang
  • Patent number: 8980741
    Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Sylvia Lo, Jing-Cheng Lin, Yen-Hung Chen, Wen-Chih Chiou
  • Publication number: 20150069613
    Abstract: According to one exemplary embodiment, a semiconductor device includes a chip main body; a first layer that is provided on the chip main body and contains nickel and phosphorus; and a second layer that is provided on the first layer and contains nickel and phosphorus and has a higher phosphorus concentration than that of the first layer.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya SHIRAISHI, Ryota YOSHIOKA
  • Publication number: 20150061114
    Abstract: A semiconductor device includes a semiconductor chip and a joined member. The semiconductor chip has a semiconductor substrate, a first electrode, and a second electrode. The first electrode is arranged on a first surface of the semiconductor substrate. The second electrode is arranged on a second surface of the semiconductor substrate. The first electrode is joined to the joined member via a joint material. A tensile force in a surface direction of the first surface that is applied to the first surface of the semiconductor substrate from the first electrode due to thermal expansion of the first electrode at a melting temperature of the joint material is at least equal to a tensile force in the surface direction that is applied to the second surface of the semiconductor substrate from the second electrode due to thermal expansion of the second electrode at the melting temperature.
    Type: Application
    Filed: August 11, 2014
    Publication date: March 5, 2015
    Inventor: Katsutoshi NARITA
  • Publication number: 20150061161
    Abstract: According to example embodiments, a wire structure includes a first wire that includes a first wire core and a first carbon shell surrounding the first wire core, and a second wire that extends in a longitudinal direction from the first wire. The first wire core has a wire shape. The first carbon shell contains carbon.
    Type: Application
    Filed: August 25, 2014
    Publication date: March 5, 2015
    Applicant: Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Eun-kyung LEE, Byoung-lyong CHOI, Won-Jae JOO, Byung-Sung KIM, Jae-Hyun LEE, Jong-Woon LEE, Dong-Mok WHANG
  • Patent number: 8969189
    Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
  • Patent number: 8969196
    Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Publication number: 20150054175
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 26, 2015
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Publication number: 20150056800
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik
  • Publication number: 20150048517
    Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Lizabeth Ann Keser, Zhongping Bao, Reynante Tamunan Alvarado
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946047
    Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
  • Patent number: 8936960
    Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuan-Yu Wang, Hui-Min Wu, Kun-Che Hsieh
  • Patent number: 8928066
    Abstract: An integrated circuit may include a semiconductor portion with a power transistor including first gate trenches that cross a first region and a sense transistor including second gate trenches that cross a second region. Each gate trench extends in a longitudinal direction and comprises a gate electrode and a field electrode. The first and second regions are arranged along the longitudinal direction. A first termination trench intersects at least the second gate trenches in a third region between the first and second regions. The first termination trench includes a first conductive structure that is electrically connected to the field electrodes in the second gate trenches. The characteristics of the sense transistor formed in the second region reliably and precisely replicate the characteristics of the power transistor.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: January 6, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Britta Wutte, Martin Poelzl
  • Patent number: 8921184
    Abstract: In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Publication number: 20140374775
    Abstract: A first metal film, of which major component is copper, is formed on a surface of a conductive portion which becomes a front surface electrode of a semiconductor element. A second metal film of which major component is silver is formed on a surface of the first metal film. A metal plate, which electrically connects the conductive portion and the other members (e.g. a circuit pattern of an insulated substrate) is bonded with a surface of the second metal film via a bonding layer containing silver particles. The second metal film does not contain nickel which decreases the bonding strength between the second metal film and the bonding layer containing silver particles. With the above configuration, an electronic component having a high bonding strength, excellent heat resistance and radiation performance, and a manufacturing method for the electronic component can be provided.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Inventors: Takashi SAITO, Tatsuo NISHIZAWA, Yoshito KINOSHITA, Norihiro NASHIDA
  • Patent number: 8916470
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 23, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Durga Panda, Jaydip Guha, Robert Kerr
  • Patent number: 8907383
    Abstract: Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Ki Yong Lee
  • Patent number: 8906795
    Abstract: A semiconductor device manufacturing method allows stably forming a plating layer at low cost on one main surface side of a substrate, while preventing unintended plating layer deposition on the other main surface side. Emitter and collector electrodes are respectively formed on the front and back surfaces of a semiconductor substrate. A first film is attached to the back surface. A notch portion of the substrate is filled with a resin member. A second film is attached to an outer peripheral portion of the substrate, straddling the substrate from the front surface to the back surface. The first and second films push out air remaining between the first and second films and the substrate. An electroless plating process is carried out while the first and second films are attached to the substrate, thereby sequentially forming a nickel plating layer and a gold plating layer on the front surface side.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: December 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shoji Sakaguchi, Idayu Sofya
  • Patent number: 8907407
    Abstract: The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Takahiro Oikawa
  • Publication number: 20140353831
    Abstract: Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Sri Ranga Sai BOYAPATI, Qinglei ZHANG