Abstract: Provided is a method for forming a semiconductor device that can reduce contact resistance of a storage node contact connecting the source/drain of a transistor with a capacitor. The method includes the steps of: forming an inter-layer insulating layer on a silicon substrate, wherein a junction is formed on a surface of the silicon substrate; forming a contact hole exposing the junction by selectively etching the inter-layer insulating layer; removing a native silicon oxide layer on the junction by forming titanium layer on the junction; and forming a titanium silicide layer as a first ohmic contact layer on the junction by carrying out a first thermal treatment.

Abstract: A method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed. A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: A method for forming tungsten structures over silicon substrates, including the following steps. A silicon substrate is having a patterned dielectric layer formed thereon defining a tungsten structure opening is provided. The silicon substrate is pre-heated to a temperature of from about 430 to 440° C. A Si-rich WSx layer is formed over the patterned dielectric layer, lining the tungsten structure opening. A WSix nucleation layer is formed over the Si-rich WSix layer. A tungsten bulk layer is formed over the WSix nucleation layer, filling the tungsten structure opening, whereby fluorine attack of the Si substrate is minimized.

Abstract: A method of forming a metal gate integrated with a salicide process on the source and drain regions. A gate dielectric layer and polysilicon/silicon dioxide/silicon nitride dummy gate layers are formed over a substrate structure and patterned to form dummy structures, comprising at least one dummy gate structure. Lightly doped source and drain regions, sidewall spacers, and source and drain regions are formed adjacent to the dummy gate structure. A silicide layer is formed on the source and drain regions by depositing titanium/titanium nitride, performing a rapid thermal anneal, selectively removing unreacted titanium/titanium nitride using NH4OH, and performing a second rapid thermal anneal. A blanket dielectric layer is formed over the dummy structures. The blanket dielectric layer, the spacers and the silicon nitride layer of the dummy structures are planarized using a chemical mechanical polishing process. The silicon nitride layer and the silicon dioxide layer of the dummy structures are removed.

Abstract: A method of forming conductive interconnections is disclosed herein. In one illustrative embodiment, the method comprises forming an opening in a layer of insulation material, forming a first plurality of silicon seed atoms in the opening, and performing a first tungsten growing process to form tungsten material in the opening. The method further comprises forming a second plurality of silicon seed atoms in the opening above at least a portion of the tungsten material formed during the first tungsten growing process, and performing at least one additional tungsten growing process after forming the second plurality of silicon seed atoms to further form tungsten material in the opening.

Abstract: The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.

Abstract: A method of forming a contact in an integrated circuit including forming a dielectric layer over a silicon substrate, etching a contact hole through the dielectric layer, exposing the etched contact hole to a plasma formed from a preclean gas comprising nitrogen trifluoride and helium and, thereafter, depositing a titanium layer within the contact hole by a plasma CVD process, where the plasma CVD process heats the substrate to a temperature less than or equal to 650° C.

Abstract: The present method of manufacturing a semiconductor device has a step of forming a metal film on the surface of a group of semiconductor wafers by bringing the internal temperature of a chamber of a film formation device to a film formation temperature at which the metal film is deposited, followed by a step of lowering the temperature of the chamber to a standby temperature at a constant rate and holding the temperature of the chamber at the standby temperature until the film formation for the next group of the semiconductor wafers.

Abstract: A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

Abstract: The present disclosure is directed to the use of non-ion-implanted silicon oxynitride films as resistive elements. Such films have been traditionally used in semiconductor processing as antireflective coatings, but their utility as highly resistive circuit elements has heretofore not been realized. Such films find specific utility when used as the load resistors in a 4-T SRAM cell.

Abstract: A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via.

Abstract: The present invention provides a method to form a self-aligned MOS transistor with a gate capped by a metal silicide layer. The gate has a larger surface area and a lower resistance, so this method is suitable as the feature size of integral circuits scale down. In this method, the primary step is to deposit a selective dielectric layer, such as polysilicon germanium layer, on the top of a gate to increase the surface area of the gate. Then, a metal silicide layer is formed on the surface of the dielectric layer to decrease the resistance of the gate. Therefore, comparing to conventional methods, a gate formed by the present method has a larger contacting area and is more ease to connect to a conductive line, so that the performance of a MOS transistor can be improved.

Abstract: A method and system to form a refractory metal layer on a substrate features a bifurcated deposition process that includes nucleating a substrate using ALD techniques to serially expose the substrate to first and second reactive gases followed forming a bulk layer, adjacent to the nucleating layer, using CVD techniques to concurrently exposing the nucleation layer to the first and second gases.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).

Abstract: A manufacturing method of a semiconductor device of the invention is a method of manufacturing a semiconductor device by forming a plurality of films on an insulating layer which has a surface in which a recess portion is partially formed. The method includes: a base-metal-film forming step of forming a base-metal film including a metal having a high melting point on the surface of the insulating layer including an inside surface of the recess portion, a surface-processing step of processing a surface of the base-metal film by means of an organic solvent having an OH-group, and a metal-for-circuit depositing step of depositing a metal for a circuit on the processed surface of the base-metal film by means of a CVD method in such a manner that at least a part of or the whole of the recess portion is filled up.

Abstract: The present invention discloses a method for forming a self-aligned silicidation of a metal oxide semiconductor. The feature of the present invention is to perform an ionic implanting step before carrying on the self-aligned silicidation. The implanted ion of the present invention, such as fluorine, chlorine, bromine, iodine, boron and trifluroborane, will react with the silicon on the surface of the gate structure and the silicon substrate and a barrier effect will be formed during silicidation. Therefore, a spike phenomenon because of the penetration of cobalt or the cobalt silicide into the gate structure or the source/drain regions is prevented. The junction leakage current and the breakdown voltage of the metal oxide semiconductor are avoided.

Abstract: Within both a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is then formed over the patterned bond pad layer a barrier layer comprising: (1) a first titanium-tungsten alloy layer; (2) a titanium-tungsten alloy nitride layer formed upon the first titanium-tungsten alloy layer; and (3) a second titanium-tungsten alloy layer formed upon the titanium-tungsten alloy nitride layer. Finally, there is then formed upon the barrier layer a seed layer which comprises a titanium layer formed upon the barrier layer. The method contemplates a microelectronic fabrication fabricated employing the method. The barrier layer provides enhanced barrier properties within the microelectronic fabrication within which is formed the barrier layer.

Abstract: A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.

Abstract: A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about −70° C. to about 0° C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

Abstract: The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.

Abstract: A polysilicon layer is formed on a semiconductor substrate followed by performing a collimator physical vapor deposition (PVD) process to form a titanium nitride layer on the polysilicon layer. A rapid thermal nitridation (RTN) process is then performed to tighten the structure of the titanium nitride layer. Finally, a silicide layer is formed on the barrier layer. By using the titanium nitride layer, the interface between the silicide layer and the polysilicon layer is effective prevented from occurring a spike.

Abstract: A method for forming a titanium film and a titanium nitride film on a surface of a substrate by lamination, by which contamination of the substrate due to the by-product is suppressed and the contact resistance of the titanium film is reduced. The method comprises the steps of forming a titanium film on the surface of the substrate using a first process gas containing TiCl4 and a reducing gas, subjecting the substrate to a plasma process using a second process gas containing N2 gas and a reducing gas, thereby decreasing Cl in the titanium film and nitriding the surface of the titanium film to form a nitride layer, and forming a barrier metal (e.g., a titanium nitride film) on the titanium film having the nitride layer. Thus, the titanium film and the titanium nitride film are formed on the substrate by lamination. The second process gas contains N2 gas in a ratio of 0.5 or lower with respect to the reducing gas.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

Abstract: A substrate is placed in a sputter chamber so as to be spaced from a target contained in the chamber. A gaseous impurity is provided into the sputter chamber so as to control a pressure within the chamber in a pressure transition range. A first pressure in the chamber when during an increase in pressure is different from a second pressure in the chamber during a decrease in pressure, while an equal amount of the nitrogen gas is provided into the sputter chamber. Accelerated particles collide with the target to sputter the metal material from the target. Accordingly, a metal barrier layer containing an impurity comprised of the gaseous impurity and the metal material is deposited on the substrate.

Abstract: Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.

Abstract: A chemical vapor deposition process for depositing tungsten films having small grain size is provided. The process involves depositing a nucleation layer having very small nuclei that are closely spaced so that there are few vacancies on the surface. Such a nucleation layer results in a film with small grains after the subsequent deposition of bulk layers. The temperature of the substrate can be increased during deposition of the nucleation layer and then lowered for deposition of the bulk layer to produce a small grain tungsten film. Additionally, the thickness of the nucleation layer can be controlled, and the deposition chamber pressure and silage flow rates can also be controlled to achieve the desired nucleation layer before deposition of the bulk layers.

Abstract: An insulating film for embedding conductive portions therein is formed so as to represent convex configurations corresponding to each top of convex conductive portions. The insulating film is covered with an etching stopper film having an etching rate which is smaller than that of the insulating film. Convex portions of the etching stopper film corresponding to each top of the conductive portions are removed partially, thereby forming a contact hole that reaches each top of the conductive portions through the removal portions of the silicon nitride film by an etching treatment. A plug conductive portion connected to each top of the conductive portions is formed in the contact hole.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

Abstract: A bonding pad structure. A substrate having a first surface and a second surface is provided. A metal bonding pad and a bonding region are respectively located on the first surface and the second surface. Intermediate plated layers located are on the metal bonding pad and the bonding region. Under ball metallurgy layers are located on each of the intermediate plated layers such that each of the under ball metallurgy layers comprises a first plated layer and a second plated layer.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a silicon layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: An ultra-thin gate oxide layer of hafnium oxide (HfO2) and a method of formation are disclosed. The ultra-thin gate oxide layer of hafnium oxide (HfO2) is formed by a two-step process. A thin hafnium (Hf) film is first formed by thermal evaporation at a low substrate temperature, after which the thin hafnium film is radically oxidized using a krypton/oxygen (Kr/O2) high-density plasma to form the ultra-thin gate oxide layer of hafnium oxide (HfO2). The ultra-thin gate oxide layer of hafnium oxide (HfO2) formed by the method of the present invention is thermally stable in contact with silicon and is resistive to impurity diffusion at the HfO2/silicon interface. The formation of the ultra-thin gate oxide layer of hafnium oxide (HfO2) eliminates the need for a diffusion barrier layer, allows thickness uniformity of the field oxide on the isolation regions and, more importantly, preserves the atomically smooth surface of the silicon substrate.

Abstract: The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process.

Abstract: A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.

Abstract: After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (18) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20a to 20c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20a to 20c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20a to 20c) and patterns (18a to 18c) of the second antireflection coating film (18) as masks.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.

Abstract: In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film (14) containing fluorine formed on a substrate (11), a titanium aluminum alloy film (17a) formed on the insulating film (14) containing fluorine, and a metallic film (17b) comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film (17a).

Abstract: Disclosed is a method and an apparatus for manufacturing a barrier layer of semiconductor device. The disclosed comprises the steps of: forming an interlayer insulating layer having a contact hole on a semiconductor substrate; forming a Ti layer on the contact hole and on the interlayer insulating layer; and reacting the Ti layer with nitrogen radical to transform a part of the Ti layer into a TiN layer.

Abstract: A method of forming a film on a substrate using one or more complexes containing one or more chelating O- and/or N-donor ligands. The complexes and methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: An integrated circuit designed to control grain growth induced roughening in a conductive stack is disclosed herein. The conductive stack includes an interconnect metallization layer formed at a low diffusivity temperature of less than 200° C. The interconnect metallization layer includes aluminum doped with copper. The conductive stack further includes subsequent depositions and/or processing involving interconnect metallization layer to be carried out at the low diffusivity temperatures.

Abstract: A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).

Abstract: The interconnection system of the present invention comprises an interconnection film formed by chemical vapor deposition, wherein the interconnection film comprises an upper layer and a lower layer in which the concentrations of impurities are different. The method of producing an interconnection film comprising an upper layer and a lower layer by chemical vapor deposition using a single chamber, comprises: a lower layer forming step of depositing the lower layer in a recesses by evacuating the chamber and by injecting a reactant gas into the chamber; a cleaning step of subsequently reducing the partial pressure of impurities which are dissociated from the reactant gas; and an upper layer forming step of subsequently depositing an upper layer onto the lower layer by injecting a reactant gas into the chamber.

Abstract: A method of forming a composite barrier layer structure for use in integrated circuits is disclosed. The composite barrier layer structure formed using both physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques. The composite barrier layer structure comprises a CVD deposited layer formed on a PVD deposited layer. During the PVD process, the underlying surface of the substrate is treated, reducing the resistivity of the barrier layer structure formed thereon.