Abstract: A platinum film orientation-controlled to (111), (200) and/or (220) is provided by depositing the platinum film under an atmosphere containing an oxygen component such as O2, O3, N2O , N2+O2, or mixtures thereof as well as an inert gas (Ar, Ne, Kr, or Xe) on a substrate heated to a temperature ranged from room temperature to 700° C., and annealing to remove the gases introduced into the platinum film during the deposition thereof. The platinum film formed in this process has excellent electrical conductivity (resistivity is lower than 15 &mgr;&OHgr;-cm), good enough adhesion strength to be used for electronic devices, and does not show hillocks, voids or pinholes.

Abstract: A method for manufacturing integrated circuits (“IC”) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.

Abstract: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chip 30 and a substrate, the semiconductor chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semiconductor chip 30 can be enhanced.

Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

Abstract: A dual-sided semiconductor chip is formed on a wafer to have a low-resistance, electrically-conductive path through the wafer. By forming the conductive path through the wafer, elements on one side of the wafer can exchange signals (voltages and/or currents) with elements on the other side of the wafer.

Abstract: To shorten a process for manufacturing a semiconductor device comprising a silicide and a non-silicide diffusion layers and to form a stable and highly homogenous non-silicide diffusion layer, ions are implanted to form a source/drain diffusion layer and then the substrate is subjected to rapid thermal oxidation in a short time to activate the ions while forming a new oxide film. A thermal oxide film (6) consisting of the new oxide film including a protective oxide film (3) is etched to form an oxide film for preventing silicidation (8), a Ti film (9) is formed over the whole surface including the oxide film for preventing silicidation (8), the product is annealed for silicidation and the unreacted Ti film (9) is removed. Thus, a diffusion layer (4) as a non-silicide layer which is little silicided and a diffusion layer (5) whose surface is a silicide layer (10) are formed.

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.

Abstract: Method for controlling the morphology and impeding electromigration of sputtered copper films and semiconductor wafers produced thereby. Copper may be deposited onto a seed layer or wetting layer of a dopant metal by PVD at an elevated temperature relative to the temperature at which the seed layer is deposited. Copper may also be deposited in a two step PVD process whereby a first copper layer is deposited at a lower temperature relative to a second copper layer. The resulting film has a smooth surface and no voids.

Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).

Abstract: A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor.

Abstract: A method and structure is described which substantially eliminates the grain growth of copper due to self annealing. Basically, by alloying the copper interconnect e.g. with Cr, Co, Zn or Ag in an amount which does not cause a second phase or precipitation at the annealing temperature, one can control and maintain the grain size of the copper and hence achieve a uniform microstructure while improving the strength, hardness and CMP removal rate of the interconnect while substantially maintaining the conductivity of the copper.

Abstract: The present invention pertains to systems and methods for reducing the agglomeration of copper deposited by physical vapor deposition. More specifically, the invention pertains to systems and methods for depositing copper seed layers on a semiconductor wafer. The invention involves the use of an anti-agglomeration agent, so that the copper deposition is completed in an even, continuous and conformal manner.

Abstract: Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.

Abstract: A method for processing a substrate comprising the formation of a metal nitride/metal stack suitable for use as a barrier/liner for sub-0.18 &mgr;m device fabrication. After a metal nitride layer is deposited upon a metal layer, the metal nitride layer is exposed to a treatment step in a nitrogen-containing environment, e.g., a plasma. The plasma treatment modifies the entire metal nitride layer and a top portion of the underlying metal layer. The plasma adds nitrogen to the top portion of the metal layer, resulting in the formation of a nitrated-metal layer. Aside from reducing the microstructure mismatch across the nitride-metal interface, the plasma treatment also densifies and reduces impurities from the deposited nitride layer. The resulting nitride/metal stack exhibits improved film properties, including enhanced adhesion and barrier characteristics. A composite nitride layer of a desired thickness can also be formed by repeating the deposition and treatment cycles of thinner component nitride layers.

Abstract: The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

Abstract: A method of encapsulating metal lines (130, 132, 134, 136, 138) by implantation of dopants to form surface regions (131, 133, 135, 137, 139) after the metal lines have been fabricated. The surface regions may act as passivation layers and electromigration inhibitors and so forth.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

Abstract: A method of monitoring a process of manufacturing a semiconductor wafer including an area of hemispherical grain polysilicon, the method comprising providing a probe including a liquid conductor; and performing a capacitance-voltage measurement with the probe, using a quasi-static measurement method, to determine capacitance-voltage characteristics at the area of hemispherical grain polysilicon.

Abstract: An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, the refractory metal 240 reacts with the conducting layer 210 to form an intermetallic 245 which further enhances the endurance of the metallization against stress-induced rupturing and via-induced electromigration. The disclosed structures and methods are particularly advantageous in “zero-overlap” designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in “Damascene” pattern definition applications.

Abstract: A method for forming a fine conductor member with a high degree of precision is provided. A conductor member formation method having a process for forming a first film on a base material, a process for forming a second film on the first film, a process for forming a first opening part on the second film so that the second film will have a prescribed pattern, a process for removing a portion of the first film so that the second film will serve as a hood, a process for forming a conductor member on the base material using the first film and the second film as masks, and a process for removing the first film and the second film, is provided.

Abstract: This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-etched, the enlarged plug enhancement region contains subsequently formed barrier layers and other conductive materials to reduce current leakage into the underlying substrate or into adjacent circuit elements.

Abstract: The present invention is a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has a via opening therein, which exposes the semiconductor substrate. Next, the surfaces of the via opening is covered with a conformal titanium layer formed by a sputtering process. The surface of the conformal titanium layer is covered with an Al—Si—Cu alloy layer formed by a sputtering process at a temperature of about 0° C. to 200° C. Then, the surface of the Al—Si—Cu alloy layer is covered with an Al—Cu alloy layer formed by a sputtering process at a temperature of about 380° C. to 450° C., which Al—Cu alloy layer fills the via opening. The Al—Cu alloy layer, the Al—Si—Cu alloy layer and the wetting layer on the dielectric layer are patterned by photolithography and etching process.

Abstract: According to a method of manufacturing a MIS semiconductor device of the present invention, a gate insulating film is formed on a silicon substrate, and a silicon thin film is deposited on the gate insulating film, whereafter a silicon film containing germanium is deposited on the silicon thin film and an amorphous silicon film is deposited on the germanium-containing silicon film. Further, heat treatment is performed to diffuse the germanium in the germanium-containing silicon film into the silicon thin film, and a metal film is deposited on the amorphous silicon film and heat treatment is performed to cause a silicidation reaction to occur with the metal film to form a silicide film. Therefore, the germanium-containing silicon film which can control gate depletion can be formed stably with a good reproducibility. Further, since the silicide film on the gate electrode is formed on the silicon film, it can be formed with a low resistance.

Abstract: A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.

Abstract: A method is disclosed for forming a high aspect ratio submicron VLSI interconnect structure. The method makes use of the high diffusivity of aluminum alloyed with germanium and the low eutectic temperature of the alloy for more uniform filling of interconnect structure openings having high aspect ratios. The method comprises preparing a semiconductor device or portion of a semiconductor device that is to receive electrical contact, covering the semiconductor device with an insulating layer, forming an interconnect structure openings through the insulating layer, depositing a layer of germanium in the interconnect structure opening, and reflow sputtering aluminum or aluminum alloy into the interconnect structure opening. Alternatively, the aluminum or aluminum alloy can be cold sputtered into the interconnect structure opening, followed by a low temperature reflow. The aluminum will readily diffuse to the bottom of the interconnect structure opening, assisted by its high diffusivity with the germanium.

Abstract: For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activated surface of the exposed part is formed in the contact hole, a gas containing an impurity component is supplied to form an impurity adsorption film on the activated surface, and the contact hole is filled with a second electrically conductive layer which electrically contacts the first layer through the contact hole.

Abstract: A method of making connection between an aluminum or aluminum based material and tungsten. The method includes providing an underlying region containing a layer of tungsten thereover. The underlying region is preferably a layer of titanium over which is a layer of titanium nitride. The layer of tungsten is etched back to the underlying region while exposed tungsten is retained over a portion of the underlying region. The underlying region also may contain a via therein which contains the exposed tungsten. An nitrogen-containing plasma, preferably elemental nitrogen, is then applied to the exposed tungsten and exposed underlying region and a layer of a barrier material is formed by reaction of the nitrogen in the plasma and the tungsten over the exposed tungsten. A further barrier layer, preferably titanium nitride, is optionally then applied followed by a layer of aluminum over the exposed surface, the barrier layer isolating the layer of aluminum from the tungsten.

Abstract: In a method for producing an integrated circuit using a CMOS process, in particular a HV CMOS process, components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate. Further, a SOI wafer substrate is used that comprises a top substrate layer for forming the CMOS components, a lateral insulation layer provided beneath the substrate layer, and a support layer arranged beneath the insulation layer. The top substrate layer has a thickness less than or equal to the greatest trough depth of the CMOS process.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: A method of depositing a (200)-oriented platinum thin film on a substrate, including the steps of forming a oxygen containing platinum layer on the surface of a silicon wafer heated to a temperature range over room temperature and not exceeding 700° C. under a mixed gaseous atmosphere of oxygen and inert gas and annealing the substrate at a temperature between 400° C. and 1000° C. The platinum thin film formed according to the present invention in (200)-oriented and does not have any conventional defects such as hillocks or voids.

Abstract: An apparatus and method of tungsten via fill using a low pressure, 2-step nucleation tungsten deposition process. The tungsten via fill includes a silane soak, a nucleation film growth, and a bulk tungsten film deposition. The nucleation film growth is a low pressure, 2-step process including a controlled first nucleation film growth and a second nucleation film growth. A wafer fabricating system that includes a film depositing system and a control system is used. The film depositing system includes a reaction chamber with at least one silane-containing gas source, a tungsten-containing gas source, and a substrate heating source. The control system instructs the silane-containing gas source and the tungsten-containing gas source to flow with a significantly higher ratio of silane-containing gas (SiH4) to form a first silane-rich nucleation layer. The control system then instructs the gas sources to flow with a higher ratio of tungsten-containing gas, such as WF6, to form a second tungsten nucleation layer.

Abstract: A high aspect ratio submicron VLSI contact and corresponding method of manufacture is disclosed. The contact is formed through an insulative layer, such as silicon dioxide, to an underlying active region on a substrate of silicon wafer. The contact comprises a layer of titanium germanosilicide at the bottom of the contact opening, and a layer of titanium germanide at the sides of the contact opening, with an overlying layer of titanium nitride. The contact is metallized, preferably using tungsten or aluminum. The disclosed method of manufacturing the contact comprises first etching the contact opening, then exposing the bottom of the contact opening to germane gas to clean native silicon dioxide from the bottom of the contact opening. A 50 Angstrom layer of germanium is then deposited over the contact opening. A layer of titanium is then deposited over the germanium layer in the contact opening. The deposition of titanium is preferably accomplished using a collimator having an aspect ratio lower than about 2.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

Abstract: The present invention provides a method and apparatus for filling contacts, vias, trenches, and other patterns, in a substrate surface, particularly patterns having high aspect ratios. Generally, the present invention provides a method for removing oxygen from the surface of an oxidized metal layer prior to deposition of a subsequent metal. The oxidized metal is treated with a plasma consisting of nitrogen, hydrogen, or a mixture thereof. In one aspect of the invention, the metal layer is Ti, TiN, Ta, TaN, Ni, NiV, or V, and a subsequent wetting layer is deposited using either CVD techniques or electroplating, such as CVD aluminum (Al) or electroplating of copper (Cu). The metal layer can be exposed to oxygen or the atmosphere and then treated with a plasma of nitrogen and/or hydrogen in two or more cycles to remove or reduce oxidation of the surface of the metal layer and nucleate the growth of a subsequent metal layer thereon.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

Abstract: A method to deposit a composite metal to form a continuous, smooth film in high aspect ratio features such as vias, contacts and/or trenches on a wafer in a single step. Metal atoms are sputtered from a composite target containing a first metal and a second metal in a single reaction chamber. A physical vapor deposition processes such as ionized physical vapor deposition (IPVD) is preferred. In one embodiment, the first metal is titanium and the second metal is aluminum. The method eliminates a high temperature anneal and results in lower resistivity, a better wetting layer for subsequent deposition and improved control over thickness of the metal layer.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Abstract: A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

Abstract: A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a relatively high aspect ratio of 2:1 or greater. The contact further includes a refractory metal germanosilicide region at the bottom of the contact opening, a refractory metal germanide layer at the sidewalls of the contact opening, and an overlying refractory metal nitride layer. The refractory metals of the invention include at least tantalum, titanium, cobalt and mixtures thereof. The contact is metallized, preferably using tungsten or aluminum. The method of manufacturing the contact comprises etching the contact opening. A germane gas is used to clean native silicon dioxide from the bottom of the contact opening and to deposit a germanium layer thereon. A refractory metal layer is deposited over the germanium layer. After annealing in a nitrogen atmosphere at a temperature of about 600° C.

Abstract: Methods and apparatus for fabricating stacked capacitor structures, which include barrier layers, are disclosed. According to one aspect of the present invention, a method for reducing outdiffusion within an integrated circuit includes forming a gate oxide layer over a substrate, and further forming a silicon plug over a portion of the gate oxide layer. A silicon dioxide layer is then formed over the gate oxide layer, and is arranged around the silicon plug. A first barrier film is formed over the silicon plug, and a dielectric layer is formed over the silicon dioxide layer. In one embodiment, forming the first barrier film includes forming a first oxide layer over the silicon plug, nitridizing the first oxide layer, and etching the nitridized first oxide layer.

Abstract: A method for forming a contact plug. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening that exposes a thin layer of native oxide. A first and a second conformal doped polysilicon layer are formed over the opening. The first doped polysilicon layer has a dopant concentration greater than that of the second doped polysilicon layer. A third doped polysilicon layer that also fills the opening is formed over second doped polysilicon layer. Dopant concentration of the third doped polysilicon layer is smaller than the second doped polysilicon layer. Last, the first, the second and the third doped polysilicon layer are annealed.

Abstract: A semiconductor device has a thin semi-insulating polycrystalline silicon (SIPOS) film on the surface of a silicon substrate having a diffused region therein. The SIPOS film is thermally treated at the bottom of a via-plug of an overlying metallic film to form a metallic silicide for electrically connecting the via-plug with the diffused region, whereas the SIPOS film is maintained as it is for insulation on a dielectric film. The SIPOS film protects the diffused regions against over-etching to thereby improve the junction characteristics and provide a larger process margin for contacts between the metallic interconnects and the diffused regions.