Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.

Abstract: The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The desired layers can be formed by initially depositing a metal-containing layer which comprises metal and halogen atoms. Subsequently, trialkylaluminum is utilized to remove the halogen atoms from the layer. The layer remaining after removal of the halogen atoms can comprise, consist essentially, or consist of any suitable metal, and in particular aspects can consist essentially of, or consist of, titanium or titanium/aluminum.

Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: Disclosed is a method for manufacturing a silicide layer of semiconductor device. The disclosed comprises the steps of: depositing a lower metal layer on the surface of semiconductor substrate and then, performing a plasma treatment; and depositing an upper metal layer on the plasma-treated lower metal layer and then, performing a thermal treatment process, thereby forming a silicide layer on the surface of semiconductor substrate.

Abstract: A method for forming an epitaxial cobalt silicide layer on a MOS device includes sputter depositing cobalt in an ambient to form a first layer of cobalt suicide on a gate and source/drain regions of the MOS device. Subsequently, cobalt is sputter deposited again in an ambient of argon to increase the thickness of the cobalt silicide layer to a second thickness.

Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Abstract: A method for formation of a copper diffusion barrier film using aluminum is disclosed. In the method, thin aluminum (Al) film is deposited on a dielectric, and a surface of the deposited aluminum film is plasma treated with NH3, thereby transforming the surface of the plasma treated aluminum film into a nitride film basically composed of aluminum nitride (AlxNy), and an aluminum film is deposited on the surface of the transformed aluminum nitride film, and copper is deposited on the surface of the deposited aluminum film. Therefore, because the diffusion of copper is suppressed, the problem that leakages between metal lines increase as pitches between the metals decrease due to high integration of parts of semiconductor can be settled.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Abstract: A method of fabricating a gate structure for a MOSFET device, allowing a reduced polysilicon depletion effect as well as increased carrier mobility to be realized, has been developed. The method features a polysilicon-germanium component of the gate structure, sandwiched between an underlying polysilicon seed layer and an overlying polysilicon cap layer. The inclusion of germanium in the deposited polysilicon-germanium component results in enhanced dopant activation and thus a reduced polysilicon depletion effect. The polysilicon seed and cap layers are subjected to low temperature, anneal procedures, performed in situ in a hydrogen ambient, after deposition of the polysilicon layers.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming an insulating film on a conductive pattern formed on a substrate; forming a resist pattern on the insulating film; performing etching to the insulating film using the resist pattern as a mask to form in the insulating film an opening at which part of the surface of the conductive pattern is exposed; forming an antioxidant layer on the part of surface of the conductive pattern exposed while removing the resist pattern; and depositing a conductive film on the conductive pattern from which the antioxidant layer has been removed.

Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract: A multilayered copper structure has been provided for improving the adhesion of copper to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The multilayered copper structure comprises a thin high-resistive copper layer to provide improved adhesion to the underlying diffusion barrier layer, and a low-resistive copper layer to carry the electrical current with minimum electrical resistance. The invention also provides a method to form the multilayered copper structure.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: Disclosed are methods for forming a conductive film or a conductive pattern on a semiconductor substrate, including nitrifying a semiconductor substrate on which a tungsten film having a partially oxidized surface is formed to form a tungsten nitride film on the surface of the tungsten film, oxidizing the surface of the tungsten film having the tungsten nitride film to change the tungsten nitride film into a tungsten oxy-nitride film, and removing the tungsten oxy-nitride film and any residue generated by a reaction of tungsten from the surface of the tungsten film to form a tungsten film. Complete removal of residues generated by a reaction of tungsten from the surface of the tungsten film is made possible. Therefore, resistance of the tungsten film may be reduced, and failures generated by reacted residues formed on tungsten films may be prevented.

Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.

Abstract: A cobalt layer is formed over an entire surface including over a device isolation region. Silicon ions are selectively implanted into only the cobalt layer on the device isolation region and thereafter a silicidation reaction is done, whereby local interconnects are formed between source and drain regions of adjacent MOS transistors.

Abstract: Disclosed is method for forming a barrier metal of a semiconductor device. According to the method, a TiSiN layer having an atomic layer thickness is deposited by performing deposition of an SiH4 layer inside a contact hole of a semiconductor device using an atomic layer deposition process and by performing deposition of a certain precursor layer on the SiH4 layer. By repetition of this ALD process, the TiSiN layer is thickly formed at a desired thickness. Then, the TiSiN layer is plasma processed under the atmosphere of a nitrogen gas and a hydrogen gas, or an ammonia gas, and thus impurities are removed from the TiSiN layer. Therefore, it is easy to thickly form the TiSiN layer for the barrier metal. It is possible to reduce resistivity of the TiSiN layer to a relatively low level. Thereby, it is possible to decrease a contact resistance of the TiSiN layer and, further, to enhance an electrical characteristic of the semiconductor device.

Abstract: The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of copper oxide (105) over the deposited copper seed layer (110) by exposure to a substantially copper-free reducing agent solution (120), such that the copper oxide (105) is substantially converted to elemental copper, followed by electrochemical deposition of a second copper layer (125) over the copper seed layer (110). Such methods and resulting conductive structures thereof may be advantageously used in methods to make integrated circuits comprising interconnection metal lines.

Abstract: The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

Abstract: A recess is formed in a microelectronic substrate, and then a metal-containing layer is formed that conforms to an inner surface of the recess and to a surface of the substrate adjacent the recess. A carbon concentration in a portion of the metal-containing layer on the surface of the substrate adjacent the recess is decreased in comparison to a portion of the metal-containing layer within the recess, e.g., using a plasma treatment that has a greater effect on the surface outside of the recess. Aluminum is then deposited on the metal-containing layer to form an aluminum layer that conforms to the inner surface of the recess and to the surface of the substrate adjacent the recess. Preferably, the carbon concentration in the portion of the metal-containing layer within the recess is sufficiently great to cause aluminum to deposited at a greater rate on the portion of the metal-containing layer within the recess.

Abstract: A method of making a transparent electrode for a light-emitting diode includes depositing metal on a top surface of a semiconductor structure, and defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal, the mask having at least one opening so that the first region is covered by the mask and a second region is aligned with the at least one opening in the mask. The method also includes removing metal aligned with the at least one opening in the mask in the second region to form the first electrode overlying the first region of the semiconductor structure and so as to reveal the top surface of the semiconductor structure in the second region.

Abstract: A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.

Abstract: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies.

Abstract: Introduction of a liquefied gas solution for deposition of a material on a semiconductor substrate. The substrate can have a trench etched thereinto with the solution including ions of the material to be deposited in the trench. The substrate can have a barrier layer at its surface prior to introduction of a liquefied gas solution including ions of a metal to be deposited above the barrier. A material layer to be formed on the substrate can be a tantalum barrier, a copper layer or other semiconductor processing feature.

Abstract: A semiconductor device production method that is used to uniformly and efficiently reduce metal oxides produced on metal (copper, for example) which forms electrodes or wirings on a semiconductor device. An object to be treated on which copper oxides are produced is put into a process chamber and is heated by a heater to a predetermined temperature. Then carboxylic acid stored in a storage tank is vaporized by a carburetor. The vaporized carboxylic acid, together with carrier gas, is introduced into the process chamber via a treating gas feed pipe to reduce the copper oxides produced on the object to be treated to metal copper. As a result, metal oxides can be reduced uniformly without making the surfaces of electrodes or wirings irregular. Moreover, in this case, carbon dioxide and water are both produced in a gaseous state. This prevents impurities from remaining on the surface of copper.

Abstract: A method for fabricating metal gates in deep sub-micron CMOS devices. The method blanket deposits a transition metal nitride layer on top of a gate dielectric layer for forming gate electrodes for both a PMOS and an NMOS device. After a cap layer is deposited on top of the gate electrode for PMOS, a rapid thermal annealing process is carried out to drive out nitrogen from the transition metal nitride on top of the NMOS. Gate electrodes having different work functions on top of the PMOS and NMOS are thus achieved simultaneously by the same fabrication process.

Abstract: A refractory metal layer is deposited onto a substrate having high aspect ratio contracts or vias formed thereon. Next, a plasma-enhanced CVD refractory metal nitride layer is deposited on the refractory metal layer. Then, a metal layer is deposited over the metal nitride layer. The resulting metal layer is substantially void free and has reduced resistivity, and has greater effective line width. Plasma-enhanced chemical vapor deposition of the metal nitride layer comprises forming a plasma of a metal-containing compound, a nitrogen-containing gas, and a hydrogen-gas to deposit a metal nitride layer on a substrate. The metal nitride layer is preferably treated with nitrogen plasma to densify the metal nitride film. The process is preferably carried out in an integrated processing system that generally includes various chambers so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without exposure to possible contaminants.

Abstract: The present invention is related to a metallization structure on a fluorine-containing dielectric. This metallization structure includes a conductive pattern; a fluorine-containing dielectric; and a barrier layer containing a material, i.e. a near noble metal such as Co, Ni, Pt, and Pd. The barrier layer includes at least a first part, being positioned between the fluorine-containing dielectric and the conductive pattern, the first part containing at least a first and a second sub-layer, the first sub-layer contacting the fluorine-containing dielectric being impermeable for fluorine.

Abstract: A conductive connection forming method includes forming a first layer including a first metal on a substrate and forming a second layer including a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material including the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may include annealing the first and second layer. An exemplary first metal includes copper, and an exemplary second metal includes aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer including a first metal over the substrate, and a layer of alloy material within the first metal including layer.

Abstract: A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.

Abstract: A method for forming a wire in a semiconductor device, in forming a titanium film and a titanium nitride film as a barrier metal layer, which can deposit a titanium film and a titanium nitride film each in a different chamber by removing a titanium oxide film used as an insulating film made of upper titanium bonding with oxygen in air as the upper portion of a titanium film is exposed to air by a plasma process and then depositing a titanium nitride film, and as a result can reduce the throughput time of chamber equipment since the partial utilization of the system of the chamber equipment is enabled by driving another chamber even in case one of the chambers breaks down.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP.

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract: A method for formation of a copper diffusion barrier film using aluminum is disclosed. In the method, thin aluminum (Al) film is deposited on a dielectric, and a surface of the deposited aluminum film is plasma treated with NH3, thereby transforming the surface of the plasma treated aluminum film into a nitride film basically composed of aluminum nitride (AlxNy), and an aluminum film is deposited on the surface of the transformed aluminum nitride film, and copper is deposited on the surface of the deposited aluminum film. Therefore, because the diffusion of copper is suppressed, the problem that leakages between metal lines increase as pitches between the metals decrease due to high integrity of parts of semiconductor can be settled.

Abstract: Structures and processes are disclosed for reducing electrical contact resistance between two metal layers. Specifically, a resistive aluminum oxide layer forms spontaneously on metal lines including aluminum, within a V-shaped contact via which is opened in an insulating layer through a mask. The mask includes an opening with a width of less than about 0.75 &mgr;m. After removing the mask, the via is treated with an RF etch. The resultant contact has a width at the bottom of less than 0.9 &mgr;m. A titanium layer of 300 Å to 400 Å is deposited into the via, with about 60 Å to 300 Å reaching the via bottom and reacted with the underlying aluminum. The reaction produces a titanium-aluminum complex (TiAlx) with a thickness of about 150 Å to 900 Å. Advantageously, this composite layer provides a low resistivity contact between the aluminum-containing layer and a subsequently deposited metal layer.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer.

Abstract: A semiconductor device including a silicon-based substrate with recessed features and a tantalum barrier film having at least about 5% silicon incorporated substantially uniformly throughout the film. The device may further include a tantalum barrier film having improved conformality and decreased halogen impurity content. A method for incorporating the silicon into the tantalum barrier layer includes depositing tantalum by PECVD and interrupting deposition at least once to treat the deposited tantalum with a silane containing plasma.

Abstract: A manufacturing method of a semiconductor device of the invention is a method of manufacturing a semiconductor device by forming a plurality of films on an insulating layer which has a surface in which a recess portion is partially formed. The method includes: a base-metal-film forming step of forming a base-metal film including a metal having a high melting point on the surface of the insulating layer including an inside surface of the recess portion, a surface-processing step of processing a surface of the base-metal film by means of an organic solvent having an OH-group, and a metal-for-circuit depositing step of depositing a metal for a circuit on the processed surface of the base-metal film by means of a CVD method in such a manner that at least a part of or the whole of the recess portion is filled up.

Abstract: In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

Abstract: At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal carbide layer is formed by depositing an alternating sequence of metal-containing layers and carbon-containing layers on top of one another and then subjecting them to a heat treatment, in such a manner that they mix with one another. The patterning of the layer sequence can be carried out before the carbide formation step.

Abstract: In order to provide a method of fabricating a high melting point metal wiring layer improved to be capable of forming a thin line without employing a mask, a gate oxide film is formed on a semiconductor substrate. A silicon layer is formed on the gate oxide film. A high melting point metal layer is formed on the silicon layer. A mixed layer of the silicon layer and the high melting point metal layer is formed on a portion for defining a wiring layer. Remaining parts of the silicon layer and the high melting point metal layer other than those forming the mixed layer are removed by etching thereby forming a wiring layer. The wiring layer is heat-treated.

Abstract: A method of fabricating a semiconductor device having copper (Cu) interconnect lines, formed in vias, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.