Abstract: A first method of forming a thin film transistor substrate having at least an electrode interconnection, wherein a first low resistive metal layer is formed, which extends on the top surface of the substrate by sputtering method. A second low resistive metal layer is formed, which is highly resistant to chemicals and extends on the top of the first low resistive metal layer by sputtering method. A photo-resist film is applied on the second low resistive metal layer for exposure and development thereof to form a photo-resist etching mask. The first and second low resistive metal layers are subjected to an isotropic etching by use of the photo-resist etching mask. A third low resistive metal layer which is highly resistant to chemicals are formed over an entire region of the substrate by sputtering method. The third low resistive metal layer is subjected to a reactive ion etching to leave the third low resistive metal layer on the opposite sides of the first low resistive metal layer.

Abstract: A method of forming a barrier layer for preventing the diffusion of a metal interconnect through an interlayer dielectric of an integrated circuit and to act as an etch stop. A thin metal layer is formed on the interlayer dielectric and then oxidized to form a metal-oxide barrier layer.

Abstract: After a contact hole is formed in an insulating film covering the surface of a semiconductor substrate, a Ti layer and a TiON (or TiN) layer are sequentially formed on the insulating film. On the TiON layer an Al alloy layer 18 containing Si is formed, and a reflow thermal treatment is performed after or during the formation of the Al alloy layer in order to improve step coverage. During this thermal treatment, Si nodules are generated. After a Ti layer is formed on the reflowed Al alloy layer, an annealing thermal treatment is performed for 120 seconds at a temperature of 450.degree. to 500.degree. C. With this thermal treatment, Si of Si nodules is absorbed in the Ti layer so that Si nodules are reduced or extinguished. After an antireflection TiN (or TiON) layer is formed on the Ti layer, wiring patterns are formed by using resist patterns as a mask. Since Si nodules are extinguished, wiring resistance can be reduced and an etching time can be shortened.

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a "graded" stoichiometry of material deposited in the recess.

Abstract: A titanium film is formed in a contact hole defined in a silicon substrate. The titanium film is transformed into a titanium silicide film and a first titanium nitride film by high-temperature lamp anneal. Further, a second titanium nitride film is stacked on the first titanium nitride film. Conditions are applied under which the titanium nitride films are formed into a granular crystal of primarily a (200) orientation. Therefore, barrier characteristics of the titanium nitride films to silicon atoms is not compromised even in the case of a subsequent high-temperature thermal treatment.

Abstract: A WSi.sub.x layer wherein the value of x as the stoichiometry of Si is not less than 2.7 and preferably not less than 3.0 is formed by LPCVD based upon reduction of SiCl.sub.2 H.sub.2 of WF.sub.6. Even if this WSi.sub.x film is used without an adhesion layer such as poly Si (polycide structure), it is excellent in adhesion with respect to an SiO.sub.2 film and provides a gate electrode capable of maintaining a satisfactory breakdown voltage value of a gate oxide film. If n-type and p-type impurities are ion-implanted into an nMOS forming region and a pMOS forming region of the WSi.sub.x layer and patterned, a gate electrode of a reduced thickness and a low resistance having a controlled work function may be formed for providing symmetrical threshold voltages.