Forming Silicide Patents (Class 438/664)
  • Patent number: 10147815
    Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua M. Rubin, Tenko Yamashita
  • Patent number: 9812329
    Abstract: There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Woong Chung, Youn Joung Cho, Jung Sik Choi
  • Patent number: 9666676
    Abstract: A method for manufacturing a semiconductor device having a MOS gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., Ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., Ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: May 30, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaaki Ogino
  • Patent number: 9607842
    Abstract: A method of forming a metal silicide can include depositing an interface layer on exposed silicon regions of a substrate, where the interface layer includes a silicide forming metal and a non-silicide forming element. The method can include depositing a metal oxide layer over the interface layer, where the metal oxide layer includes a second silicide forming metal. The substrate can be subsequently heated to form the metal silicide beneath the interface layer, using silicon from the exposed silicon regions, the first silicide forming metal of the interface layer and the second silicide forming metal of the metal oxide layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: March 28, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventor: Jacob Huffman Woodruff
  • Patent number: 9548205
    Abstract: A method of manufacturing a semiconductor device that reduces degradation of device properties includes forming an impurity region in a surface layer of a semiconductor substrate by ion injection; forming a transition metal layer in a surface of the impurity region; and exposing the semiconductor substrate with the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves. The transition metal layer is heated and the heat is transferred from the transition metal layer to the impurity region to form an ohmic contact at the interface of the transition metal layer and the impurity region by reaction of the transition metal layer and the impurity region, and the impurity region is activated. When the substrate is a silicon carbide substrate, the ohmic contact is composed of a transition metal silicide and the impurity region, which is an ion injection layer, is activated.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 17, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi, Masaaki Tachioka
  • Patent number: 9496180
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) and the corresponding device are disclosed. A high-k/metal gate (HK/MG) and a conductive feature are disposed over a substrate, separated by a first dielectric layer. A global hard mask (GHM) layer is formed over the HK/MG, the conductive feature and the first dielectric layer. A second dielectric layer is then formed over the GHM layer. The second dielectric layer is etched to form a first opening to expose a portion of the HK/MG and a second opening to expose a portion of the conductive feature, by using the GHM layer as an etch stop layer. The GHM layer in the first opening and the second opening is then removed.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuen-Ming Liou, Chia-Ying Lee
  • Patent number: 9368586
    Abstract: A transistor including a recessed gate structure having improved doping characteristics and a method for forming such a transistor. The transistor includes a recess in a semiconductor substrate, where the recess is filled with a recessed gate structure including an impurity doped layer and a layer doped with a capture species. The capture species accumulates the impurity and diffuses the impurity to other layers of the recessed gate structure.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Yong-Seok Eun, Mi-Ri Lee
  • Patent number: 9275866
    Abstract: A method of forming a low temperature silicide film on a substrate includes supplying a source gas to a cluster formation chamber to form a gas cluster that is subsequently moved to an ionization-acceleration chamber to form a gas cluster ion beam (GCIB). The GCIB is injected into a processing chamber containing the substrate. A precursor gas is injected through an injection device located on a top portion of the processing chamber to form a silicide film on the substrate by bombarding the substrate with the GCIB in the presence of the precursor gas.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Ahmet S. Ozcan
  • Patent number: 9093424
    Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating more particularly to a structure and method for fabricating silicides with different compositions and/or thicknesses on a single structure having more than one type of device using laser annealing. A method is disclosed that includes using a photoresist compatible with a laser annealing process to protect a region of a semiconductor substrate from silicide formation.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: July 28, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas L. Breil, Oleg Gluschenkov
  • Patent number: 9000494
    Abstract: A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Ying Zhang
  • Patent number: 9000534
    Abstract: According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: April 7, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andreas H. Knorr, Frank Scott Johnson
  • Patent number: 8999855
    Abstract: According one embodiment, a method for manufacturing a semiconductor device is provided, which includes forming a pair of element isolation insulation films on a semiconductor substrate, forming a gate electrode structure on sides of the gate electrode structure, selectively removing oxide films that are formed on a top surface of the diffusion layer and a top surface of the gate electrode by placing the substrate in a gas atmosphere selected from the group consisting of F, Cl, Br, I, H, O, Ar, or N; and irradiating the semiconductor substrate with microwave radiation. The method also includes depositing a metal film on a top surface of the diffusion layer and a top surface of the gate electrode, and a silicide film is formed by heating the substrate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Tomonori Aoyama
  • Publication number: 20150091093
    Abstract: Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: GLOBAL FOUNDRIES, Inc.
    Inventors: Guillaume Bouche, Shao Ming Koh, Jeremy A. Wahl, Andy Wei
  • Patent number: 8993390
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Patent number: 8981565
    Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Dong-Ick Lee, Ahmet Serkan Ozcan, Zhen Zhang
  • Patent number: 8946081
    Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ahmet Serkan Ozcan, Viraj Yashawant Sardesai, Cung Do Tran
  • Patent number: 8946015
    Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 3, 2015
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, Inc.
    Inventors: Anh Duong, Clemens Fitz, Olov Karlsson
  • Patent number: 8937012
    Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: January 20, 2015
    Assignee: Eugene Technology Co., Ltd.
    Inventors: Hai Won Kim, Sang Ho Woo, Sung Kil Cho, Gil Sun Jang
  • Patent number: 8927423
    Abstract: Methods for annealing a contact metal layer for a metal silicidation process are provided in the present invention. In one embodiment, a method for annealing a contact metal layer for a silicidation process in a semiconductor device includes providing a substrate having a contact metal layer disposed thereon in a thermal annealing processing chamber, providing a heat energy to the contact metal layer in the thermal processing chamber, supplying a gas mixture including a nitrogen gas and a hydrogen gas while providing the heat energy to the contact layer in the thermal processing chamber, wherein the nitrogen gas and the hydrogen gas is supplied at a ratio between about 1:10 and about 1:1, and forming a metal silicide layer on the substrate.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 6, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Wei Tang, Kavita Shah, Srinivas Gandikota, San H. Yu, Avgerinos Gelatos
  • Patent number: 8927422
    Abstract: A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
  • Publication number: 20140353825
    Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventors: Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8889552
    Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangline Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wongsang Choi
  • Patent number: 8889554
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 18, 2014
    Assignee: The Institue of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Wei Jiang, Zhijiong Luo, Huilong Zhu
  • Publication number: 20140335646
    Abstract: The present invention is related to a method for forming a metal silicide layer on a textured silicon substrate surface. The method includes providing a metal layer on a textured silicon substrate and performing a pulsed laser annealing step providing at least one UV laser pulse with a laser fluence in the range between 0.1 J/cm2 and 1.5 J/cm2 and with a laser pulse duration in the range between 1 ns and 10 ms. Then, the method includes converting at least part of the metal layer into a metal silicide layer. In addition, the present invention is related to the use of such a method in a process for fabricating a photovoltaic cell, wherein the dielectric layer is a surface passivation layer, or wherein the dielectric layer is an antireflection coating.
    Type: Application
    Filed: November 23, 2012
    Publication date: November 13, 2014
    Inventors: Loic Tous, Monica Aleman, Joachim John, Thierry Emeraud
  • Patent number: 8877583
    Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Young-Pil Kim, Kwan-Heum Lee, Sun-Ghil Lee
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8859398
    Abstract: Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tobias Letz, Frank Feustel, Kai Frohberg
  • Patent number: 8846527
    Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Neil Zhao
  • Publication number: 20140284728
    Abstract: A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.
    Type: Application
    Filed: December 12, 2012
    Publication date: September 25, 2014
    Applicant: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Peng Xu, Wei Zhang, Shi-Li Zhang
  • Patent number: 8835995
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Publication number: 20140248770
    Abstract: A method is provided for removing residual Ni/Pt and/or Pt from a semiconductor substrate in a post salicidation cleaning process using microwave heating of a stripping solution. Embodiments include depositing a Ni/Pt layer on a semiconductor substrate; annealing the deposited Ni/Pt layer, forming a nickel/platinum silicide and residual Ni/Pt and/or Pt; removing the residual Ni/Pt and/or Pt from the semiconductor substrate by: microwave heating a strong acid solution in a non-reactive container; exposing the residual Ni/Pt and/or Pt to the microwave heated strong acid solution; and rinsing the semiconductor substrate with water H2O.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Clemens FITZ, Sven METZGER, Paul R. BESSER, Vincent SIH, Anh DUONG
  • Patent number: 8815736
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Javorka, Stefan Flachowsky, Clemens Fitz
  • Patent number: 8816448
    Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita
  • Patent number: 8815737
    Abstract: The method for the formation of a silicide film herein provided comprises the steps of forming an Ni film on the surface of a substrate mainly composed of Si and then heat-treating the resulting Ni film to thus form an NiSi film as an upper layer of the substrate, wherein, prior to the heat-treatment for the formation of the NiSi film, the Ni film is subjected to a preannealing treatment using H2 gas at a temperature which is less than the heat-treatment temperature and which never causes the formation of any NiSi film in order to remove any impurity present in the Ni film, and the resulting Ni film is then subjected to a silicide-annealing treatment to thus form the NiSi film.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 26, 2014
    Assignee: Ulvac, Inc.
    Inventors: Yasushi Higuchi, Toshimitsu Uehigashi, Kazuhiro Sonoda, Harunori Ushikawa, Naoki Hanada
  • Patent number: 8815738
    Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 26, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Chang Hsu, Bor-Shyang Liao, Kuo-Chih Lai, Nien-Ting Ho, Chi-Mao Hsu, Shu-Min Huang, Min-Chung Cheng
  • Patent number: 8809187
    Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
  • Patent number: 8809140
    Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: August 19, 2014
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, Inc.
    Inventors: Anh Duong, Clemens Fitz, Olov Karlsson
  • Patent number: 8790983
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Tsuchiya, Takashi Shinohe
  • Publication number: 20140206188
    Abstract: A method for forming a metal silicide layer is disclosed. The method includes the steps of: forming a first metal layer with a thickness less than 10 nm on a silicon substrate; forming a second metal layer with a thickness more than 10 nm on the first metal layer; annealing the metal layers and the silicon substrate, so that a part of the second metal layer penetrates through the first metal layer, and both the part of the second metal layer penetrating through the first metal layer and a part of the first metal layer react with the silicon substrate to form the metal silicide layer, while the remaining part of the first and second metal layers form a third metal layer; and removing the third metal layer, so that the metal silicide layer can be formed in the semiconductor substrate.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-His Lee, Chi-Ting Wu
  • Patent number: 8785310
    Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Toshio Hasegawa, Kunihiro Tada, Hideaki Yamasaki, David L. O'Meara, Gerrit J. Leusink
  • Patent number: 8772159
    Abstract: A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: I-Ming Tseng, Tsung-Lung Tsai, Yi-Wei Chen
  • Patent number: 8765603
    Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Wei-Yang Lee, Xiong-Fei Yu, Kuang-Yuan Hsu
  • Patent number: 8759922
    Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8759183
    Abstract: A method of forming a semiconductor device may include forming a metal layer on a silicon portion of a substrate, and reacting the metal layer with the silicon portion to form a metal silicide. After reacting the metal layer, unreacted residue of the metal layer may be removed using an electrolyzed sulfuric acid solution. More particularly, a volume of sulfuric acid in the electrolyzed sulfuric acid solution may be in the range of about 70% to about 95% of the total volume of the electrolyzed sulfuric acid solution, a concentration of oxidant in the electrolyzed acid solution may be in the range of about 7 g/L to about 25 g/L, and a temperature of the electrolyzed sulfuric acid solution may be in the range of about 130 degrees C. to about 180 degrees C.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Shik Heo, Naein Lee, Soonmoon Jung
  • Publication number: 20140167264
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Paul R. Besser, Mark V. Raymond, Valli Arunachalam, Hoon Kim
  • Patent number: 8748256
    Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Gregory Charles Baldwin, Shashank S. Ekbote, Youn Sung Choi
  • Patent number: 8741773
    Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Asa Frye, Andrew Simon
  • Patent number: 8735282
    Abstract: The present invention discloses a semiconductor device and a manufacturing method therefor. Conventionally, platinum is deposited in a device substrate to suppress diffusion of nickel in nickel silicide. However, introducing platinum by means of deposition makes the platinum only stay on the surface but fails to effectively suppress the diffusion of nickel over a desirable depth. According to the present invention, a semiconductor device is formed by implanting platinum into a substrate and forming NiSi in a region of the substrate where platinum is implanted. With the present invention, platinum can be distributed over a desirable depth range so as to more effectively suppress nickel diffusion.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Bing Wu
  • Publication number: 20140131881
    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng
  • Publication number: 20140134817
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshinori TSUCHIYA, Takashi SHINOHE