Including Heat Treatment Of Conductive Layer Patents (Class 438/660)
  • Patent number: 11791268
    Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Travis Rampton, Everett Allen McTeer, Rita J. Klein
  • Patent number: 11446929
    Abstract: A liquid discharging head and an ink-jet apparatus that can achieve stable discharging over time by suppressing clogging of a nozzle due to particles and the like contained in liquid, and by suppressing adhesion of particles to a channel and a diaphragm surface. A liquid discharging head includes a nozzle configured to discharge liquid; a pressure chamber communicated with the nozzle; an individual channel communicated with the pressure chamber through a narrow part; a common channel communicated with the individual channel; an energy generation element configured to generate energy; and a diaphragm configured to convey the energy to the pressure chamber, wherein a monomolecular film is formed at inner walls of the nozzle, the pressure chamber, the narrow part, the diaphragm, and the individual channel, the monomolecular film being lyophilic to the liquid.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: September 20, 2022
    Inventors: Shuhei Nakatani, Kazunobu Irie
  • Patent number: 11432407
    Abstract: An electronic device package includes a molded case, a plurality of leads and a case lid. The molded case includes integrally formed side walls, end walls, and a bottom wall, which together define an interior for components. Each side wall includes top and bottom portions. The top portion includes first and second surfaces extending downward from a top edge of the side wall. The bottom portion has a top surface that extends away from the interior, a third surface extending downward from the top surface to a bottom edge, and a fourth surface extending downward from the second surface to the bottom wall. The leads are molded in the side wall from the bottom edge to the top edge. Each lead has an end extending above the top edge, and another end extending along the bottom edge of the side wall. The case lid is engaged with the molded case.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 30, 2022
    Assignee: XFMRS, Inc.
    Inventors: Tung Kong Luk, Yu Kun Liao
  • Patent number: 11276701
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Collin Howder, Chet E. Carter
  • Patent number: 11189546
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 30, 2021
    Inventors: Josh Lin, Chung-Jen Huang, Yun-Chi Wu, Tsung-Yu Yang
  • Patent number: 11148979
    Abstract: A method is provided for making ceramic bodies having improved properties, such as optical and/or strength properties in which the ceramic bodies are densified by new sintering processes. The sintering profiles may have shorter run times than conventional sintering processes. Ceramic bodies made by these methods are suitable for use in dental applications, for example, as crowns.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 19, 2021
    Assignee: James R. Glidewell Dental Ceramics, Inc.
    Inventors: Sreeram Balasubramanian, Yan Yang, Akash
  • Patent number: 11081601
    Abstract: A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: August 3, 2021
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Matthieu Moors, Taeseok Kim
  • Patent number: 10889734
    Abstract: This invention is directed to stretchable polymer thick film compositions useful for wearable garments. More specifically, the polymer thick film may be used in applications where significant stretching is required, particularly on substrates that can be highly elongated. A particular type of substrate is a thermoplastic polyurethane substrate.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 12, 2021
    Inventors: Michael Zanoni Burrows, Mark Steven Critzer, Jay Robert Dorfman
  • Patent number: 10872814
    Abstract: There is provided a film forming method including: an etching step of etching a portion of a base film to reduce a film thickness of the base film by intermittently supplying a tungsten chloride gas into a processing container while performing a purging step in the course of the intermittent supply of the tungsten chloride gas, wherein the processing container accommodates a substrate, and the base film is formed on a surface of the substrate; and a film forming step of forming a tungsten film on the base film by alternately supplying the tungsten chloride gas and a reducing gas for reducing the tungsten chloride gas into the processing container while performing the purging step in the course of the alternate supply of the tungsten chloride gas and the reducing gas, wherein the film forming step occurs after the etching step.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 22, 2020
    Inventors: Kensaku Narushima, Takanobu Hotta, Atsushi Matsumoto
  • Patent number: 10741397
    Abstract: A method includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening in the dielectric layer. A first layer of metallic material (e.g., non-nitride metal) is deposited to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening. A second layer of metallic material (e.g., copper) is deposited to fill the opening with metallic material. An overburden portion of the second layer of metallic material is removed by planarizing the second layer of metallic material down an overburden portion of the liner layer on the upper surface of the dielectric layer. A surface treatment process (e.g., plasma nitridation) is performed to convert the overburden portion of the liner layer into a layer of metal nitride material. The layer of metal nitride material is selectively etched away using a wet etch process.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10615115
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 7, 2020
    Inventor: Masahiro Inohara
  • Patent number: 10615050
    Abstract: Methods for seam-less gapfill comprising depositing a film in a feature, treating the film to change some film property and selectively etching the film from the top surface are described. The deposition, treatment and etching are repeated to form a seam-less gapfill in the feature.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna, Yihong Chen
  • Patent number: 10604857
    Abstract: An electroplating copper layer includes bamboo-like copper crystal particles having a highly preferred orientation. The bamboo-like copper crystal particles have a long axis direction and a short axis direction, and the bamboo-like copper crystal particles have a length of 20 nm to 5 ?m in the long axis direction and a length of 20 nm to 2 ?m in the short axis direction. A method of preparing the bamboo-like copper crystal particles is also disclosed.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 31, 2020
    Assignee: Suzhou Shinhao Materials LLC
    Inventors: Yun Zhang, Jing Wang, Zifang Zhu, Tao Ma, Luming Chen
  • Patent number: 10580654
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 3, 2020
    Assignee: Lam Research Corporation
    Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
  • Patent number: 10204986
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: February 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Rung-Yuan Lee, Chun-Tsen Lu, Kuan-Hung Chen
  • Patent number: 10096513
    Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Jason A. Farmer, Jeffrey S. Leib, Daniel B. Bergstrom
  • Patent number: 9558996
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: January 31, 2017
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, Jing-Gang Li, Min-Hsien Chen, Jian-Hong Su
  • Patent number: 9349818
    Abstract: A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 24, 2016
    Inventors: Kun-Huang Yu, Shih-Yin Hsiao
  • Patent number: 9266721
    Abstract: A method for producing a semiconductor component (166) is proposed.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: February 23, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Andreas Pruemm, Karl-Heinz Kraft, Thomas Mayer, Arnim Hoechst, Christoph Schelling
  • Patent number: 9054239
    Abstract: A process of forming a front-grid electrode on a silicon wafer having an ARC layer, comprising the steps: (1) printing and drying a metal paste A comprising an inorganic content comprising 0.5 to 8 wt.-% of glass frit and having fire-through capability, wherein the metal paste A is printed on the ARC layer to form a bottom set of thin parallel finger lines, (2) printing and drying a metal paste B comprising an inorganic content comprising 0.2 to 3 wt.-% of glass frit over the bottom set of finger lines, wherein the metal paste B is printed in a grid pattern which comprises (i) thin parallel finger lines forming a top set of finger lines superimposing the bottom set of finger lines and (ii) busbars intersecting the finger lines at right angle, and (3) firing the double-printed silicon wafer, wherein the inorganic content of metal paste B contains less glass frit plus optionally present other inorganic additives than the inorganic content of metal paste A.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: June 9, 2015
    Inventors: Russell David Anderson, Kenneth Warren Hang, Shih-Ming Kao, Giovanna Laudisio, Cheng-Nan Lin, Chun-Kwei Wu
  • Publication number: 20150147880
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Teng-Chun Tsai, Li-Ting Wang, Chi-Yuan Chen, Cheng-Tung Lin, Chi-Hsuan Ni, Chia-Han Lai, Wei-Jung Lin, Huicheng Chang, Huang-Yi Huang
  • Patent number: 9024179
    Abstract: The invention is directed to a polymer thick film conductive composition comprising (a) a conductive silver-coated copper powder; and (b) an organic medium comprising two different resins and organic solvent, wherein the ratio of the weight of the conductive silver-coated copper powder to the total weight of the two different resins is between 5:1 and 45:1. The invention is further directed to a method of electrode grid and/or bus bar formation on thin-film photovoltaic cells using the composition and to cells formed from the method and the composition.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 5, 2015
    Assignee: E I du Pont de Nemours and Company
    Inventor: Jay Robert Dorfman
  • Patent number: 9023253
    Abstract: The present invention provides a conductive paste characterized by a crystal-based corrosion binder being combined with a glass frit and mixed with a metallic powder and an organic carrier. Methods for preparing each components of the conductive paste are disclosed including several embodiments of prepare Pb—Te—O-based crystal corrosion binder characterized by melting temperatures in a range of 440° C. to 760° C. and substantially free of any glass softening transition upon increasing temperature. Method for preparing the conductive paste includes mixture of the components and a grinding process to ensure all particle sizes in a range of 0.1 to 5.0 microns. Method of applying the conductive paste for the formation of a front electrode of a semiconductor device is presented to illustrate the effectiveness of the crystal-based corrosion binder in transforming the conductive paste to a metallic electrode with good ohmic contact with semiconductor surface.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 5, 2015
    Assignee: Soltrium Technology, Ltd
    Inventors: Xiaoli Liu, Ran Guo, Delin Li
  • Publication number: 20150118843
    Abstract: The present disclosure is directed to a physical vapor deposition system configured to heat a semiconductor substrate or wafer. In some embodiments the disclosed physical vapor deposition system comprises at least one heat source having one or more lamp modules for heating of the substrate. The lamp modules may be separated from the substrate by a shielding device. In some embodiments, the shielding device comprises a one-piece device or a two piece device. The disclosed physical vapor deposition system can heat the semiconductor substrate, reflowing a metal film deposited thereon without the necessity for separate chambers, thereby decreasing process time, requiring less thermal budget, and decreasing substrate damage.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 30, 2015
    Inventors: Ming-Chin Tsai, Bo-Hung Lin, You-Hua Chou, Chung-En Kao
  • Publication number: 20150118796
    Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Inventors: Young Do Kweon, Tongbi Jiang
  • Publication number: 20150111378
    Abstract: [PROBLEMS TO BE SOLVED] The present invention provides a method of manufacturing a semiconductor device, which is capable of forming a film having low roughness and resistivity by suppressing a void from being generated during the forming of the film, a substrate processing apparatus and a program.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 23, 2015
    Inventors: Arito OGAWA, Atsuro SEINO
  • Patent number: 8980741
    Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Sylvia Lo, Jing-Cheng Lin, Yen-Hung Chen, Wen-Chih Chiou
  • Patent number: 8981211
    Abstract: An interlayer structure that, in one implementation, includes a combination of an amorphous or nano-crystalline seed-layer, and one or more metallic layers, deposited on the seed layer, with the fcc, hcp or bcc crystal structure is used to epitaxially orient a semiconductor layer on top of non-single-crystal substrates. In some implementations, this interlayer structure is used to establish epitaxial growth of multiple semiconductor layers, combinations of semiconductor and oxide layers, combinations of semiconductor and metal layers and combination of semiconductor, oxide and metal layers. This interlayer structure can also be used for epitaxial growth of p-type and n-type semiconductors in photovoltaic cells.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: March 17, 2015
    Assignee: Zetta Research and Development LLC—AQT Series
    Inventors: Erol Girt, Mariana Rodica Munteanu
  • Patent number: 8975182
    Abstract: A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignees: Nissan Motor Co., Ltd., Sumitomo Metal Mining Co., Ltd., Sanken Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Satoshi Tanimoto, Yusuke Zushi, Yoshinori Murakami, Takashi Iseki, Masato Takamori, Shinji Sato, Kohei Matsui
  • Publication number: 20150061060
    Abstract: A method of manufacturing a semiconductor device provided with an interlayer insulating film formed on a semiconductor substrate, and a plurality of wiring layers formed on the interlayer insulating film. The method includes forming of a first wiring layer closest to the semiconductor substrate among the plurality of wiring layers, and forming of an alloy of a titanium layer and a metal layer by heating treatment. The forming of the first wiring layer includes: forming of a titanium layer on an interlayer insulating film; forming of a metal layer containing a metal capable of forming an alloy with titanium in the titanium layer; forming of an orientation layer on the metal layer; and forming of an aluminum layer on the orientation layer.
    Type: Application
    Filed: August 25, 2014
    Publication date: March 5, 2015
    Inventor: Yukinobu Suzuki
  • Patent number: 8969198
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 8969197
    Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Christopher Parks, Tsong-Lin Tai
  • Patent number: 8962477
    Abstract: A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsuan Chan, Wei-Yang Lee, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8951810
    Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: SK hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Ji Eun Kim, Hee Min Shin, Chong Ho Cho
  • Patent number: 8946083
    Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Ting-Chun Wang, Szu-An Wu
  • Patent number: 8940627
    Abstract: Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgassing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Nthdegree Technologies Worldwide Inc.
    Inventors: Richard A. Blanchard, William J. Ray, Mark D. Lowenthal, Xiaorong Cai, Theodore Kamins
  • Patent number: 8940601
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
  • Patent number: 8937014
    Abstract: A liquid treatment apparatus of continuously performing a plating process on multiple substrates includes a temperature controlling container for accommodating a plating liquid; a temperature controller for controlling a temperature of the plating liquid in the temperature controlling container; a holding unit for holding the substrates one by one at a preset position; a nozzle having a supply hole through which the temperature-controlled plating liquid in the temperature controlling container is discharged to a processing surface of the substrate; a pushing unit for pushing the temperature-controlled plating liquid in the temperature controlling container toward the supply hole of the nozzle; and a supply control unit for controlling a timing when the plating liquid is pushed by the pushing unit. The temperature controller controls the temperature of the plating liquid in the temperature controlling container based on the timing when the plating liquid is pushed by the pushing unit.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: January 20, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Tanaka, Yusuke Saito, Mitsuaki Iwashita
  • Publication number: 20150017802
    Abstract: In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal.
    Type: Application
    Filed: July 13, 2014
    Publication date: January 15, 2015
    Applicant: Bandgap Engineering, Inc.
    Inventors: Joanne Yim, Jeff Miller, Michael Jura, Marcie R. Black, Joanne Forziati, Brian Murphy, Adam Standley
  • Publication number: 20150001644
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 8922003
    Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 30, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Nanyang Technological University
    Inventors: Dexter Xueming Tan, Yoke King Chin, Kin Leong Pey
  • Patent number: 8916804
    Abstract: Provided is a thermal processing method including a first process comprising changing a set temperature of the heating plate from a first temperature to a second temperature; initiating a thermal processing for a first substrate before the temperature of the heating plate reaches the second temperature; obtaining temperature data of the heating plate after the thermal processing is initiated; changing the set temperature of the heating plate from the second temperature when the set temperature reaches the second temperature; and thermal processing of the first substrate using the heating plate for which the set temperature has been changed. The method further includes a second process comprising reinstating the temperature of the heating plate to the second temperature after the thermal processing of the first substrate; and thermal processing of a next substrate using the heating plate while the temperature of the heating plate is maintained at the second temperature.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 23, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Kenichi Shigetomi
  • Publication number: 20140370703
    Abstract: A TSV front-top interconnection process is provided. In an embodiment of the present invention, the stress concentration area of a TSV copper pillar is eliminated, which reduces the possibility of generating delamination or cracks between an insulating layer and the substrate due to stress. Meanwhile, the defect of the existing process that the TSV copper pillar may expose after an electroplating and annealing process is re-used to achieve the interconnection between the TSV copper pillar and the metal redistribution layer.
    Type: Application
    Filed: May 7, 2014
    Publication date: December 18, 2014
    Inventors: Fengwei Dai, Daquan Yu
  • Publication number: 20140353751
    Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Applicant: International Business Machines Corporation
    Inventors: Guy Cohen, Cyril Cabral, Anirban Basu, JR.
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Publication number: 20140308811
    Abstract: A semiconductor integrated-circuit device using the copper wiring having increased electromigration resistance, low resistivity, and a line width of 70 nm or less, is provided. The present invention is characterized by the annealing treatment wherein a copper wiring having a line width of 70 nm or less is heated with a heating rate of 1K to 10K per second, and then the temperature is constantly maintained for a prescribed time duration.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 16, 2014
    Inventors: Yasushi SASAJIMA, Jin OONUKI, Suguru TASHIRO, Khyou Pin KHOO
  • Patent number: 8859415
    Abstract: A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Tajima, Akira Tojo
  • Publication number: 20140295665
    Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventors: Bo ZHENG, Arvind SUNDARRAJAN, Xinyu FU
  • Patent number: 8847380
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 30, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Publication number: 20140284797
    Abstract: A method for fabricating a power semiconductor device that comprises a base substrate with a conductive layer on a surface of the base substrate and semiconductor components mounted on the base substrate includes forming a hardened layer on the surface of the conductive layer before mounting a semiconductor component on the base substrate. The forming of the hardened layer may optionally be performed using a peening process, for example, a shot peening process, a laser peening process, or an ultrasonic peening process. The conductive layer may comprise a metal such as, for example, aluminum or copper.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 25, 2014
    Inventors: Yuuji HISAZATO, Hiroki SEKIYA, Yo SASAKI, Kazuya KODANI, Nobumitsu TADA, Hitoshi MATSUMURA, Tomohiro IGUCHI