Abstract: Provided are a wafer cleaning apparatus based on light irradiation capable of effectively cleaning residue on a wafer without damaging the wafer, and a wafer cleaning system including the cleaning apparatus. The wafer cleaning apparatus is configured to clean residue on the wafer by light irradiation and includes: a light irradiation unit configured to irradiate light onto the wafer during the light irradiation; a wafer processing unit configured accommodate the wafer and to control a position of the wafer such that the light is irradiated onto the wafer during the light irradiation; and a cooling unit configured to cool the wafer after the light irradiation has been completed. The light irradiation unit, the wafer processing unit, and the cooling unit are sequentially arranged in a vertical structure with the light irradiation unit above the wafer processing unit and the wafer processing unit above the cooling unit.

Abstract: Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.

Abstract: A substrate processing method includes providing a processing target substrate having a pattern, forming a film on the substrate, forming a reaction layer on a surface layer of the substrate by plasma, and removing the reaction layer by applying energy to the substrate.

Abstract: Microelectronic assemblies and methods of making the same are disclosed.

Abstract: A semiconductor device according to an embodiment includes a cell region, a gate connection region, and a cell end region between the cell region and the gate connection region. The cell region includes, an n-type first SiC region, a p-type second SiC region, a n-type third SiC region, a p-type fourth SiC region, a gate insulating film, a gate electrode, a first electrode contacting with the first and fourth SiC regions, a second electrode. The gate connection region includes a p-type fifth SiC region between the third SiC region and a field insulating film and having a peak p-type impurity concentration of 1×1018 cm?3 or more. The cell end region includes a p-type sixth SiC region connected to the fifth SiC region, a p-type seventh SiC region having a higher p-type impurity concentration than the sixth SiC region, the first electrode contacting with the sixth and seventh SiC regions.

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate having an oxide layer is provided. At least a portion of the oxide layer is removed and forms a nitride layer. The nitride layer is removed, leaving nitride precipitates. The nitride precipitates are removed using phosphoric acid.

Abstract: To provide a lead-free piezoelectric material having a high and stable piezoelectric constant in a wide operating temperature range. The piezoelectric material contains a perovskite type metal oxide having the general formula (1), Mn, Mg, (Ba1-xCax)a(Ti1-y-zSnyZrz)O3??(1) (wherein x is in the range of 0.050?x?0.200, y is in the range of 0.010?y?0.040, and z is in the range of 0?z?0.040, provided that x?0.375(y+z)+0.050, and a is in the range of 0.9925+b?a?1.0025+b) wherein the amount b (mol) of Mn on a metal basis per mole of the metal oxide is in the range of 0.0048?b?0.0400, and the Mg content on a metal basis per 100 parts by weight of the metal oxide is 0.100 parts by weight or less.

Abstract: There is provided a lead-free piezoelectric material having a high and stable piezoelectric constant and mechanical quality factor in a wide operating temperature range. A piezoelectric material mainly composed of a perovskite type metal oxide having the general formula (1), wherein manganese is incorporated in the metal oxide, and the Mn content is 0.12 parts by weight or more and 0.40 parts by weight or less on a metal basis per 100 parts by weight of the metal oxide. (Ba1-xCax)a(Ti1-y-zSnyZrz)O3??(1) (1.00?a?1.01, 0.125?x?0.300, 0<y?0.020, and 0.041?z?0.069).

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench.

Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

Abstract: A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.

Abstract: In the transistor including an oxide semiconductor film, which includes a film for capturing hydrogen from the oxide semiconductor film (a hydrogen capture film) and a film for diffusing hydrogen (a hydrogen permeable film), hydrogen is transferred from the oxide semiconductor film to the hydrogen capture film through the hydrogen permeable film by heat treatment. Specifically, a base film or a protective film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film. At this time, the hydrogen permeable film is formed on a side which is in contact with the oxide semiconductor film. After that, hydrogen released from the oxide semiconductor film is transferred to the hydrogen capture film through the hydrogen permeable film by the heat treatment.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A first region of a silicon carbide layer constitutes a first surface, and is of a first conductivity type. A second region is provided on the first region, and is of a second conductivity type. A third region is provided on the second region, and is of the first conductivity type. A fourth region is provided in the first region, located away from each of the first surface and the second region, and is of the second conductivity type. A gate insulation film is provided on the second region so as to connect the first region with the third region. A gate electrode is provided on the gate insulation film. A first electrode is provided beneath the first region. A second electrode is provided on the third region.

Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Abstract: A method for preparing a device having a film on a substrate is disclosed. In the method, a film is deposited on a substrate. The film includes a first and a second metal. The first and the second metals in the film are converted to an intermetallic compound using microwave radiation. One example device prepared by the method includes a silicon substrate and a film on the substrate, wherein the film includes semiconducting copper germanide as the intermetallic compound.

Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process.

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a silicon dioxide film on the silicon carbide substrate, and forming an electrode containing Al and Ti to make contact with the silicon carbide substrate and the silicon dioxide film. The step of forming the electrode includes the steps of forming a metal film containing Al and Ti on the silicon carbide substrate, and heating the metal film to not less than 500° C. in an atmosphere in which oxygen gas is introduced. Thereby, the method for manufacturing the silicon carbide semiconductor device capable of improving insulation reliability of an insulating film can be provided.

Abstract: A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

Abstract: A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

Abstract: Certain example embodiments relate to systems and/or methods for preferentially and selectively heat treating conductive coatings such as ITO using specifically tuned near infrared-short wave infrared (NIR-SWIR) radiation. In certain example embodiments, the coating is preferentially heated, thereby improving its properties while at the underlying substrate is kept at low temperatures. Such techniques are advantageous for applications on glass and/or other substrates, e.g., where elevated substrate temperatures can lead to stress changes that adversely effect downstream processing (such as, for example, cutting, grinding, etc.) and may sometimes even result in substrate breakage or deformation. Selective heating of the coating may in certain example embodiments be obtained by using IR emitters with peak outputs over spectral wavelengths where the conductive coating (or the conductive layer(s) in the conductive coating) is significantly absorbing but where the substrate has reduced or minimal absorption.

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

Abstract: A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: A method of performing rapid thermal annealing on a substrate including heating the substrate to a first temperature in a rapid thermal annealing system having a front-side heating source and a backside heating source. The method further includes raising the temperature of the substrate from the first temperature to a second temperature greater than the first temperature. The backside heating source provides a greater amount of heat than the front-side heating source during the raising of the temperature of the substrate.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a silicon dioxide film on the silicon carbide substrate, and forming an electrode containing Al and Ti to make contact with the silicon carbide substrate and the silicon dioxide film. The step of forming the electrode includes the steps of forming a metal film containing Al and Ti on the silicon carbide substrate, and heating the metal film to not less than 500° C. in an atmosphere in which oxygen gas is introduced. Thereby, the method for manufacturing the silicon carbide semiconductor device capable of improving insulation reliability of an insulating film can be provided.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: Methods of performing laser spike annealing (LSA) in forming gallium nitride (GaN) light-emitting diodes (LEDs) as well as GaN LEDs formed using LSA are disclosed. An exemplary method includes forming atop a substrate a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method also includes performing LSA by scanning a laser beam over the p-GaN layer. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.

Abstract: A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction.

Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: In the case of a lens array type homogenizer optical system, the incident angle and intensity of a laser beam 1 entering a large-sized lens (long-axis condenser lens 22) of a long-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while long-axis lens arrays 20a and 20b are reciprocated in a direction corresponding to a long axial direction of a linear beam (X-direction). Therefore, vertical stripes are significantly reduced. Further, the incident angle and intensity of a laser beam 1 entering a large-sized lens (projection lens 30) of a short-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while short-axis lens arrays 26a and 26b are reciprocated in a direction corresponding to a short axial direction of a linear beam (Y-direction). Therefore, horizontal stripes are significantly reduced.

Abstract: This disclosure relates to a passivation composition containing at least one sulfonic acid, at least one compound containing a nitrate or nitrosyl ion, and water. The passivation composition is substantially free of a halide ion.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is first etched and then annealed in a reducing atmosphere or an inert atmosphere to promote the formation of a desired crystal structure and to remove oxygen rich compounds. The binary metal compound may be a metal oxide. Etching the metal oxide (i.e. molybdenum oxide) may result in the removal of oxygen rich phases and the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer.

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract: Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.