Conductive Feedthrough Or Through-hole In Substrate Patents (Class 438/667)
  • Patent number: 11328955
    Abstract: A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Bernhard Goller
  • Patent number: 11289388
    Abstract: A semiconductor die includes semiconductor devices located over a substrate, at least one dielectric material portion that laterally surrounds the semiconductor devices, and interconnect-level dielectric material layers. At least one edge seal ring structure can be provided, each including a composite edge seal via structure and a set of metal barrier structures. The composite edge seal via structure includes a metallic material layer and a dielectric fill material portion. Alternatively or additionally, at least one slit ring structure can laterally surround the semiconductor devices and the metal interconnect structures. Each slit ring structure continuously extends through each of the interconnect-level dielectric material layers and into the at least one dielectric material portion, and includes at least one dielectric material.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 29, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takahiro Tanamachi, Shuya Hatao, Hidetoshi Nakamoto, Michimoto Kaminaga
  • Patent number: 11289402
    Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
  • Patent number: 11264547
    Abstract: A light-emitting device includes a substrate, a first light-emitting chip, a first wavelength conversion member, and a barrier member. The first light-emitting chip is mounted on the substrate. The first wavelength conversion member covers the upper surface of the first light-emitting chip. A first reflective member covers the side surface of the first wavelength conversion member. Further, the barrier member includes an outer wall surrounding the side surfaces of the first light-emitting chip and the first reflective member.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 1, 2022
    Assignee: SEOUL SEMICONDUCTOR CO., LTD.
    Inventors: Hye In Kim, Jung Hun Son
  • Patent number: 11233087
    Abstract: Disclosed is an image sensor including a substrate having a first surface and a second surface opposite to each other, a first photoelectric conversion region and a second photoelectric conversion region in the substrate, a through electrode between the first and second photoelectric conversion regions, an insulation structure on the second surface of the substrate, a first color filter and a second color filter respectively provided on the first and second photoelectric conversion regions, and a photoelectric conversion layer on the insulation structure and electrically connected to the through electrode. The through electrode include a first end adjacent to the first surface and a second end adjacent to the second surface. The first end has a non-planar shape.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhwa Kim, JungHun Kim, Sang-Su Park, Beomsuk Lee, Gang Zhang, Jaesung Hur
  • Patent number: 11211689
    Abstract: A chip antenna includes a first ceramic substrate, a second ceramic substrate, a first patch antenna, a second patch antenna, and a feed via. The second ceramic substrate is disposed to oppose the first ceramic substrate. The first patch antenna includes a seed layer, disposed on a surface of the first ceramic substrate, and a plating layer disposed on the seed layer. The second patch antenna disposed on the second ceramic substrate. The feed via includes a seed layer, formed along an internal wall of a via hole penetrating through the first ceramic substrate in a thickness direction, and a conductive material surrounded by the seed layer in the via hole. The seed layer of the first patch antenna and the seed layer of the feed via are connected to each other.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: December 28, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ji Hyung Jung, Sung Yong An
  • Patent number: 11201258
    Abstract: A method for manufacturing a light emitting device includes: providing an intermediate structure including first and second layered structures arranged in a first direction in a light reflecting member, wherein each of the layered structures includes a first and second electrodes arranged in a second direction, and wherein the intermediate structure has a first surface at which the first and second electrodes are exposed; on the first surface, forming a first hole in the light reflecting member between the first electrodes as viewed in the second direction; on the first surface, forming a second hole in the light reflecting member between the second electrodes as viewed in the second direction; forming a conductive film on exposed surfaces of the first and second electrodes, and in the first and second holes; and severing the light reflecting member and the conductive film at positions that pass through the first and second holes.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 14, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Tadaaki Ikeda, Toru Hashimoto
  • Patent number: 11183454
    Abstract: A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11183384
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a layer to-be-etched including first regions and second regions. A second region includes a second trench region. The method also includes forming a first mask layer over the first and second regions, and forming first trenches discretely in the first mask layer in the first regions. Moreover, the method includes forming a divided doped layer, and implanting dopant ions into the first mask layer disposed outside the second trench region. In addition, the method includes forming a mask sidewall spacer on a sidewall of a first trench after forming the divided doped layer and implanting the dopant ions into the first mask layer disposed outside the second trench region. Further, the method includes forming a second trench in the first mask layer in the second region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 23, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Patent number: 11171130
    Abstract: Semiconductor devices and semiconductor device packages may include at least one first semiconductor die supported on a first side of a substrate. The at least one first semiconductor die may include a first active surface. A second semiconductor die may be supported on a second, opposite side of the substrate. The second semiconductor die may include a second active surface located on a side of the second semiconductor die facing the substrate. The second semiconductor die may be configured to have higher median power consumption than the at least one first semiconductor die during operation. An electronic system incorporating a semiconductor device package is disclosed, as are related methods.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Xiaopeng Qu
  • Patent number: 11127756
    Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 21, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Patent number: 11121033
    Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki-Hong Yang, Ki-Hong Lee
  • Patent number: 11114525
    Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a semiconductor layer sequence having an active region configured to emit radiation, a dielectric layer, a solder layer including a first metal arranged on the dielectric layer and a seed layer arranged between the solder layer and the dielectric layer, wherein the seed layer includes the first metal and a second metal, wherein the second metal is less noble than the first metal, wherein an amount of the second metal in the seed layer is between 0.5 wt % and 10 wt %, and wherein the first metal is Au and the second metal is Zn.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: September 7, 2021
    Assignee: OSRAM OLED GMBH
    Inventor: Guido Weiss
  • Patent number: 11088310
    Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua M. Rubin, Jared Barney Hertzberg, Sami Rosenblatt, Vivekananda P. Adiga, Markus Brink, Arvind Kumar
  • Patent number: 11081420
    Abstract: A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 3, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin-En Chen, Ian Hu, Chih-Pin Hung
  • Patent number: 11075095
    Abstract: A supply flow passage branches into a plurality of upstream flow passages. The plurality of upstream flow passages include a branching upstream flow passage that branches into a plurality of downstream flow passages. A plurality of discharge ports are respectively disposed at a plurality of positions differing in distance from a rotational axis and discharge processing liquids, supplied via the plurality of upstream flow passages, toward an upper surface of a substrate held by a substrate holding unit.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: July 27, 2021
    Inventors: Kenji Kobayashi, Jun Sawashima, Yuta Nishimura, Akito Hatano, Motoyuki Shimai, Toyohide Hayashi
  • Patent number: 11063008
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11063169
    Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 13, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park
  • Patent number: 11049819
    Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 10982144
    Abstract: Provided are a silicon nitride layer etching composition, and more specifically, a silicon nitride layer etching composition, capable of etching the silicon nitride layer at a high selectivity ratio relative to a silicon oxide layer by comprising a polysilicon compound in the etching composition, an etching method of a silicon nitride layer using the same, and a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 20, 2021
    Assignee: ENF TECHNOLOGY CO., LTD.
    Inventors: Dong Hyun Kim, Hyeon Woo Park, Jang Woo Cho, Tae Ho Kim, Myung Ho Lee, Myung Geun Song
  • Patent number: 10937801
    Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Koichiro Nagata, Junpei Kanazawa
  • Patent number: 10867855
    Abstract: One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Honeywell International Inc.
    Inventors: Robert E. Higashi, Son T. Lu, Elenita Chanhvongsak
  • Patent number: 10833016
    Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte
  • Patent number: 10797066
    Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Chanho Kim
  • Patent number: 10748921
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Patent number: 10699954
    Abstract: A method of forming void-free, high aspect ratio through-substrate vias by “bottom-up” electroplating. In one embodiment, the method requires providing a substrate, forming a dielectric layer on the substrate's bottom side, providing at least one perforation through the dielectric layer, forming a via hole through the substrate from its top side to the dielectric layer and over the perforations, forming an isolation layer on the sidewalls of the via hole, forming a metal seed layer on the bottom side of the dielectric layer, electroplating the seed layer such that all of the perforations are plugged, and electroplating up the via hole from the plugs to fill the via hole.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 30, 2020
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Alexandros Papavasiliou, Adam Young, Robert Mihailovich, Jeff DeNatale
  • Patent number: 10651155
    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Michel Koopmans
  • Patent number: 10615029
    Abstract: A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Uwe Seidel
  • Patent number: 10595477
    Abstract: Aspects disclosed herein relate to methods of depositing pure silicon oxide on a substrate using Octamethylcyclotetrasiloxane (OMCTS) precursor. In one aspect, the method generally includes positioning a substrate in a processing chamber, introducing an oxygen-containing gas into the processing chamber, introducing OMCTS precursor into the processing chamber, and reacting the oxygen-containing gas and the OMCTS precursor to remove carbon and deposit pure silicon oxide on the substrate.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lei Guo, Praket P. Jha, Milind Gadre, Deenesh Padhi, Tza-Jing Gung
  • Patent number: 10586824
    Abstract: Disclosed is an image sensor including a substrate having a first surface and a second surface opposite to each other, a first photoelectric conversion region and a second photoelectric conversion region in the substrate, a through electrode between the first and second photoelectric conversion regions, an insulation structure on the second surface of the substrate, a first color filter and a second color filter respectively provided on the first and second photoelectric conversion regions, and a photoelectric conversion layer on the insulation structure and electrically connected to the through electrode. The through electrode include a first end adjacent to the first surface and a second end adjacent to the second surface. The first end has a non-planar shape.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhwa Kim, JungHun Kim, Sang-Su Park, Beomsuk Lee, Gang Zhang, Jaesung Hur
  • Patent number: 10504776
    Abstract: A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Yu-Young Wang, Sen-Bor Jan
  • Patent number: 10504842
    Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte
  • Patent number: 10497668
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Patent number: 10475732
    Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wen-Shiang Liao
  • Patent number: 10418256
    Abstract: A method for producing a glass substrate according to the present invention includes the steps of: (I) forming a through hole (11) in a glass sheet (10); (II) forming a resin layer (20) on a first principal surface of the glass sheet (10) using a resin composition sensitive to light having a predetermined wavelength ?1; (III) photoexposing an area of the resin layer (20) that covers the through hole (11) by irradiating the area with light U having the wavelength ?1 and applied from the direction of a second principal surface of the glass sheet (10); and (IV) forming a through-resin hole (21) by removing the area photoexposed in the step (III). The glass sheet (10) protects the resin layer (20) from the light U so as to prevent the resin layer (20) from being photoexposed by beams of the light U that are incident on the second principal surface of the glass sheet (10) in the step (III).
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 17, 2019
    Assignee: NIPPON SHEET GLASS COMPANY, LIMITED
    Inventors: Keiji Tsunetomo, Hideki Hashizume, Kazuya Ohkawa
  • Patent number: 10347506
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
  • Patent number: 10332761
    Abstract: A supply flow passage branches into a plurality of upstream flow passages. The plurality of upstream flow passages include a branching upstream flow passage that branches into a plurality of downstream flow passages. A plurality of discharge ports are respectively disposed at a plurality of positions differing in distance from a rotational axis and discharge processing liquids, supplied via the plurality of upstream flow passages, toward an upper surface of a substrate held by a substrate holding unit.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 25, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kenji Kobayashi, Jun Sawashima, Yuta Nishimura, Akito Hatano, Motoyuki Shimai, Toyohide Hayashi
  • Patent number: 10319625
    Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Mohit K. Haran, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan
  • Patent number: 10276656
    Abstract: Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Frank Hille, Andre Brockmeier, Francisco Javier Santos Rodriguez, Daniel Schloegl, Hans-Joachim Schulze
  • Patent number: 10270003
    Abstract: Methods and apparatus for forming a bond pad of a semiconductor device such as a backside illuminated (BSI) image sensor device are disclosed. The substrate of a device may have an opening at the backside, through the substrate reaching the first metal layer at the front side of the device. A buffer layer may be formed above the backside of the substrate and covering sidewalls of the substrate opening. A pad metal layer may be formed above the buffer layer and in contact with the first metal layer at the bottom of the substrate opening. A bond pad may be formed in contact with the pad metal layer. The bond pad is connected to the pad metal layer vertically above the substrate, and further connected to the first metal layer of the device at the opening of the substrate.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Hung Cheng
  • Patent number: 10236180
    Abstract: A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: March 19, 2019
    Assignee: Sk hynix Inc.
    Inventor: Jin Ha Kim
  • Patent number: 10199315
    Abstract: An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta Ghate Farooq, John Matthew Safran
  • Patent number: 10199270
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Colin Bombardier, Ming He, Vikrant Chauhan, Anbu Selvam KM Mahalingam, Keith Donegan
  • Patent number: 10163852
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Patent number: 10163693
    Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, James M. Derderian, Xiao Li
  • Patent number: 10157842
    Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, John M. Cotte
  • Patent number: 10115594
    Abstract: A method of forming fine island patterns of semiconductor devices includes: forming a plurality of first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; patterning a plurality of islands in the upper buffer mask layer; separating each of the islands into a plurality of sub-islands; etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 30, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Chiang-Lin Shih, Chih-Ching Lin
  • Patent number: 10024907
    Abstract: A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring, an upper layer connection wiring, and a top layer connection wiring are provided in the multilayer wiring. The through electrode is connected to the bottom layer connection wiring, and a via is arranged at a position other than a position immediately above the through electrode.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Watanabe, Toshihiro Nambu
  • Patent number: 9994007
    Abstract: Disclosed is an apparatus for graphene wet transfer, which includes: a reservoir body having at least two reservoirs; a barrier structure located on the reservoir and having at least one separated space formed by barriers; and a substrate frame located below the barrier structure and having at least one substrate accommodation groove for accommodating a target substrate to which graphene is transferred. Here, each reservoir may be filled with a solution for a wet transfer process, and the graphene may be separately located in each separated space in a floating state in the solution.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 12, 2018
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chulki Kim, Seok Lee, Jae Hun Kim, Taikjin Lee, Minah Seo, Jaebin Choi, Young Min Jhon, Deok Ha Woo, Chaehyun Lim
  • Patent number: RE47709
    Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chun Hsieh, Wei-Cheng Wu, Hsiao-Tsung Yen, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng