Conductive Feedthrough Or Through-hole In Substrate Patents (Class 438/667)
  • Patent number: 10797066
    Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Chanho Kim
  • Patent number: 10748921
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Patent number: 10699954
    Abstract: A method of forming void-free, high aspect ratio through-substrate vias by “bottom-up” electroplating. In one embodiment, the method requires providing a substrate, forming a dielectric layer on the substrate's bottom side, providing at least one perforation through the dielectric layer, forming a via hole through the substrate from its top side to the dielectric layer and over the perforations, forming an isolation layer on the sidewalls of the via hole, forming a metal seed layer on the bottom side of the dielectric layer, electroplating the seed layer such that all of the perforations are plugged, and electroplating up the via hole from the plugs to fill the via hole.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 30, 2020
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Alexandros Papavasiliou, Adam Young, Robert Mihailovich, Jeff DeNatale
  • Patent number: 10651155
    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Michel Koopmans
  • Patent number: 10615029
    Abstract: A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Uwe Seidel
  • Patent number: 10595477
    Abstract: Aspects disclosed herein relate to methods of depositing pure silicon oxide on a substrate using Octamethylcyclotetrasiloxane (OMCTS) precursor. In one aspect, the method generally includes positioning a substrate in a processing chamber, introducing an oxygen-containing gas into the processing chamber, introducing OMCTS precursor into the processing chamber, and reacting the oxygen-containing gas and the OMCTS precursor to remove carbon and deposit pure silicon oxide on the substrate.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lei Guo, Praket P. Jha, Milind Gadre, Deenesh Padhi, Tza-Jing Gung
  • Patent number: 10586824
    Abstract: Disclosed is an image sensor including a substrate having a first surface and a second surface opposite to each other, a first photoelectric conversion region and a second photoelectric conversion region in the substrate, a through electrode between the first and second photoelectric conversion regions, an insulation structure on the second surface of the substrate, a first color filter and a second color filter respectively provided on the first and second photoelectric conversion regions, and a photoelectric conversion layer on the insulation structure and electrically connected to the through electrode. The through electrode include a first end adjacent to the first surface and a second end adjacent to the second surface. The first end has a non-planar shape.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhwa Kim, JungHun Kim, Sang-Su Park, Beomsuk Lee, Gang Zhang, Jaesung Hur
  • Patent number: 10504842
    Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte
  • Patent number: 10504776
    Abstract: A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Yu-Young Wang, Sen-Bor Jan
  • Patent number: 10497668
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Patent number: 10475732
    Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wen-Shiang Liao
  • Patent number: 10418256
    Abstract: A method for producing a glass substrate according to the present invention includes the steps of: (I) forming a through hole (11) in a glass sheet (10); (II) forming a resin layer (20) on a first principal surface of the glass sheet (10) using a resin composition sensitive to light having a predetermined wavelength ?1; (III) photoexposing an area of the resin layer (20) that covers the through hole (11) by irradiating the area with light U having the wavelength ?1 and applied from the direction of a second principal surface of the glass sheet (10); and (IV) forming a through-resin hole (21) by removing the area photoexposed in the step (III). The glass sheet (10) protects the resin layer (20) from the light U so as to prevent the resin layer (20) from being photoexposed by beams of the light U that are incident on the second principal surface of the glass sheet (10) in the step (III).
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 17, 2019
    Assignee: NIPPON SHEET GLASS COMPANY, LIMITED
    Inventors: Keiji Tsunetomo, Hideki Hashizume, Kazuya Ohkawa
  • Patent number: 10347506
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
  • Patent number: 10332761
    Abstract: A supply flow passage branches into a plurality of upstream flow passages. The plurality of upstream flow passages include a branching upstream flow passage that branches into a plurality of downstream flow passages. A plurality of discharge ports are respectively disposed at a plurality of positions differing in distance from a rotational axis and discharge processing liquids, supplied via the plurality of upstream flow passages, toward an upper surface of a substrate held by a substrate holding unit.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 25, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kenji Kobayashi, Jun Sawashima, Yuta Nishimura, Akito Hatano, Motoyuki Shimai, Toyohide Hayashi
  • Patent number: 10319625
    Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Mohit K. Haran, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan
  • Patent number: 10276656
    Abstract: Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Frank Hille, Andre Brockmeier, Francisco Javier Santos Rodriguez, Daniel Schloegl, Hans-Joachim Schulze
  • Patent number: 10270003
    Abstract: Methods and apparatus for forming a bond pad of a semiconductor device such as a backside illuminated (BSI) image sensor device are disclosed. The substrate of a device may have an opening at the backside, through the substrate reaching the first metal layer at the front side of the device. A buffer layer may be formed above the backside of the substrate and covering sidewalls of the substrate opening. A pad metal layer may be formed above the buffer layer and in contact with the first metal layer at the bottom of the substrate opening. A bond pad may be formed in contact with the pad metal layer. The bond pad is connected to the pad metal layer vertically above the substrate, and further connected to the first metal layer of the device at the opening of the substrate.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Hung Cheng
  • Patent number: 10236180
    Abstract: A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: March 19, 2019
    Assignee: Sk hynix Inc.
    Inventor: Jin Ha Kim
  • Patent number: 10199315
    Abstract: An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta Ghate Farooq, John Matthew Safran
  • Patent number: 10199270
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Colin Bombardier, Ming He, Vikrant Chauhan, Anbu Selvam KM Mahalingam, Keith Donegan
  • Patent number: 10163693
    Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, James M. Derderian, Xiao Li
  • Patent number: 10163852
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Patent number: 10157842
    Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, John M. Cotte
  • Patent number: 10115594
    Abstract: A method of forming fine island patterns of semiconductor devices includes: forming a plurality of first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; patterning a plurality of islands in the upper buffer mask layer; separating each of the islands into a plurality of sub-islands; etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 30, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Chiang-Lin Shih, Chih-Ching Lin
  • Patent number: 10024907
    Abstract: A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring, an upper layer connection wiring, and a top layer connection wiring are provided in the multilayer wiring. The through electrode is connected to the bottom layer connection wiring, and a via is arranged at a position other than a position immediately above the through electrode.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Watanabe, Toshihiro Nambu
  • Patent number: 9994007
    Abstract: Disclosed is an apparatus for graphene wet transfer, which includes: a reservoir body having at least two reservoirs; a barrier structure located on the reservoir and having at least one separated space formed by barriers; and a substrate frame located below the barrier structure and having at least one substrate accommodation groove for accommodating a target substrate to which graphene is transferred. Here, each reservoir may be filled with a solution for a wet transfer process, and the graphene may be separately located in each separated space in a floating state in the solution.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 12, 2018
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chulki Kim, Seok Lee, Jae Hun Kim, Taikjin Lee, Minah Seo, Jaebin Choi, Young Min Jhon, Deok Ha Woo, Chaehyun Lim
  • Patent number: 9978708
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • Patent number: 9916986
    Abstract: Aspects of the disclosure include method of making semiconductor structures. Aspects include providing a semiconductor structure including a plurality of spacer, an organic planarization layer, and a SiARC layer. Aspects also include forming an inverted mask on the semiconductor structure, the inverted mask including an inverted mask opening above a portion of the plurality of spacers and a portion of the TiN layer. Aspects also include eroding the portion of the plurality of spacers below the inverted mask opening. Aspects also include depositing a fill material masking the portion of the plurality of spacers below the inverted mask opening and the portion of the TiN layer below the inverted mask opening to generate a masked TiN layer segment and an unmasked TiN layer segment and removing a portion of the unmasked TiN layer segment.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Yann A. Mignot
  • Patent number: 9917009
    Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
  • Patent number: 9865502
    Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenro Nakamura
  • Patent number: 9842773
    Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: December 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenro Nakamura
  • Patent number: 9799672
    Abstract: A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Ick Son, Sung-Hoon Kim
  • Patent number: 9786545
    Abstract: A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Jason Eugene Stephens, Byoung Youp Kim, Craig Michael Child, Jr., Shreesh Narasimha
  • Patent number: 9783907
    Abstract: Al—Mnx/Al—Mny multilayers with a wide range of structures ranging from microcrystalline to nanocrystalline and amorphous were electrodeposited using a single bath method under galvanostatic control from room temperature ionic liquid. By varying the Mn composition by ?1-3 at. % between layers, the grain sizes in one material can be systematically modulated between two values. For example, one specimen alternates between grain sizes of about 21 and 52 nm, in an alloy of average composition of 10.3 at. % Mn. Nanoindentation testing revealed multilayers with finer grains and higher Mn content exhibited better resistance to plastic deformation. Other alloy systems also are expected to be electrodeposited under similar circumstances.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 10, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Wenjun Cai, Christopher A. Schuh
  • Patent number: 9768271
    Abstract: Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 9741687
    Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Nan Shih
  • Patent number: 9716074
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • Patent number: 9679809
    Abstract: A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jongwook Kye, Yan Wang, Chenchen Wang, Wenhui Wang, Lei Yuan, Jia Zeng, Guillaume Bouche
  • Patent number: 9673133
    Abstract: Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwa Park, Kwangjin Moon, Byung Lyul Park, Sukchul Bang
  • Patent number: 9564413
    Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 7, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 9484325
    Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: November 1, 2016
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 9478462
    Abstract: Methods of forming a SAV using a selective SAQP or SADP process are provided. Embodiments include providing on a TiN layer and dielectric layers alternating mandrels and non-mandrel fillers, spacers therebetween, and a metal cut plug through a mandrel or a non-mandrel filler; removing a non-mandrel filler through a SAV patterning stack having an opening over the non-mandrel filler and adjacent spacers, forming a trench; removing a mandrel through a second SAV patterning stack having an opening over the mandrel and adjacent spacers, forming a second trench; etching the trenches through the TiN and dielectric layers; forming plugs in the trenches; removing the mandrels and non-mandrel fillers, forming third trenches; etching the third trenches through the TiN layer; removing the metal cut plug and spacers and etching the third trenches into the dielectric layer; removing the plugs; and filling the trenches with metal.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wenhui Wang, Ryan Ryoung-han Kim, Lei Sun, Erik Verduijn, Yulu Chen
  • Patent number: 9478481
    Abstract: An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a damascene method. Next, a through hole is formed, and a first interlayer insulating film, which is provided with a projected portion that is in the same pattern as a lower insulating film, is exposed within the through hole at the same time. After etching the first interlayer insulating film so that a part of the projected portion remains as an etching residue, a via insulating film is formed and the via insulating film at the bottom of the through hole is etched. After that, a through electrode is formed by plating an electrode material on the inner side of the via insulating film on the through hole.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: October 25, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Toshiro Mitsuhashi
  • Patent number: 9455214
    Abstract: A wafer frontside-backside through silicon via and methods of manufacture are disclosed. The method includes forming a plurality of frontside metalized vias into a partial depth of a substrate. The method further includes forming a backside via in the substrate which exposes, from the backside, the plurality of frontside metalized vias. The method further includes forming a metal in the via in contact with the plurality of metalized frontside vias.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Zeljka Topic-Beganovic, Daniel S. Vanslette
  • Patent number: 9449898
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9431380
    Abstract: A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: August 30, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tab A. Stephens, Michael B. McShane, Perry H. Pelley
  • Patent number: 9425126
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9425098
    Abstract: A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof. The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 23, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang
  • Patent number: 9330947
    Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou-Cheng Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: RE47709
    Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chun Hsieh, Wei-Cheng Wu, Hsiao-Tsung Yen, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng