Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract: A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 ?m.

Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.

Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.

Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer.

Abstract: A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.

Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

Abstract: A wiring board includes a first insulation layer, a first conducive layer having first conductive patterns formed on the first insulation layer, a wiring structure positioned on the first insulation layer and including a second insulation layer and a second conductive layer having second conductive patterns formed on the second insulation layer, multiple conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively, multiple first electrodes formed on the first conductive patterns, respectively, and multiple second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively. The first electrodes and the second electrodes have top surfaces which form the same plane.

Abstract: A method for manufacturing a component having an electrical through-connection is described. The method includes the following steps: providing a semiconductor substrate having a front side and a back side opposite from the front side, producing an insulating trench, which annularly surrounds a contact area, on the front side of the semiconductor substrate, filling the insulating trench with an insulating material, producing an electrical contact structure on the front side of the semiconductor substrate by depositing an electrically conductive material in the contact area, removing the semiconductor material remaining in the contact area on the back side of the semiconductor substrate in order to produce a contact hole which opens up the bottom side of the contact structure, and depositing a metallic material in the contact hole in order to electrically connect the electrical contact structure to the back side of the semiconductor substrate.

Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. A semiconductor structure includes a device substrate, a conductive film, a dielectric film and a conductive plug. The device substrate includes a semiconductor substrate and a conductive structure on an active surface of the semiconductor substrate. The device substrate has a substrate opening passing through the semiconductor substrate and exposing the conductive structure. The conductive film, the conductive plug and the dielectric film between the conductive film and the conductive plug are disposed in the substrate opening.

Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract: A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

Abstract: A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate.

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device includes a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. A guard structure is disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. A portion of the guard structure is disposed within a substrate of the semiconductor chip.

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract: An organic light-emitting diode (OLED) display and a manufacturing method thereof are disclosed. One inventive aspect includes a first substrate, a second substrate, and a first insulation layer, a metal layer and a second insulation layer formed on the first insulation layer. The metal layer is formed on the first insulating layer and has a first through hole. The second insulation layer is formed on the metal layer and has a second through hole. The inventive aspect further includes a sealing member formed by filling the first and second through hole so as to seal the first substrate to the second substrate.

Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.

Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.

Abstract: An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap.

Abstract: A fan out package includes a molding compound, a conductive plug in the molding compound, a dielectric covering the molding compound and a portion of the conductive plug, and an interconnect disposed over the dielectric and contacted with the conductive plug, wherein a width of the interconnect contacting the conductive plug is substantially smaller than a width of the conductive plug in the molding compound, and a width of the interconnect disposed over the dielectric is substantially greater than the width of the conductive plug in the molding compound.

Abstract: A method of manufacturing a wiring substrate, includes, forming an etching stop layer and a first wiring layer on a supporting member, forming a first insulating layer on the first wiring layer, forming a via hole reaching the first wiring layer, and forming the wiring layers of an n-layer and the insulating layers of an n-layer, removing the supporting member and the etching stop layer, thereby forming a build-up intermediate body, forming a second insulating layer on the wiring layer of an n-th layer, and forming a third insulating layer on first wiring layer, forming a via hole reaching the wiring layer of the n-th layer, and forming a via hole reaching the first wiring layer, forming a roughened face to the third insulating layer, and forming a second wiring layer connected to the wiring layer, and forming a third wiring layer connected to the first wiring layer.

Abstract: A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Abstract: A method of manufacturing an integrated circuit device includes forming an inter-level dielectric layer over a semiconductor substrate, forming a transformative layer over the inter-level dielectric layer, forming a protective layer over the transformative layer without allowing the transformative layer to undergo a substantive transformation, and after forming the protective layer, causing the transformative layer to undergo a volume-increasing transformation. The volume-increasing transformation produces a high density material that provides an effective etch stop.

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

Abstract: A method for forming a through wafer via hole in a semiconductor device, wherein the semiconductor device comprises a wafer having a SiC substrate with a front side and a backside, a GaN-based layer formed on the front side of the SiC substrate, and a mask structure formed on the backside of the SiC substrate defining an etching area. The etching area is first descummed A through substrate via hole is formed by etching the etching area through the SiC substrate. The mask structure is removed and the inner surface of the through substrate via hole is cleaned. The inner surface of the through substrate via hole is then descummed A through wafer via hole is formed by etching through the GaN layer in the through substrate via hole. And lastly the inner surface of the through wafer via hole is cleaned.

Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.

Abstract: A semiconductor device and method of fabricating the device are provided, the method including providing an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; forming connection holes to the active region in the insulating layer to expose at least part of the active region, wherein the connection holes include a first portion of a first width and a second portion of a second width, the first portion of the connection holes being adjacent to the active region, and the first width being less than the second width; filling the connection holes with a metal material to form the contacts to the active region. As such, contacts formed for the active region also include a first portion of a first width and a second portion of a second width.

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.

Abstract: An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.

Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.

Abstract: The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.

Abstract: A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Abstract: A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material.

Abstract: A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an interlayer connection by stacking a plurality of such silicon substrates, a through hole of a silicon substrate is filled using molten solder itself. In detail, solid solder placed above the through hole of the silicon substrate is molten and the molten solder is guided to and filled in the internal space. A metal layer can be deposited on an internal surface of the through hole beforehand, and also an intermetallic compound (IMC) can be formed in a portion other than the metal layer.