Abstract: A satisfactory conductive fill of a vertical trench of aspect ratio of at least 20 to 1 in a silicon substrate is obtained by heating the substrate to a temperature of about 375° C. or less in a chamber for chemical vapor deposition along with a mixture of WF6, H2, and SiH4 for filling the trench with tungsten. Also, W(CO)6 may be substituted for the WF6.

Abstract: A method for producing structures having a high aspect ratio includes the following steps: a material of the structure to be produced is provided in the form of a layer, a mask is applied to the layer, the layer is subjected to dry etching using the mask, thereby forming redepositions of the layer material on side walls of the mask and the mask is removed, so that a structure having a high aspect ratio is left behind. The method enables very high (≧1 &mgr;m) and very thin (≦50 nm) structures to be produced in a relatively simple and rapid manner in only very few process steps and with only one mask technique. Structures having such large aspect ratios, particularly when they are composed of a conductive material, cannot be produced, or can be produced only with a high outlay, by using other methods.

Abstract: A method for forming a Cu-thin film includes the steps of coating a dispersion containing Cu-containing ultrafine particles individually dispersed therein on a semiconductor substrate having recessed portions, such as wiring grooves, via holes or contact holes, which have an aspect ratio ranging from 1 to 30; firing the coated semiconductor substrate in an atmosphere which can decompose organic substances present in the dispersion, but never oxidizes Cu to form a Cu-thin film on the substrate; then removing the Cu-thin film on the substrate except for that present in the recessed portions to thus level the surface of the substrate and to form the Cu-thin film in the recessed portions. The method permits the complete embedding or filling of the recessed portions of LSI substrates having a high aspect ratio with a Cu-thin film and thus permits the formation of a conductive, uniform and fine pattern, and further requires a low processing cost.

Abstract: A method of creating ultra-small nibble structures using a modification of an already existing mask is comprised of the steps of depositing a layer of nitride on a circuit being fabricated according to standard MOSFET process steps. A layer of photoresist is patterned using a modification of an existing mask, such as a contact mask modified to include a nibble pattern. The nitride layer and an underlying oxide layer are removed according to the patterned photoresist to create a contact opening and an opening over the field oxide. Spacers may be created in the opening over the field oxide. A conductive layer and a polysilicon layer exposed in the opening over the field oxide are removed extending the opening down to the field oxide to create a nibble structure in the polysilicon layer.

Abstract: A method for preventing tungsten contact plug loss problem after a backside pressure fault problem in a deposition chamber is provided. In the method, first deposited by a silane soak step and a tungsten nucleation layer is subsequently deposited, a heat treating step by a rapid thermal process is carried out at a temperature of at least 600° C. for a time period of at least 10 seconds. The heat treating step significantly improves the uniform distribution of the silicon prenucleation layer and substantially prevents the formation of any tungsten silicide layers such that during an etchback process, the dry etchant utilized does not remove a tungsten silicide layer at a much faster rate and thereby does not result in a plug loss problem.

Abstract: Methods of forming integrated circuitry lines such as coaxial integrated circuitry interconnect lines, and related integrated circuitry are described. An inner conductive coaxial line component is formed which extends through a substrate. An outer conductive coaxial line component and coaxial dielectric material are formed, with the coaxial dielectric material being formed operably proximate and between the inner and outer conductive coaxial line components. In a preferred implementation, the substrate includes front and back surfaces, and a hole is formed which extends through the substrate and between the front and back surfaces. In one implementation, the outer conductive coaxial line component constitutes doped semiconductive material. In another implementation, such constitutes a layer of metal-comprising material. A layer of dielectric material is formed over and radially inwardly of the outer line component. Conductive material is then formed over and radially inwardly of the dielectric material layer.

Abstract: A via is formed between a copper conductor and a second copper conductor in a thin film electronic device with a copper plug interconnecting the copper conductor and the second copper conductor. Form a stop layer over the first copper conductor and a dielectric layer over the stop layer. Pattern the dielectric and etch stop layers by etching a hole therethrough down into a copper conductor leaving an exposed surface of the copper conductor and exposed sidewalls of the dielectric layer and the etch stop layer. Grow a copper germanide (Cu.sub.3 Ge) compound, thin film at the base of the hole on the exposed surface of the copper conductor from exposure to germane GeH.sub.4 gas. Form a barrier layer over the copper germanide (Cu.sub.3 Ge) compound, thin film, the dielectric layer and the first copper conductor. The barrier layer forms a via hole in the hole. Form a second copper conductor including the copper plug over the barrier layer, the copper plug filling the narrow via hole.

Abstract: Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.

Abstract: An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal o

Abstract: Methods of forming electrical connections between conductive layers include the steps of forming a first electrically conductive layer on a substrate and then forming a first protective layer (e.g., Si.sub.3 N.sub.4, poly-Si) which is resistant to a first etchant, on the first electrically conductive layer. A second protective layer (e.g., SiO.sub.2) is then formed on the first protective layer. The second protective layer is preferably resistant to a second etchant which is capable of etching the first protective layer. A mask is then patterned on the second protective layer. The mask is preferably patterned to have an opening therein which extends opposite the first electrically conductive layer. The second protective layer is then selectively etched using the first etchant, to expose a portion of the first protective layer extending opposite the first electrically conductive layer.

Abstract: A process is disclosed for fabricating a semiconductor device with a patterned metal layer (9). A layer (7) of a material with poor adhesion capability to the metal is deposited on the surface of a semiconductor substrate. On the layer (7), pattern lines (8) separated by a distance a are formed of a material with good adhesion capability to the metal, and the metal layer (9) is deposited such that by suitable choice of the ratio of the distance a to its thickness d and of its material properties, the metal layer (9) is caused to adhere only to the pattern lines (8) and to the area of the layer (7) between the pattern lines (8).

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

Abstract: A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization.

Abstract: A method for forming an integrated circuit comprising providing a substrate comprising a node to which electrical connection is to be made; providing a layer of material outwardly of the node; and providing an electrically conductive plug through the layer of material and in electrical connection with the underlying node, the layer of material and conductive plug forming an interlocking discontinuity which effectively prevents displacement of the electrical conductive plug from the node. The present invention also contemplates an integrated circuit wherein an interlocking discontinuity comprises a projection which extends laterally outwardly relative to an electrically conductive plug, or a projection which extends laterally outwardly from a layer of material into an electrically conductive plug.

Abstract: A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

Abstract: A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques.

Abstract: A method is provided for eliminating the dishing effect of the chemical mechanical polishing (CMP) process on wide inlaid conductor leads in the layer of dielectric on a semiconductor device. A silicon dioxide dielectric having narrow and wide trenches is first coated with a blanket deposition of conductor material. The conductor material is coated with a photoresist and patterned with a reverse photo image of the trenches. The photoresist is etched leaving the photoresist over the trenches and the conductor material exposed between the trenches. The conductor material is etched removing the conductor material between the trenches and leaving the original thickness of conductor material over the trenches. The remaining photoresist is removed and the conductor material subject to CMP with the original thickness of conductor material acting to prevent dishing.

Abstract: A process used to create a non-smooth, top surface topography, for a semiconductor substrate, needed to improve the adhesion between a protective molding compound, and the underlying top surface of the semiconductor substrate, has been developed. The process features the creation of the non-smooth, top surface topography, including either: recessed, or etched back, copper damascene structures, in an insulator layer; or copper damascene structures, in a recessed, or etched back, insulator layer. The recessing of the copper damascene structures, or of the insulator layer, is accomplished via selective, dry or wet etch procedures. After formation of a gold wire bond, on the top surface of a copper damascene structure, a protective molding compound is applied, to the underlying, non-smooth, top surface topography.

Abstract: An improved dual damascene process is provided. By a spacer formed on sidewalls of an oxide layer, the method can make a via plug and a metal layer serving as an interconnect simultaneously form in a self-aligned process. Therefore, it can successfully avoid misalignment while forming a via plug and an interconnect.

Abstract: There is provided a method for fabricating a semiconductor device, by which passivation layers are formed with good step coverage to prevent crack or void from being occurred in high aspect ratio of metallization layers and the time for performing the processes can be decreased to enhance the productability and the yield of the device. The method is performed as follows. Over a substrate having completed metallization layers, an oxide layer is formed as a first passivation layer by high-density plasma chemical vapor deposition (HDP-CVD). On the HDP-CVD oxide layer, a nitride layer is formed as a second passivation layer by plasma enhanced chemical vapor deposition (PECVD) or HDP-CVD.

Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

Abstract: A method of fabricating a metal contact in a reduced aspect ratio contact hole. The method begins by forming a first insulating layer and a first barrier layer having a first barrier opening over a substrate. The first insulating layer is anisotropically etched through the first barrier opening forming an upper contact hole. A second barrier layer is formed on the first barrier layer and the first insulating layer. The second barrier layer is anisotropically etched forming spacers on sidewalls of the first insulating layer. The first insulating layer is anisotropically etched using the first barrier layer and the spacers as an etch mask forming a lower contact hole. The first barrier layer and the spacers are removed to form the reduced aspect ratio contact hole. The reduced aspect ratio contact hole is comprised by the upper and lower contact holes. The reduced aspect ratio contact hole is filled with a contact metal to contact the contact region in the substrate.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A fabricating process of a semiconductor device includes the steps of forming a first photoresist layer on a surface of a substrate so as to cover a gate electrode on the substrate, forming a second photoresist layer on the fist photoresist layer with an increased sensitivity, forming a third photoresist layer on the second photoresist layer with a reduced sensitivity, forming an opening in a photoresist structure thus formed of the first through third photoresist layers such that the opening exposes the gate electrode and such that the opening has a diameter that increases gradually from the first photoresist layer to the second photoresist layer. Further, a low-resistance metal layer is deposited on the photoresist structure including the opening, such that the metal layer forms a low-resistance electrode on the gate electrode.

Abstract: Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

Abstract: A method of filling a via less than about 0.16 .mu.m in diameter in an oxide layer of a substrate with a TiN plug deposited by CVD and capping the plug with TiN only. In one embodiment, a first layer of TiN is deposited on a substrate by thermal CVD, and a second layer of TiN is deposited on the first layer by PECVD. Alternatively, a one-step process is used to deposit a TiN layer using either thermal CVD or PECVD. The method eliminates a tungsten layer, and thus eliminates a processing step.

Abstract: A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer.

Abstract: A contact hole for an integrated circuit substrate is fabricated by forming first and second layers on an integrated circuit substrate and a photoresist pattern on the second layer including a first opening therein. The second layer is etched through the first opening to define a sidewall therein while concurrently forming a polymer on the sidewall, so as to form a second opening in the second layer that is smaller than the first opening. The etching step preferably comprises the step of etching the second layer using a fluorocarbon to define a sidewall therein while concurrently forming a fluorocarbon polymer on the sidewall. The first layer is then etched through the second opening to form the contact hole to the integrated circuit substrate. A conductive layer may be formed in the contact hole to form a conductive contact that electrically contacts the integrated circuit substrate.

Abstract: A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench.

Abstract: A semiconductor device has a semiconductor layer such as of Si, an insulator film formed on the semiconductor layer and having a contact hole formed therein, a first contacting layer such as of Ti formed in the contact hole so as to be in contact with the semiconductor layer, a second contacting layer such as of TiN formed on the first contact material, and a contacting material such as W formed on the second contacting layer so as to substantially fill the contact hole. The first contacting layer in as formed state has a thickness of 4 nm or greater, while the second contacting layer as formed has a thickness of 1 nm or greater. The optimum thicknesses of the contacting layers are determined based on the pattern rule, e.g., 3.5 m rule, and the kinds of the materials such as Ti, TiN and W. Electrically stable ohmic contact can be obtained at a high yield.

Abstract: A method of reducing tungsten plug loss in processes for fabrication for silicon-based semiconductor devices that include a tungsten plug in a high aspect ratio contact hole. The invention provides a barrier layer prepared by first forming a conformal layer of titanium nitride by chemical vapor deposition. Afterward, another film of titanium nitride is supplied by plasma vapor deposition. The barrier layer comprises at least these two films, and tungsten is then deposited to at least fill the high aspect ratio film-coated contact hole. Upon removal of excess tungsten as by wet etch back, the tungsten plug remains essentially intact, and any plug loss is insignificant in comparison with the prior art.

Abstract: Methods for forming via holes in inter-level dielectric layers for via connections to underlying electrodes are described. The underlying electrodes do not have electrode pads or enlarged areas of the electrode to contact the conductive material in the via hole. The method avoids the problems of oversize vias and mis-aligned vias. One of the embodiments uses extra wide dielectric spacers formed in two steps on the sidewalls of the underlying electrodes. The spacers provide an effective electrode width greater than the actual width of the electrode thereby increasing the tolerance for both the size and the alignment of the via holes. Another embodiment uses alternate layers of two dielectric materials and etching methods which etch each of the two materials selectively. The dielectric material which is not etched in each step serves as an etch stop layer.

Abstract: The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Abstract: Methods of establishing electrical communication with substrate node locations, methods of forming DRAM circuitry, and semiconductor assemblies are described. In one implementation, a contact opening is formed over a substrate node location with which electrical communication is desired. The contact opening has a base over which a refractory metal layer is formed. A refractory metal silicide layer is formed over the refractory metal layer, and the substrate is exposed to conditions effective to convert the refractory metal layer to a refractory metal silicide. In one embodiment, the refractory metal layer and the refractory metal silicide layer are chemical vapor deposited. In another embodiment, the refractory metal silicide layer comprises a silicide of the refractory metal layer. In a preferred implementation, the refractory metal layer comprises titanium and the refractory metal silicide layer comprises titanium silicide.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method for forming a barrier layer inside a contact in a semiconductor wafer is disclosed herein. The forgoing semiconductor wafer includes a dielectric layer on a silicon contained layer. A portion of the silicon contained layer is exposed by the contact. The method mentioned above includes the following steps.First, form a conductive layer on the topography of the semiconductor wafer by a method other than CVD to increase the ohmic contact to the exposed silicon contained layer. Thus a first portion of the conductive layer is formed on the dielectric layer, and a second portion of the conductive layer is formed on the exposed silicon contained layer. Next, remove the first portion of the conductive layer to expose the dielectric layer. Finally, use a chemical vapor deposition (CVD) method to form the barrier layer on the dielectric layer and the first portion of the conductive layer to prevent said silicon contained layer from exposure.

Abstract: In a method for forming a high aspect ratio structure using copper in an ultra high-speed device, the degree of copper burying is heightened. A high aspect ratio structure, such as a fine connecting hole, is formed in a layer insulating film on a silicon substrate. Then, after a CVD-TiN film is formed to have a thickness of 10 nm on the insulating film, a copper film having a thickness of 1 .mu.m is formed. In this case, the highly pure copper film is formed by controlling film-forming conditions so as to set oxygen and sulfur concentrations in the film equal to a fixed level or lower. Thus, during its burying in the connecting hole, the surface diffusibility and fluidity of the copper film heated by means of laser irradiation are facilitated.

Abstract: A process and resulting product are disclosed for an integrated circuit structure including two or more metal wiring levels interconnected by metal-filled vias. A first insulation layer, such as an oxide layer, is formed over a first metal wiring level on an integrated circuit structure. A via mask layer, such as a nitride mask layer, is then formed over the insulation layer with openings formed in the via mask layer in registry with portions of the underlying metal wiring to which it is desired to make electrical contact by the formation of vias through the first insulation layer. A second insulation layer, which may comprise a second oxide layer, is then formed over the mask layer. A reverse second metal wiring level mask, such as a photoresist mask or another nitride mask, is then formed over the second insulation layer to define the second metal wiring. The second insulation layer is then anisotropically etched with an etchant which is selective to the second level metal wiring mask and the via mask, i.e.

Abstract: A technique is disclosed for general IC structures to modify the layout of electrically unisolated metal lines before patterning same so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer. Upon such standardization of metal line spacing, the intermetal dielectric will be planarized in a single process step of deposition. Circuit layout design modifications can be made by adding electrically isolated dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing between the metal lines and dummy metal features. As the nonstandard spacing between metal lines becomes standardized, an internetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.

Abstract: A method of forming a viahole in an interlayer insulating film without the formation of irregularities on a side wall of the viahole. The method includes a first step of forming a viahole in an interlayer insulating film having a multi-layer structure of plural kinds of insulating layers; a second step of forming a side wall film on a side wall of the viahole; and a third step of removing a native oxide film formed on a bottom portion of the viahole by etching.

Abstract: A forced plug process for high aspect ratio structures. The process comprises the steps of providing a liquid plug in a high aspect ratio structure; increasing a gas pressure to force the liquid plug down into the high aspect ratio structure; and suddenly decreasing the gas pressure allowing the liquid plug to be ejected from the high aspect ratio structure. The process is useful for removing unwanted particles from a high aspect ratio structure, as well as for etching and coating the side walls of the structure.

Abstract: In a method of manufacturing a semiconductor device, when a copper diffusion preventing film portion on the connecting hole bottom portion is to be removed, a film thickness of other portion of the copper diffusion preventing film not to be removed is more thickly formed than that of the to-be-removed copper diffusion preventing film portion on the connecting hole bottom portion, thereby only the copper diffusion preventing film portion to be removed can be removed. The method can extend a durable length of time of a wire and can reduce a resistance of the metal wires in a connecting hole bottom portion by removing a copper diffusion preventing film on the bottom portion of the connecting hole.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided. The method removes metal oxides with .beta.-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed.

Abstract: A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1 Torr. Step coverage of the fill material and sputtering parameters are chosen to satisfy a predetermined relationship. The upper surface of the substrate comprises regions of exposed aluminum, aluminum-copper or copper alloys. After filling the vias and lines, the exposed aluminum, aluminum-copper or copper alloys are reacted with a gas containing germanium to form a germanium alloy over the upper surface of the substrate.

Abstract: The present invention describes a method for forming interconnections in semiconductor device fabrication. A via (or trench) is formed on a semiconductor substrate. A metal layer is deposited over the semiconductor substrate using directional sputtering techniques. The metal layer is deposited such that the resulting metal layer has a large surface area and a high degree of curvature. The metal layer is then reflowed. During reflow, the high degree of curvature of the metal layer improves the migration of the metal layer. Thus the metal layer is distributed in a manner that rapidly and more evenly fills the via thereby forming a reliable interconnection.

Abstract: A method for manufacturing semiconductor device is provided, this method comprises the steps of: depositing a metal film for forming wirings on a substrate; forming a wiring layer, wherein dummy wiring is inserted between wiring space where the dummy wiring can be inserted, and wiring space, where the dummy wiring cannot be inserted, is reduced by widening wiring pattern facing the wiring space; forming an interlayer insulating film on said wiring layer; and flattening surface of the interlayer insulating film. The film can be flattened by a CMP method or by an etchback of entire surface of the film. It is possible to flatten the surface of the semiconductor device cost-effectively and precisely.

Abstract: An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal o

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.