Abstract: A method of forming a doped silicon film on a substrate. According to the present invention, a substrate is placed in a reaction chamber and heated. Next, a silicon containing gas is fed into the reaction chamber to produce a silicon containing gas partial pressure of between 4 and 20 torr.

Abstract: A method of fabricating a semiconductor device includes the steps of forming an inter-layer insulating film, forming a contact hole in the inter-layer insulating film, forming a thin conductive film filling the contact hole and covering the inter-layer insulating film, and forming a contact plug filling the contact hole by etching the thin conductive film and thus exposing the surface of the inter-layer insulating film. The etching is conducted such that, from the time when a surface of the inter-layer insulating film is about to be exposed, the thin conductive film and the inter-layer insulating film are etched under substantially the same etching speed. Plug loss in the contact hole is suppressed so that wiring breakage in the contact hole can be prevented.

Abstract: A method for forming an integrated circuit comprising providing a substrate comprising a node to which electrical connection is to be made; providing a layer of material outwardly of the node; and providing an electrically conductive plug through the layer of material and in electrical connection with the underlying node, the layer of material and conductive plug forming an interlocking discontinuity which effectively prevents displacement of the electrical conductive plug from the node. The present invention also contemplates an integrated circuit wherein an interlocking discontinuity comprises a projection which extends laterally outwardly relative to an electrically conductive plug, or a projection which extends laterally outwardly from a layer of material into an electrically conductive plug.

Abstract: This circuit comprises an insulating substrate covered on at least part of its surface by a fine conducting layer (7) whose geometrical form corresponds to the layout chosen for the circuit; the said conducting layer having one or more very fine grooves (9) with a depth of more than 1 .mu.

Abstract: A method of creating ultra-small nibble structures using a modification of an already existing mask includes the steps of depositing a layer of nitride on a circuit being fabricated according to standard MOSFET process steps. A layer of photoresist is patterned using a modification of an existing mask, such as a contact mask modified to include a nibble pattern. The nitride layer and an underlying oxide layer are removed according to the patterned photoresist to create a contact opening and an opening over the field oxide. Spacers may be created in the opening over the field oxide. A conductive layer and a polysilicon layer exposed in the opening over the field oxide are removed extending the opening down to the field oxide to create a nibble structure in the polysilicon layer.

Abstract: The control speed of semiconductor circuitry is increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are "T-topped" (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

Abstract: The present invention provides a method of fabrication for semiconductor devices which enables a photolithography technique in a fabrication process to have a maximal effect on the transistor characteristics. Polysilicon film 16 and silicon nitride film 17 are formed to active transistor 11 and field shield isolation transistor 12, with isotropic etching of silicon nitride film 17 carried out using a resist pattern 20 which was patterned within the minimum processing width as the mask. Then, using the pattern of silicon nitride film 17 as a mask, thermal oxidation of polysilicon film 16 is carried out. Next, after eliminating silicon nitride film 17, anisotropic etching of polysilicon film 16 is carried out using silicon oxide film 21 as a mask, silicon oxide film 21 being formed by thermal oxidation of polysilicon film 16. In this way, a contact pad 22 formed of polysilicon film 16 is completed.

Abstract: The present invention features a method and an article of manufacture for directly attaching silicon chips to circuit carriers. Both the method and the article of manufacture feature a dissolvable, thin wafer that is soldered first to the chip and then to the circuit board, completing the connection. The wafer article consists of embedded, spaced-apart, flexible wires that fit the connection footprints of both the chip and the carrier board. The wafer is fashioned from a matrix block having a heat-resistant, dissolvable substance which encapsulates the wires. The matrix is cut into thin slices that are wafer-thin. Each slice or wafer of the matrix carrier is then attached to a chip, using solder with an appropriate melting temperature that is thermally compatible with the chip. The solder attaches one end of the embedded wires to the chip.

Abstract: A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

Abstract: A method for fabricating wiring in a semiconductor device in which a conductor line and a contact hole are formed by self-alignment, includes the steps of: forming an insulating layer on a substrate; forming an etch-step layer on the insulating layer; etching the etch-stop layer of a wiring region connected to a window and the insulating layer to a predetermined thickness; forming a mask layer on the etch-stop layer and the insulating layer; etching the mask layer to remove the mask layer at the central part of the window; and etching the insulating layer of the central part of the window so as to form a contact hole. By applying such a method, a highly improved reliability can be obtained, and a process thereof is simplified by a single photolithography. Also, the contact hole is formed by self-alignment in the lengthwise direction and in the vertical direction of the conductor line.

Abstract: A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. A metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first region 15 and a second region 17. An insulating layer 39 is deposited on the metal layer, and the insulating layer 39 is patterned with a conductor pattern of widely-spaced leads and closely-spaced leads. Widely-spaced leads 16 are formed in the first region 15 of the metal layer 14. At least adjacent portions of closely-spaced leads 18 are formed in the second region 17 of the metal layer 14. A low-permittivity material 34 is deposited between adjacent portions of the closely-spaced leads 18. A structural dielectric layer 26 is deposited between at least the widely-spaced leads.

Abstract: A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.

Abstract: A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. Metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first portion 15 and a second portion 17. Widely-spaced leads 16 are formed in the first portion 15 of the metal layer 14, and a first structural dielectric layer 26 is deposited on at least the widely-spaced leads. Closely-spaced leads 18 are formed in the second portion 17 of the metal layer 14, and low-permittivity material 34 is deposited between closely-spaced leads 18. A second structural dielectric layer 36 is deposited on at least low-permittivity material 34 and closely-spaced leads 18.

Abstract: A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer.

Abstract: A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.

Abstract: A process has been developed in which high aspect ratio contact holes, are filled with chemically vapor deposited tungsten plugs, exhibiting little or no seam at the center of the tungsten plug. The process features protection of the tungsten plug from the final removal and overetch steps, needed to remove residual tungsten from areas outside the contact hole. This is accomplished by delaying the residual removal procedure, until the tungsten plug is protected by an overlying interconnect metallization structure.