Abstract: According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.

Abstract: A method of manufacturing electronic devices containing one or more layers of materials that are sensitive to the strong chemicals used to remove cross-linked polymeric layers such as photoresists and antireflective coatings is provided. The cross-linked polymeric layers can be easily removed following etching through the use of certain removable layers disposed between the substrate and the cross-linked polymeric layers.

Abstract: Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries. The method comprises using light at a wavelength of one of 248 nm, 193 nm, or 157 nm to illumimate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted light and non-phase-shifted light passing through the reticle are then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist.

Abstract: A method of fabricating electronic, optical or magnetic devices requiring an array of large numbers of small features in which regions defining individual features of the array are formed by the steps of: (a) depositing a very thin film of a highly soluble solid onto a flat hydrophilic substrate; (b) exposing the film to solvent vapor under controlled conditions so that the film reorganizes into an array of discrete hemispherical islands on the surface; (c) depositing a film of a suitable resist material over the whole surface; (d) removing the hemispherical structures together with their coating of resist leaving a resist layer with an array of holes corresponding to the islands; and (e) subjecting the resulting structure to a suitable etching process so as to form a well at the position of each hole.

Abstract: A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.

Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.

Abstract: The specification describes a contact printing technique for forming patterns of thin films with nanometer resolution over large areas. The procedure, termed here “nanotransfer printing (nTP)”, relies on tailored surface chemistries for transferring thin films, typically metal films, from the raised regions of a stamp to a substrate when these two elements are brought into intimate physical contact. This technique is purely additive, it is fast (<15 s contact times), and the printing occurs in a single processing step at room temperature in open air. nTP is capable of producing patterns with a wide range of features with sizes down to ˜100 nm, and edge resolution better than 25 nm. Electrical contacts and interconnects have been fabricated for high performance organic thin film transistors (TFTs) and complementary inverter circuits, to demonstrate one of the many potential applications for nTP.

Abstract: A method of depositing a metal film on a substrate includes a supercritical preclean step, a supercritical desorb step, and a metal deposition step. Preferably, the preclean step includes maintaining supercritical carbon dioxide and a chelating agent in contact with the substrate in order to remove an oxide layer from a metal surface of the substrate. More preferably, the preclean step includes maintaining the supercritical carbon dioxide, the chelating agent, and an acid in contact with the substrate. Alternatively, the preclean step includes maintaining the supercritical carbon dioxide and an amine in contact with the oxide layer. The desorb step includes maintaining supercritical carbon dioxide in contact with the substrate in order to remove adsorbed material from the substrate.

Abstract: A process that advantageously forms MRAM cells without the application of ion beam milling processes. Unlike conventional processes that rely on ion beam milling processes to remove materials from a magnetoresistive sandwich from areas other than areas that will later form MRAM cell bodies, this process forms a layer of photoresist over areas other than those areas that correspond to MRAM cell bodies. The photoresist is lifted off after the deposition of a magnetoresistive sandwich that forms the MRAM cell bodies, thereby safely removing the magnetoresistive sandwich from undesired areas while maintaining the magnetoresistive sandwich in the areas corresponding to MRAM cell bodies.

Abstract: A method of forming a patterned thin film comprises the steps of forming a first plating layer and a second plating layer. Each of the steps of forming the plating layers includes: the step of forming a coating film by applying a liquid resist to the layer below; the heat processing step of forming a resist layer by performing heat processing on the coating film; the step of forming a frame by patterning the resist layer; and the step of forming the plating layer by plating through the use of the frame. Each of sublayers includes: a first portion having a sidewall and encased in a groove of the frame; and the second portion extending out of the groove. The second portion has overhang portions that overhang and extend more outward than the sidewall of the first portion.

Abstract: Digital circuitry, such as interconnective pads which are patterned as waffles according to the embossing methods for flexible substrates which are disclosed, so as to be especially suited for the interconnection of stacks of circuitry blocks forming digital memory known as Permanent Inexpensive, Rugged Memory (PIRM) cross point arrays.

Abstract: A multilayer ceramic substrate has a first conductive pattern that is transfer-printed on a ceramic substrate using an intaglio plate made of a flexible resin. The intaglio plate has a plurality of grooves with different depts. A first insulation layer is on the first conductive pattern, and a second conductive pattern is on the insulating layer. The two conductive patterns are coupled by a via.

Abstract: A process for producing a pattern of negative electron beam resist comprises: depositing a layer of plasma polymerized fluoropolymer on a face of a substrate, the plasma polymerized fluoropolymer forming the negative electron beam resist; producing an electron beam; moving the electron beam on the layer of plasma polymerized fluoropolymer to define the pattern, the layer then having exposed fluoropolymer areas defining the pattern and unexposed fluoropolymer areas; and removing the unexposed fluoropolymer areas to leave only the pattern on the face of the substrate.

Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

Abstract: A method for forming a conductive layer is disclosed, which has the following steps. First, a substrate is provided, and then a patterned photoresist layer having an undercut is formed on the substrate. After that, at least one conductive layer is deposited on the substrate. Finally, the patterned photoresist layer is lifted off; wherein the shape of the conductive layer remaining on the substrate is complementary to that of the patterned photoresist layer.

Abstract: According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract: An improved and novel method of forming a tiered structure, such as a T-gate structure, including the fabrication of a stabilized resist layer that provides for the prevention of interlayer intermixing with the deposition of subsequent resist layers. The method includes patterning a base resist layer to provide for an opening which will form the stem of the tiered structure and subsequently stabilizing the resist base layer without deforming the stem opening. Next, a resist stack is deposited on an uppermost surface of the stabilized resist layer. Patterning the resist stack provides for an opening on an uppermost layer or portion, and a reentrant profile in a portion of the resist stack adjacent the stabilized resist layer. Metallization and subsequent removal of the resist layers results in a tiered structure, such as a T-gate structure, formed using only low to medium molecular weight, linear polymeric materials such as those used in positive optical resists in optical lithography.

Abstract: A method is provided for forming a device. The method provides a substrate, and provides a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.

Abstract: The present invention provides a method for producing semiconductor device having a planarized structure wherein elevational disparities are removed. The semiconductor is produced by forming insulation layer on the transistor device, coating the photo resist layer on the insulator layer, carrying out patterning so that the contact region is opened, forming the region on which the metal is mounted by removing the insulation layer of the contact region, depositing the electrode metal, and removing the photo resist layer by lift-off process.

Abstract: A method for removal of resist structures used in liftoff patterning of submicron features on structure surfaces, wherein the method does not adversely affect the control of structure thickness nor damage the structure surfaces. The technique comprises the use of a liftoff fluid for solvating the resist, wherein the fluid is assisted by chemical mechanical polishing.

Abstract: The invention relates to a multi-layer structure used in an optical communication field and its manufacturing method in which the capacitance effect between the metal patterns of a Silicon Optical Bench (SiOB) is significantly reduced. The multi-layer structure includes a dielectric layer and conductive patterns on a semiconductor substrate, such that the conductive patterns are separated from each other, wherein the dielectric layer and upper portions of the semiconductor substrate between the conductive patterns are etched out to a predetermined thickness to effectively reduce the capacitance without changing the area or structure of the metal patterns.

Abstract: A method for fabricating a thin-film edge emitter device includes the steps of providing a first conductive layer having a top surface; providing an insulating layer having a top surface disposed above the top surface of the first conductive layer; providing a second conductive layer on the insulating layer; and providing a well in the insulating layer over the first conductive layer and an edge in the second conductive layer proximate the well. Providing the well and the edge includes processing the first conductive, insulating, and second conductive layers by at least one of lift-off processing, photolithography processing, and processing with the use of a pre-formed insulating layer having at least one opening associated with a location of the well. The first conductive layer forms an anode. Lastly, the second conductive layer forms at least one of a cladded cathode having an emissive edge and a control electrode.

Abstract: A method of fabricating a vertically profiled electrode like a T-gate 40 on a semiconductor substrate 20 is described. The method comprises providing a resist structure 34 on the substrate 20, the resist structure 34 containing at least a first resist pattern 24′ arranged on the substrate 20 and having a first opening 26, the first resist being negative resist, and a second resist pattern 32 having a second opening 30 surrounding the first opening 26. The vertical profile of the gate electrode 40 is defined by the contours and the relative location of the first and the second opening 26, 30. On the resist structure 34 a metal 38 is deposited and lift-off is performed to remove the second resist 32 together with the metal 38 deposited thereon.

Abstract: A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.

Abstract: A gate electrode is formed in the following manner. A first resist layer having a first opening is formed on a semiconductor substrate. A second resist layer having a second opening larger than the first opening is formed on the first resist layer. A first conductor layer containing a high-melting-point metal is formed. Subsequently, a second conductor layer containing low-resistance metal is formed, and then the first conductor layer within the second opening is removed by etching. Next, the second resist layer is removed by a lift-off process, and finally the first resist layer is removed by ashing.

Abstract: A process for improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.

Abstract: A process of simultaneously forming a plurality of metal features on a substrate, in which at least one metal feature has undercut sides and at least one metal feature does not have undercut sides involves the application of a lower photoresist feature having rounded sides and an upper photoresist feature having undercut sides wherein the upper photoresist feature is positioned in offset relation to the lower photoresist feature such that one edge of the upper photoresist feature does not extend over the corresponding edge of the lower photoresist feature and the other edge of the upper photoresist feature does extend beyond the corresponding edge of the lower photoresist feature.

Abstract: An method for fabricating a semiconductor device reduces a size of a MOSFET by self aligning a gate electrode with a device isolation insulation film. Thus, the gate electrode is not overlapped with the device isolation insulation film, differently from a conventional method for forming a MOSFET by partially overlapping the gate electrode with the device isolation insulation film in consideration of misalignment and CD variations in a mask process. As a result, a size of the MOSFET is reduced, thereby efficiently achieving the high integration of the semiconductor device.

Abstract: The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the top barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A Cu layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion. The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.

Abstract: In the case of providing a contact hole (2a) in an insulting film (2) on the substrate (1), and forming a wiring on the insulting film to be connected to an exposed portion by the contact hole, a tin film (4) is formed on a location where the wiring is formed, and a paradium film (5) is formed on a location where the wiring is formed by immersing a portion where the tin film is provided in a solution containing a paradium ion (Pd2+). Then, the paradium film is used as a reaction start layer to form a copper film (6) by the electroless plating method. Furthermore, a second copper film may be formed by the electroplating by using the copper film as the feeder layer. By doing so, there is provided a semiconductor device wherein the diffusion of elements of the reaction start layer (the seed layer) into the film is prevented, a copper film having a small specific resistance and excellent conductivity formed with good reliability, and a higher integration can be provided with further fine wiring.

Abstract: A method of fabricating a multi-layer ceramic substrate for forming a first conductive pattern on a ceramic substrate. An intaglio plate is manufactured which has first and second grooves. The grooves are filled with an electroconductive paste. Conductivity of paths in the grooves is increased by deaerating and drying the paste. The intaglio plate is glued to and then separated from a ceramic substrate so that the pattern of the pattern of the electroconductive paste is transferred to the substrate. An insulation layer and a further conductive pattern are then applied.

Abstract: The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the top barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A Cu layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion. The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.

Abstract: A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regions formed therein upon which is formed a low dielectric constant dielectric layer. There is then formed over the substrate a silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first subtractive etching environment the pattern into the hard mask layer. There is then subtractively etched employing the patterned hard mask layer and a second etching environment the pattern into the low dielectric constant dielectric layer, simultaneously stripping the photoresist etch mask layer.

Abstract: A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack on a semiconductor substrate, and forming a protective layer on sidewalls of the gate stack. The protective layer extends horizontally over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer is formed over the protective layer and in contact with a gate conductor of the gate stack and in contact with a diffusion region formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor.

Abstract: There is formed, so as to cover the upper structure (a gold-containing, low-resistance metal layer) of a T- or Y-shaped gate, a thin film (e.g. a thin TiN film) which is not reactive to the low-resistance metal layer, which is resistant to an etching solution to be applied in a later wet etching step, and which has good adhesivity to a resist to be coated in a later step, to prevent the direct contact of the low-resistance metal layer with the resist. In this state, supports are formed.

Abstract: A process for the formation of a wiring pattern, which includes the steps of: exposing a resist through a photomask, the photomask having a pattern whose line width is equal to or less than a resolution limit; and developing the exposed resist to form a resist pattern having groove depressions on the surface thereof, the depressions not reaching the back of the resist pattern. The resist may be a positive resist in which case the resist pattern is formed on an underplate feed film; a plating metal is precipitated on the feed film in a region not covered by the resist pattern; the resist pattern is stripped after the precipitation; and the feed film is selectively removed in a region not covered by the plating metal. Alternatively, the resist may be a negative resist in which case the resist pattern is formed on a substrate; a metallic material is deposited on the resist pattern and the substrate; and the resist is stripped from the substrate to remove the overlying metallic material.

Abstract: The present invention provides apparatus, systems, and methods related to the manufacture of integrated circuits. Specifically, embodiments of the present invention include apparatus designed to provide thorough and reliable fluid mixture for gases used in a semiconductor processing system. In one embodiment of the invention, the gas mixing apparatus comprises a gas mixer housing having a gas inlet, a fluid flow channel, and a gas outlet. The fluid flow channel is fluidly coupled to a plurality of gas sources. The majority of the gas mixture occurs in the fluid flow channel which comprises one or more fluid separators for separating the gas into two or more gas portions and one or more fluid collectors for allowing the gas portions to collide with each other to mix the gas portions. This separation and collection of the gas portions results in a thoroughly mixed gas.

Abstract: A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.

Abstract: An electrically conductive apparatus includes, a) an electrically non-conducting substrate, the substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; b) a capping layer of first electrically conductive material coating the elevated surface only portions of the step wall, the capping layer having outer top and outer side portions; and c) a conductive trace of second electrically conductive material which is different from the first electrically conductive material; the conductive trace overlying the substrate, portions of the step wall not covered by the capping layer, and the outer side portions of the capping layer. Methods are disclosed for producing such a construction, for forming an electrically conductive projection outwardly extending from a substrate, and for providing an electrical interconnection between adjacent different elevation areas on a substrate.

Abstract: A method for monitoring bubble formation in and over a spin-on glass(SOG) layer during the CVD deposition of a superjacent insulative layer is described wherein a monitor wafer is processed either with or without a metal pattern. After a SOG layer has been deposited and cured, a layer of silicon oxide is deposited over it by CVD. If bubbles are formed during the silicon oxide deposition step as a result of out-gassing of the SOG layer, they are entrapped at or near the SOG/silicon oxide interface. The silicon oxide layer is then subjected to a buffered HF etch which exposes the bubbles either by opening them up by eroding the SOG layer underneath the oxide layer or by bringing the surface of the silicon oxide layer closer to the entrapped bubbles, thereby decorating them to make them visible to a white light scanning tool. The monitor wafer is initially scanned just prior to the SOG deposition to obtain a reference scan.

Abstract: The present invention provides an electrooptical panel and electronic appliances provided with the electrooptical panel, wherein production yield and a pixel aperture ratio are not decreased even when pixels are made fine in the electrooptical panel using an active matrix addressing method by TFT addressing. The foregoing problems can be solved by putting a plurality of communication lines into electrical contact with the TFT array substrate via contact holes, wherein a plurality of pixel electrodes addressed using a TFT by the data line and scanning line are provided. A lift-up film is formed under the contact holes formed through an interlayer insulation film to put the drain region of the TFT in electrical contact with the pixel electrode.

Abstract: A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Abstract: A process for increasing the sheet resistance and lowering the temperature coefficient of resistance of a thin film resistor deposited on a wafer, the process comprising ramping the temperature of the wafer to an annealing temperature above the decomposition temperature of the thin film resistor using a radiant heat source such that the wafer reaches the annealing temperature within a ramp up time of from about 5 to 10 seconds, and annealing the wafer at the annealing temperature for an annealing period of from about 50 to 85 seconds.

Abstract: The present invention provides an electrooptical panel and electronic appliances provided with the electrooptical panel, wherein production yield and a pixel aperture ratio are not decreased even when pixels are made fine in the electrooptical panel using an active matrix addressing method by TFT addressing. The foregoing problems can be solved by putting a plurality of communication lines into electrical contact with the TFT array substrate via contact holes, wherein a plurality of pixel electrodes addressed using a TFT by the data line and scanning line are provided. A lift-up film is formed under the contact holes formed through an interlayer insulation film to put the drain region of the TFT in electrical contact with the pixel electrode.

Abstract: Transparent electrodes of a plasma display panel is patterned from a transparent conductive layer by using a lift-off technique; a photo-resist mask is roughened through exposure to oxygen plasma before the deposition of the transparent conductive layer, and the rough surface causes the photo-resist mask to be partially uncovered with the transparent conductive layer, thereby allowing photo-resist remover to rapidly penetrate into the boundary between the photo-resist mask and a glass substrate.

Abstract: Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer.In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses.

Abstract: An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.

Abstract: An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal o

Abstract: A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer.