Abstract: An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal o

Abstract: A method for fabricating an interconnect with high aspect ratio contact members is provided. The interconnect is adapted to make electrical connections with a semiconductor component, such as a die, a wafer, or a chip scale package for testing. The method includes providing a substrate with projections, and forming a first conductive layer on the projections and substrate. The first conductive layer is then patterned using a resist mask having a thickness greater than a height of the projections. The resist mask can be a thick film resist that includes an epoxy resin, an organic solvent and a photo initiator. A second conductive layer is then formed on the projections, and patterned using a second resist mask having a thickness less than the height of the projections. Each contact member includes a projection with a tip portion having an exposed portion of the first conductive layer, and with a portion of the second conductive layer providing an electrical path to the projection.

Abstract: An electrically conductive apparatus includes, a) an electrically non-conducting substrate, the substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; b) a capping layer of first electrically conductive material coating the elevated surface only portions of the step wall, the capping layer having outer top and outer side portions; and c) a conductive trace of second electrically conductive material which is different from the first electrically conductive material; the conductive trace overlying the substrate, portions of the step wall not covered by the capping layer, and the outer side portions of the capping layer. Methods are disclosed for producing such a construction, for forming an electrically conductive projection outwardly extending from a substrate, and for providing an electrical interconnection between adjacent different elevation areas on a substrate.

Abstract: A method of forming a bump electrode, comprises the steps of preparing an Si-substrate having a plurality of bonding pads, forming a core on a substantially central portion of the bonding pad on the substrate, forming a resist layer around the core, which has a greater plan-view shape than the core and is provided with an opening portion through which that portion of the bonding pad, which is located around the core, is exposed, and coating an electric conduction strip having a uniform thickness on peripheral and upper surfaces of the core and on that portion of the bonding pad, which is located around the core, by a plating method.

Abstract: A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.

Abstract: In a method of manufacturing an electronic component for forming a conductor pattern on an insulating substrate by transfer method employing intaglio printing technique, this manufacturing method comprises a step of fabricating an intaglio 20 made of flexible resin forming an insulating layer 23 on a groove 21, a step of filling the groove 21 with Ag paste 24 and drying, a step of overlaying the intaglio 20 on an insulating substrate 2 having a water-soluble resin 28 formed on the surface by pressing a pressing portion 26, freezing, peeling off the intaglio 20 and insulating substrate 2, and transferring the pattern of the Ag paste 24, and a step of firing it and forming a conductor pattern.

Abstract: A fabricating process of a semiconductor device includes the steps of forming a first photoresist layer on a surface of a substrate so as to cover a gate electrode on the substrate, forming a second photoresist layer on the fist photoresist layer with an increased sensitivity, forming a third photoresist layer on the second photoresist layer with a reduced sensitivity, forming an opening in a photoresist structure thus formed of the first through third photoresist layers such that the opening exposes the gate electrode and such that the opening has a diameter that increases gradually from the first photoresist layer to the second photoresist layer. Further, a low-resistance metal layer is deposited on the photoresist structure including the opening, such that the metal layer forms a low-resistance electrode on the gate electrode.

Abstract: In a fabrication method of a semiconductor apparatus, the semiconductor apparatus is made with a selective gold plating process rather than an ion-milling process. A tungsten film (W film) as a current supplying layer is formed on the entire front surface of an insulation film. The insulation film is formed on a GaAs substrate on which devices such as FETs are formed. With a mask of a photoresist film, a titanium (Ti) film, a platinum (Pt) film, and a gold (Au) film are successively evaporated and then lift-off process is performed. A photoresist film is patterned. A gold plate film with a thickness of 8 .mu.m is formed. The current supplying layer is removed by magnetron discharge plasma ion-etching process. Thick U-shaped gold plate lines are formed.

Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.

Abstract: A production method for forming contact structures on a planar surface of a substrate.

Abstract: An insulating film is formed by CVD on the surface of a semiconductor substrate formed with circuit elements such as transistors, and thereafter a hydrogen silsesquioxane resin film is formed on the insulating film by spin-coating or the like. This resin film is sequentially subjected to low temperature annealing at 400.degree. C. or lower and then to high temperature annealing at 700.degree. C. or higher. The low temperature annealing changes the resin film into a silicon oxide film, and the high temperature annealing is performed in order to make dense the film quality of the silicon oxide film. The high temperature annealing is performed by rapid thermal annealing in an oxidizing atmosphere of water vapor or the like. A CVD insulating film is formed on the densified silicon oxide film and planarized by CMP or the like, according to necessity. A contact hole is formed through the CVD insulating film, densified silicon oxide film and the insulating film, and a wiring layer is thereafter deposited.

Abstract: A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

Abstract: In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in first regions of the resist layer corresponding to regions where the electrodes are formed, while dummy apertures are also formed in a second region of the resist layer in a rest part other than the first regions. Thereafter, the insulating layer is etched using the resist layer as a mask. With the resist layer remaining, electrode material is accumulated on the surface of the semiconductor wafer, and thereafter, the resist layer is removed. As a result, electrodes with desirable ohmic characteristics are stably formed.

Abstract: An electrically conductive apparatus includes a) an electrically non-conducting substrate, the substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; b) a capping layer of first electrically conductive material coating the elevated surface only portions of the step wall, the capping layer having outer top and outer side portions; and c) a conductive trace of second electrically conductive material which is different from the first electrically conductive material; the conductive trace overlying the substrate, portions of the step wall not covered by the capping layer, and the outer side portions of the capping layer. Methods are disclosed for producing such a construction, for forming an electrically conductive projection outwardly extending from a substrate, and for providing an electrical interconnection between adjacent different elevation areas on a substrate.

Abstract: A method for forming contact holes of a semiconductor device, capable of preventing a photoresist film pattern used as a contact hole mask separating from a boro-phospho silicate glass (BPSG) film disposed of beneath the photoresist film pattern due to an over-etching of the BPSG film occurring when the BPSG film is wet etched. The method includes sequentially laminating a thin insulating film and a planarizing BPSG film over a semiconductor substrate, thermally treating the BPSG film at a temperature ranging from 80.degree. C. to 350.degree. C. and depositing a photoresist film over the BPSG film in a continuous manner with the same equipment used in the thermal treatment, removing a desired portion of the photoresist film, thereby forming a photoresist film pattern, wet etching an exposed portion of the BPSG film not covered with the photoresist film pattern to a desired depth, and dry etching the remaining BPSG film along with the insulating film, thereby forming contact holes.

Abstract: A method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The method comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 .OMEGA.-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600.degree. to 900.degree. C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500.

Abstract: A process for forming aluminum interconnect structures has been developed, that concentrates on alleviating the effects of the poor step coverage of the interconnect metallization, that develops in areas where aluminum overlies tungsten filled contact holes. A high pressure treatment of the aluminum based metallization layer is performed at pressures in the range of 50 to 120 Mega-pascal, to improve the coverage of the aluminum based layer, specifically in seams or voids in the underlying tungsten plugs.

Abstract: Method for fabricating a semiconductor device is disclosed, including the steps of: forming a first resist layer on a substrate; patterning a predetermined region of the first resist layer to form a pattern having a first width which exposes the substrate; forming an insulating film on an entire surface of the substrate including the first resist layer; forming a second resist layer on the insulating film; patterning a predetermined region of the second resist layer to form a pattern over the pattern of the first resist layer having a second width which exposes the insulating film; using the second resist layer as a mask in etching the exposed insulating film to form sidewall spacers at sides of the pattern of the first resist layer; forming a metal layer on an entire resultant surface including the second photoresist layer; and, removing the first and second resist layers and the insulating film to form a T form gate electrode.