Evaporative Coating Of Conductive Layer Patents (Class 438/679)
  • Patent number: 9287377
    Abstract: A semiconductor device includes a trench extending into a semiconductor body from a first surface. At least one of a ternary carbide and a ternary nitride is in the trench.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: March 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Glaser, Peter Irsigler, Hans-Joachim Schulze
  • Patent number: 9275794
    Abstract: An object of the present invention is to provide an R—Fe—B based sintered magnet that exhibits excellent corrosion resistance and maintains excellent adhesion strength to an adherend even under severe conditions, and a method for producing the same. A corrosion-resistant magnet of the present invention as a means for achieving the object is characterized by comprising a chemical conversion film containing at least Zr, V, Al, fluorine, and oxygen as constituent elements and not containing phosphorus over a surface of an R—Fe—B based sintered magnet with a film made of Al or an alloy thereof therebetween.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: March 1, 2016
    Assignee: HITACHI METALS, LTD.
    Inventors: Atsushi Kikugawa, Koshi Yoshimura, Yoshimi Tochishita, Masanao Kamachi, Nobuhiro Misumi
  • Patent number: 9224803
    Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: December 29, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Zusing Yang, Fang-Hao Hsu, Hong-Ji Lee
  • Publication number: 20150130069
    Abstract: A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such as flexible electronic circuits, is described.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Ankit Mahajan, Carl Daniel Frisbie, Lorraine F. Francis
  • Patent number: 8956698
    Abstract: Systems and methods for depositing complex thin-film alloys on substrates are provided. In particular, systems and methods for the deposition of thin-film Cd1-xMxTe ternary alloys on substrates using a stacked-source sublimation system are provided, where M is a metal such as Mg, Zn, Mn, and Cu.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: February 17, 2015
    Assignee: Colorado State University Research Foundation
    Inventors: Walajabad S. Sampath, Pavel S. Kobyakov, Kevin E. Walters, Davis R. Hemenway
  • Patent number: 8888916
    Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Ming-Kuei (Michael) Tseng, Norman L. Tam, Yoshitaka Yokota, Agus S. Tjandra, Robert Navasca, Mehran Behdjat, Sundar Ramamurthy, Kedarnath Sangam, Alexander N. Lerner
  • Patent number: 8809192
    Abstract: A method for deposition of at least one electrically conducting film on a substrate, wherein the method includes the steps of: selecting a layer of a film material, wherein the layer includes a mask on a front side, and wherein the layer and the mask are one piece; positioning the front side of the layer upon the substrate; applying at least one laser pulse onto a back side of the layer, so as to melt and to vaporize at least parts of the layer such that melt droplets are propelled toward and deposited upon the substrate; and forming the film, wherein at least one slot of the mask limits the distribution of the melt droplets.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: August 19, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Dietrich Bertram, Jochen Hugo Stollenwerk, Johannes Krijne, Holger Schwab, Edward Willem Albert Young, Jeroen Henri Antoine Maria Van Buul, Andres Gasser, Konrad Wissenbach, Christian Vedder, Norbert Pirch
  • Patent number: 8778801
    Abstract: A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Bin Chiang, Hung-Chih Wang, Kuei-Pin Lee, Chi-Yu Chou, Yao Hsiang Liang
  • Patent number: 8778081
    Abstract: Systems and methods for depositing complex thin-film alloys on substrates are provided. In particular, systems and methods for the deposition of thin-film Cd1-xMxTe ternary alloys on substrates using a stacked-source sublimation system are provided, where M is a metal such as Mg, Zn, Mn, and Cu.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: July 15, 2014
    Assignee: Colorado State University Research Foundation
    Inventors: Walajabad S. Sampath, Pavel S. Kobyakov, Kevin E. Walters, Davis R. Hemenway
  • Patent number: 8673777
    Abstract: An apparatus for vapor deposition of a sublimated source material as a thin film on a substrate is provided. The apparatus includes a receptacle configured to hold a source material and a distribution plate positioned above the receptacle. The distribution plate defines a pattern of passages therethrough. The apparatus also includes a conveyor configured to travel in a continuous loop such that its transfer surface passes above the distribution plate in a first direction to receive thereon sublimated source material passing through the passages of the distribution plate. The conveyor is also configured to travel in a second direction while carrying a substrate on its raised edges. A heating system heats the conveyor while it travels in the second direction to transfer the source material from the transfer surface to the substrate. A process is provided for vapor deposition of a sublimated source material to form thin film.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 18, 2014
    Assignee: First Solar, Inc.
    Inventors: Russell Weldon Black, Scott Daniel Feldman-Peabody, Christopher Rathweg
  • Patent number: 8575027
    Abstract: Provided are methods and systems for forming discreet multilayered structures. Each structure may be deposited by in situ deposition of multiple layers at one of multiple site isolation regions provided on the same substrate for use in combinatorial processing. Alignment of different layers within each structure is provided by using two or more differently sized openings in-between one or more sputtering targets and substrate. Specifically, deposition of a first layer is performed through the first opening that defines a first deposition area. A shutter having a second smaller opening is then positioned in-between the one or more targets and substrate. Sputtering of a second layer is then performed through this second opening that defines a second deposition area. This second deposition area may be located within the first deposition area based on sizing and alignment of the openings as well as alignment of the substrate.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Sean Barstow, Owen Fong
  • Patent number: 8492196
    Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin
  • Patent number: 8435829
    Abstract: A method of producing a light-emitting element is provided. The method includes forming a first half-transmitting/reflecting film and a second half-transmitting/reflecting film sequentially on an organic layer by physical vapor deposition.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Eisuke Negishi, Jiro Yamada, Mitsuhiro Kashiwabara, Hirofumi Nakamura, Seonghee Noh
  • Patent number: 8409985
    Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: April 2, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
  • Patent number: 8349731
    Abstract: Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Errol Todd Ryan
  • Patent number: 8329502
    Abstract: Method of applying a conformal coating to a highly structured substrate and devices made by the disclosed methods are disclosed. An example method includes the deposition of a substantially contiguous layer of a material upon a highly structured surface within a deposition process chamber. The highly structured surface may be associated with a substrate or another layer deposited on a substrate. The method includes depositing a material having an amorphous structure on the highly structured surface at a deposition pressure of equal to or less than about 3 mTorr. The method may also include removing a portion of the amorphous material deposited on selected surfaces and depositing additional amorphous material on the highly structured surface.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: David S. Ginley, John Perkins, Joseph Berry, Thomas Gennett
  • Patent number: 8299341
    Abstract: Solid and hollow cylindrical nanopillars with nanoscale diameters are provided. Also provides is a method of making such nanopillars using electron beam lithography followed by the electroplating.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 30, 2012
    Assignee: The California Institute of Technology
    Inventors: Julia R. Greer, Michael Burek
  • Patent number: 8268725
    Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: September 18, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
  • Patent number: 8198120
    Abstract: An optical article and method of making the same are provided. The optical article has optical multi-aperture operation. The optical article has one or more electrically conductive and selectively passivated patterns.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: June 12, 2012
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Jitendra S. Goela, Michael A. Pickering, Neil D. Brown, Angelo Chirafisi, Mark Lefebvre, Jamie L. Triba
  • Patent number: 8183082
    Abstract: A method of fabricating organic solar arrays for application in DC power supplies for electrostatic microelectromechanical systems (MEMS) devices. A solar array with 20 miniature cells (as small as 1 mm2) interconnected in series is fabricated and characterized. Photolithography is used to isolate individual cells and output contacts of the array, whereas the thermal-vacuum deposition is employed to make the series connections of the array. With 1 mm2 for single cell and a total device area of 2.2 cm2, the organic solar array based on bulk heterojunction structure of ?-conjugated polymers and C60 derivative (6,6)-phenyl C61 butyric acid methyl ester produces an open-circuit voltage of 7.8 V and a short-circuit current of 55 ?A under simulated air mass (AM) 1.5 illumination with an intensity of 132 mW/cm2. The present method can be used in the fabrication of microarrays as small as 0.01 mm2.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: May 22, 2012
    Assignee: University of South Florida
    Inventors: Jason Lewis, Jian Zhang, Xiaomei Jiang
  • Patent number: 8168543
    Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 1, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
  • Patent number: 8133811
    Abstract: A semiconductor device, which suppresses formation of an organic impurity layer and has excellent adhesiveness to a copper film and a metal to be a base, is manufactured. A substrate (wafer W) coated with a barrier metal layer (base film) 13 formed of a metal having a high oxidation tendency, such as titanium, is placed in a processing chamber. At the time of starting to supply water vapor or after that, a material gas containing an organic compound of copper (for instance, Cu(hfac)TMVS) is supplied, and a copper film is formed on the surface of the barrier metal layer 13 whereupon the oxide layer 13a is formed by the water vapor. Then, heat treatment is performed on the wafer W, and the oxide layer 13a is converted into an alloy layer 13b of a metal and copper which constitute the barrier metal layer 13.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: March 13, 2012
    Assignee: Tokyo Electrcn Limited
    Inventors: Yasuhiko Kojima, Taro Ikeda, Tatsuo Hatano
  • Patent number: 8105872
    Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: January 31, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin
  • Patent number: 8101521
    Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: January 24, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Juwen Gao, Lana Hiului Chan, Panya Wongsenakhum
  • Patent number: 8093136
    Abstract: A single crystal semiconductor substrate and a base substrate are prepared; a first insulating film is formed over the single crystal semiconductor substrate; a separation layer is formed by introducing ions at a predetermined depth through a surface of the single crystal semiconductor substrate; plasma treatment is performed on the base substrate so as to planarize a surface of the base substrate; a second insulating film is formed over the planarized base substrate; a surface of the first insulating film is bonded to a surface of the second insulating film by making the surface of the single crystal semiconductor substrate and the surface of the base substrate face each other; and a single crystal semiconductor film is provided over the base substrate with the second insulating film and the first insulating film interposed therebetween by performing separation at the separation layer.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Shunpei Yamazaki
  • Patent number: 8087380
    Abstract: A plurality of chamber are arranged about a transport chamber. The linear transport chamber may include a linear track supporting robot arms. The robot arms transport substrates to and from the chambers. Each chamber includes a plurality of evaporators, each controlled independently. Each substrate positioned in the chamber is coated from a plurality of the evaporators, such that by controlling the operation of each evaporator independently the formation of the layers and the concentration gradient of each layer can be precisely controlled.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: January 3, 2012
    Assignee: Intevac, Inc.
    Inventors: Terry Bluck, Michael S. Barnes, Kevin P. Fairbairn
  • Publication number: 20110318924
    Abstract: The invention relates to a method for deposition of at least one electrically conducting film (20) on a substrate (30), comprising the steps: selecting a layer (10) of a film material, wherein the layer (10) comprises a mask (40) on a front side (11) and wherein the layer (10) and the mask (40) are one piece, positioning the front side (11) of the layer (10) upon the substrate (30), applying at least one laser pulse (120) onto a back side (12) of the layer (10), so as to melt and to vaporize at least parts of the layer (10) such that melt droplets (110) are propelled toward and deposited upon said substrate (30), forming the film (20), wherein at least one slot (45) of the mask (40) limits the distribution of said melt droplets (110).
    Type: Application
    Filed: January 11, 2010
    Publication date: December 29, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Dietrich Bertram, Jochen Stollenwerk, Johannes Krijne, Holger Schwab, Edward W. A. Young, Jeroen H. A. M. Van Buul, Andres Gasser, Konrad Wissenbach, Christian Vedder, Norbert Pirch
  • Patent number: 8056500
    Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 15, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ming-Kuei (Michael) Tseng, Norman Tam, Yoshitaka Yokota, Agus Tjandra, Robert Navasca, Mehran Behdjat, Sundar Ramamurthy, Kedarnath Sangam, Alexander N. Lerner
  • Patent number: 8053364
    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: November 8, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Wayne French, Pragati Kumar, Prashant Phatak, Tony Chiang
  • Patent number: 8048800
    Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: November 1, 2011
    Assignee: Dongguk University Industry—Academic Corporation Foundation
    Inventors: Jin-Koo Rhee, Seong-Dae Lee, Mi-Ra Kim, Dae-Hong Min, Wan-Joo Kim
  • Patent number: 8048805
    Abstract: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: November 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Lana Hiului Chan, Panya Wongsenakhum, Joshua Collins
  • Patent number: 7989798
    Abstract: A patterned array of metallic nanostructures and fabrication thereof is described. A device comprises a patterned array of metallic columns vertically extending from a substrate. Each metallic column is formed by metallically coating one of an array of non-metallic nanowires catalytically grown from the substrate upon a predetermined lateral pattern of seed points placed thereon according to a nanoimprinting process. An apparatus for fabricating a patterned array of metallic nanostructures is also described.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: August 2, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Philip J Kuekes, M. Saif Islam, Shih-Yuan Wang, Alexandre M. Bratkovski
  • Patent number: 7972960
    Abstract: A method for manufacturing a thin film includes: applying a liquid to a surface of a processing target member having at least one of a trench and a concave portion. The liquid includes a solvent and at least one of fine particles of a metal, fine particles of a semiconductor, fine particles containing a metal oxide, and fine particles containing a semiconductor oxide. A first heat treatment is included for volatilizing the solvent of the liquid applied to the surface of the processing target member. The fine particles are remained on the surface of the processing target member. A second heat treatment is also included for heating the fine particles by using microwave irradiation. At least one of the trench and the concave portion is filled with the thin film containing the fine particles or a component of the fine particles.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Yoshitaka Tsunashima
  • Patent number: 7956292
    Abstract: A printed circuit board manufacturing method includes: a hole-forming step of forming a through hole in a substrate that will become an element of a printed circuit board after manufacturing; and a jig insertion step of inserting a jig in the through hole formed in the hole-forming step such that the jig adheres to a portion of an inner wall of the through hole, the inner wall having a portion connecting to the outside of the through hole. The method further includes a conductive-film forming step of forming a conductive film only on the portion of the inner wall of the through hole connecting to the outside of the through hole, after the jig is inserted into the through hole in the jig insertion step.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Limited
    Inventor: Mitsuhiko Sugane
  • Patent number: 7955972
    Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: June 7, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
  • Patent number: 7880292
    Abstract: A semiconductor device that allows an image sensor (in an upper area of a SiP semiconductor device) to exchange signals with a device in a lower area of a SiP semiconductor device. A semiconductor device includes at least one of: A semiconductor substrate having a photodiode area and a transistor area. A PMD (Pre Metal Dielectric) layer formed on and/or over the semiconductor substrate. At least one metal layers formed on and/or over the PMD layer. A first penetrating electrode penetrating the PMD layer and the at least one metal layers. A second penetrating electrode penetrating the semiconductor substrate and connected to the first penetrating electrode.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jae-Won Han
  • Patent number: 7867904
    Abstract: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: January 11, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Tony P Chiang, Richard R Endo, James Tsung
  • Patent number: 7855147
    Abstract: Copper seed layers are formed on diffusion barrier layers (e.g., on Ta, and TaNx layers) without significant agglomeration of copper, with the use of an engineered barrier layer/seed layer interface. The engineered interface includes an adhesion layer, in which copper atoms are physically trapped and are prevented from migrating and agglomerating. The adhesion layer can include between about 20-80% atomic of copper. The copper atoms of the adhesion layer are exposed during deposition of a copper seed layer and serve as the nucleation sites for the deposited copper. Thin, continuous, and conformal seed layers can be deposited on top of the adhesion layer. The trapping of copper within the adhesion layer is achieved by intermixing diffusion barrier and seed layer materials using PVD and/or ALD.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: December 21, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Alexander Dulkin, Asit Rairkar, Frank Greer, Anshu A. Pradhan, Robert Rozbicki
  • Patent number: 7833899
    Abstract: A multi-layer thick metallization structure for a microelectronic device includes a first barrier layer (111), a first metal layer (112) over the first barrier layer, a first passivation layer (113) over the first metal layer, a via structure (114) extending through the first passivation layer, a second barrier layer (115) over the first passivation layer and in the via structure, a second metal layer (116) over the second barrier layer, and a second passivation layer (117) over the second metal layer and the first passivation layer.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Publication number: 20100273305
    Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 28, 2010
    Inventor: Rita J. Klein
  • Patent number: 7816254
    Abstract: A film-forming method for forming a metal film on a substrate by a sputtering process includes the steps of depressurizing a processing space, in which deposition of the metal film is caused by the sputtering process, applying a DC bias voltage between the substrate and a target disposed in the processing space so as to face the substrate, and igniting plasma by introducing secondary electrons to the processing space from a secondary electron source.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: October 19, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tatsuo Muraoka, Kazunori Kobayashi
  • Patent number: 7799602
    Abstract: A semiconductor device is made by forming a build-up interconnect structure over a substrate. A semiconductor die is mounted to the build-up interconnect structure. The semiconductor die is electrically connected to the build-up interconnect structure. A ground pad is formed on the build-up interconnect structure. An encapsulant is formed over the semiconductor die and build-up interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the build-up interconnect structure to isolate the semiconductor die from inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. The substrate is removed. A backside interconnect structure is formed over the build-up interconnect structure, opposite the semiconductor die.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: September 21, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Rui Huang, Yaojian Lin
  • Patent number: 7795144
    Abstract: A method for forming an electrode structure in a light emitting device is disclosed. The method includes the steps of: forming a mask material layer having an opening; depositing a first material layer on the mask material layer and on a portion of a compound semiconductor layer exposed through the bottom of the opening by a physical vapor deposition method reducing the particle density so that the mean free path for collision is long; depositing a second material layer on the first material layer on the mask material layer, on the first material layer deposited on the bottom of the opening, and on a portion of the compound semiconductor layer exposed through the bottom of the opening by a vapor deposition method other than the physical vapor deposition method; and removing the mask material layer and the first and second material layers deposited on the mask material layer.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: September 14, 2010
    Assignee: Sony Corporation
    Inventor: Naoki Hirao
  • Patent number: 7767574
    Abstract: The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 3, 2010
    Assignees: Kabushiki Kaisha Mikuni Kogyo, National Institute of Advanced Industrial Science and Technology
    Inventors: Yoshihiro Gomi, Masahiro Aoyagi, Hiroshi Nakagawa, Katsuya Kikuchi, Yoshikuni Okada, Hirotaka Oosato
  • Patent number: 7763535
    Abstract: The present invention relates to a method for manufacturing a backside contact of a semiconductor component, in particular, of a solar cell, comprising a metallic layer on the backside of a substrate in a vacuum treatment chamber, and the use of a vacuum treatment system for performing said method. Through this method and its use, in particular silicon based solar cells, can be provided with a back contact in a simple manner in a continuous process sequence, wherein the process sequence can be provided particularly efficient and economical, since no handling systems for rotating the substrate are required, and in particular silk screening steps can be dispensed with.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: July 27, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Roland Trassl, Jian Liu, Stephan Wieder, Jürgen Henrich, Gerhard Rist
  • Patent number: 7745332
    Abstract: Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: June 29, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Roey Shaviv, Alexander Dulkin, Neil Mackie, Daniel Juliano, Robert Rozbicki
  • Patent number: 7709383
    Abstract: A film forming method comprising forming a liquid coating film on a substrate by supplying a liquid containing a coating type thin film forming substance and a solvent onto the substrate, substantially converging a variation in film thickness of the coating film, making the coating film stand by in an atmosphere including moisture under a predetermined condition after the substantial-convergence, the predetermined condition being such that a product of a time for which the coating film is exposed to the atmosphere and a water content per unit volume in an atmosphere in the vicinity of a surface of the coating film is made to be greater than or equal to a predetermined value, and forming a solid thin film on the substrate after the stand-by, the thin film being formed by carrying out an elimination of the solvent in the coating film and heat treatment for generating an irreversible reaction to the coating type thin film forming substance in the coating film.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 4, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Tomoyuki Takeishi, Shinichi Ito
  • Patent number: 7674694
    Abstract: A process for realizing TFT devices on a substrate comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: March 9, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Leonardi, Salvatore Coffa, Claudia Caligiore, Guglielmo Fortunato, Luigi Mariucci, Massimo Cuscuna
  • Patent number: 7659204
    Abstract: A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Xianmin Tang, Hua Chung, Rongjun Wang, Praburam Gopalraja, Jick M. Yu, Jenn Yue Wang
  • Patent number: 7618893
    Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical valor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: November 17, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim