Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/685)
  • Patent number: 10002936
    Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: June 19, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Suvi Haukka, Michael Givens, Eric Shero, Jerry Winkler, Petri Räisänen, Timo Asikainen, Chiyu Zhu, Jaakko Anttila
  • Patent number: 9966268
    Abstract: Provided are a method of manufacturing a semiconductor device capable of forming a high-quality film having low roughness and resistivity and a substrate processing apparatus and program. The method includes (a) forming an amorphous metal film on a substrate while maintaining the substrate by performing steps (a-1) and (a-2) in a time-divisional manner wherein the step (a-1) includes supplying in the time-divisional manner a metal-containing gas and a first reducing gas to the substrate a predetermined number of times to form a first amorphous metal film on the substrate, and the step (a-2) includes simultaneously supplying the metal-containing gas and a second reducing gas to the substrate having the first amorphous metal film formed thereon to form a second amorphous metal film on the first amorphous metal film; and (b) heating the substrate having the amorphous metal film formed thereon to.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 8, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Arito Ogawa, Atsuro Seino
  • Patent number: 9685373
    Abstract: A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 20, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Meng-Tsung Ko, Yung-Tai Hung, Chin-Ta Su
  • Patent number: 9252102
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 2, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Bing-Lung Yu, Chin-Tsan Yeh, Yung-Tai Hung, Chin-Ta Su
  • Patent number: 9236294
    Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Po-Cheng Shih, Chih-Hung Sun, Kuang-Yuan Hsu, Joung-Wei Liou, Tze-Liang Lee
  • Patent number: 9224692
    Abstract: A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Douglas M. Reber
  • Patent number: 9219009
    Abstract: A method of fabricating an integrated circuit (IC) is disclosed. The method includes providing a substrate having a conductive feature. A dielectric layer is formed over the substrate, having an opening to expose the conductive feature. A tungsten (W) capping layer is formed over the conductive feature in the opening without using fluorine-containing gases. A bulk W layer is formed over the W capping layer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lai, Chun-I Tsai, Wei-Jung Lin
  • Patent number: 9218986
    Abstract: A method includes forming at least one trench in a dielectric layer using a hard mask. An edge cover layer is formed over the hard mask. The at least one trench is filled with a metal layer.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Huang-Yi Huang, Chih-Chien Chi, Ching-Hua Hsieh
  • Patent number: 9174853
    Abstract: A continuous or semi-continuous process for producing a high purity germane includes (a) preparing a reaction mixture containing hydrogen and crude germane and (b) separating the hydrogen from the crude germane by a pressure swing adsorption process. The pressure swing adsorption process results in a hydrogen-rich product stream and a germane-rich product stream. The method further includes (c) purifying the germane-rich product stream by continuous distillation thereof to remove impurities therefrom and to produce a high purity germane containing less than 0.1 volume percent of impurities.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: November 3, 2015
    Assignee: Gelest Technologies, Inc.
    Inventors: Barry C. Arkles, George A. Timberlake, Jr.
  • Patent number: 9151781
    Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 6, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Richard P. Volant, Ping-Chuan Wang
  • Patent number: 9145612
    Abstract: Provided are methods of depositing films comprising alloys of aluminum, which may be suitable as N-metal films. Certain methods comprise exposing a substrate surface to a metal halide precursor comprising a metal halide selected from TiCl4, TaCl5 and HfCl4 to provide a metal halide at the substrate surface; purging metal halide; exposing the substrate surface to an alkyl aluminum precursor comprising one or more of dimethyaluminum hydride, diethylhydridoaluminum, methyldihydroaluminum, and an alkyl aluminum hydrides of the formula [(CxHy)3-aAlHa]n, wherein x has a value of 1 to 3, y has a value of 2x+2, a has a value of 1 to 2, and n has a value of 1 to 4; and exposing the substrate surface to an alane-containing precursor comprising one or more of dimethylethylamine alane, methylpyrrolidinealane, di(methylpyrolidine)alane, and trimethyl amine alane borane. Other methods comprise exposing a substrate surface to a metal precursor and trimethyl amine alane borane.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 29, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Xinliang Lu, Shih Chung Chen, Wei Tang, Jing Zhou, Seshadri Ganguli, David Thompson, Jeffrey W. Anthis, Atif Noori, Faruk Gungor, Dien-Yeh Wu, Mei Chang, Xinyu Fu, Yu Lei
  • Patent number: 9070749
    Abstract: A method of forming a fluorine-free tungsten diffusion barrier layer having a reduced resistivity, and a semiconductor device, and method for forming such semiconductor device, using the fluorine-free tungsten diffusion barrier layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 30, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dong-Kyun Kang
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Patent number: 9034760
    Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Roey Shaviv, Raashina Humayun, Deqi Wang
  • Patent number: 9034768
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and depositing a tungsten-containing layer on the substrate surface to partially fill one or more high aspect ratio features. The method continues with selective removal of a portion of the deposited layer such that more material is removed near the feature opening than inside the feature. In certain embodiments, removal may be performed at mass-transport limited conditions with less etchant available inside the feature than near its opening. Etchant species are activated before being introduced into the processing chamber and/or while inside the chamber. In specific embodiments, recombination of the activated species is substantially limited and/or controlled during removal, e.g., operation is performed at less than about 250° C. and/or less than about 5 Torr.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
  • Patent number: 9029253
    Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Patent number: 8975142
    Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Abhijeet Paul, Abner Bello, Vimal K. Kamineni, Derya Deniz
  • Patent number: 8975180
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Publication number: 20150031204
    Abstract: A method of depositing a film is provided. In the method, one operation of a unit of film deposition process is performed by carrying a substrate into a processing chamber, by depositing a nitride film on the substrate, and by carrying the substrate out of the processing chamber after finishing depositing the nitride film on the substrate. The one operation is repeated a predetermined plurality of number of times continuously to deposit the nitride film on a plurality of substrates continuously. After that, an inside of the processing chamber is oxidized by supplying an oxidation gas into the processing chamber.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 29, 2015
    Inventors: Hiroko SASAKI, Yu WAMURA, Masato KOAKUTSU
  • Publication number: 20150004805
    Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Thomas R. Omstead, Cole S. Franklin
  • Publication number: 20140353774
    Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 4, 2014
    Inventors: Cerina Zhang, Nim Tea
  • Patent number: 8900999
    Abstract: A method of filling a feature in a substrate with tungsten without forming a seam is presented. The tungsten is deposited by a thermal chemical vapor deposition (CVD) process using hydrogen (H2) and tungsten hexafluoride (WF6) precursor gases. The H2 to WF6 flow rate ratio is greater than 40 to 1, such as from 40 to 1 to 100 to 1. The substrate temperature during deposition is less than 300 degrees Celsius (° C.) and the processing pressure during deposition is greater than 300 Torr.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kai Wu, Sang-Hyeob Lee, Joshua Collins, Kiejin Park
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8895443
    Abstract: Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Xinliang Lu, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Mei Chang
  • Patent number: 8895456
    Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Tachibana, Hiroaki Ikegawa, Yu Wamura, Muneyuki Otani, Jun Ogawa, Kosuke Takahashi
  • Patent number: 8888916
    Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Ming-Kuei (Michael) Tseng, Norman L. Tam, Yoshitaka Yokota, Agus S. Tjandra, Robert Navasca, Mehran Behdjat, Sundar Ramamurthy, Kedarnath Sangam, Alexander N. Lerner
  • Patent number: 8858763
    Abstract: Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 14, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Erich R. Klawuhn, Robert Rozbicki, Girish A. Dixit
  • Patent number: 8853046
    Abstract: A single TiON film is used to form a ReRAM device by varying the oxygen and nitrogen content throughout the device to form the electrodes and switching layer. A ReRAM device that can be formed in a single deposition chamber is also disclosed. The ReRAM device can be formed by forming a first titanium nitride layer, forming a titanium oxynitride-titanium oxide-titanium oxynitride layer, and then forming a second titanium nitride.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nan Lu, Chien-Lan Hsueh
  • Patent number: 8853080
    Abstract: Methods of producing low resistivity tungsten bulk layers having low roughness and associated apparatus are provided. According to various embodiments, the methods involve CVD deposition of tungsten at high pressures and/or high temperatures. In some embodiments, the CVD deposition occurs in the presence of alternating nitrogen gas pulses, such that alternating portions of the film are deposited by CVD in the absence of nitrogen and in the presence of nitrogen.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: October 7, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Yan Guan, Abhishek Manohar, Deqi Wang, Feng Chen, Raashina Humayun
  • Patent number: 8846531
    Abstract: To provide a method of manufacturing a semiconductor device that can be in contact with both of an n-type SiC region and a p-type SiC region and can suppress increase in contact resistance due to oxidation, a method of manufacturing a semiconductor device includes the steps of preparing a SiC layer, and forming an ohmic electrode on a main surface of the SiC layer. The step of forming the ohmic electrode includes the steps of forming a conductor layer which will become the ohmic electrode on the main surface of the SiC layer, and performing heat treatment such that the conductor layer becomes the ohmic electrode. After the step of performing the heat treatment, a temperature of the ohmic electrode when a surface of the ohmic electrode is exposed to an atmosphere containing oxygen is set to 100° C. or lower.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideto Tamaso, Keiji Wada
  • Publication number: 20140264887
    Abstract: Interconnects for semiconductors formed of materials that exhibit crystallographic anisotropy of the resistivity size effect such that line resistivity in one crystallographic orientation becomes lower than the resistivity in the other directions and methods of fabrication and use thereof are described. A wire having a dimension that results in an increase in the electrical resistivity of the wire can be formed of a material with a conductive anisotropy due to crystallographic orientation relative to the direction of current flow that minimizes the increase in the electrical resistivity as compared to the other orientations at that dimension.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: KATAYUN BARMAK VAZIRI, KEVIN COFFEY, DOOHO CHOI
  • Patent number: 8835317
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
  • Patent number: 8835310
    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik, Xuena Zhang
  • Patent number: 8828869
    Abstract: One illustrative method disclosed herein includes forming a seed layer above a structure, forming a nucleation layer on the seed layer, forming a plurality of spaced-apart, vertically oriented alloy structures that are comprised of materials from the seed layer and the nucleation layer, forming a sacrificial material layer above the nucleation layer and around the alloy structures, performing an etching process to remove the alloy structures and portions of the seed layer so as to thereby define a plurality of openings, forming an initial masking structure in each of the openings, performing an etching process to remove the sacrificial material layer and the nucleation layer so as to thereby expose the structure and define a masking layer comprised of the initial masking structures, and performing at least one process operation on the structure through the masking layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Manfred Heinrich Moert
  • Patent number: 8822350
    Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Ryuji Yamamoto
  • Patent number: 8802552
    Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Patent number: 8802578
    Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 12, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zuozhen Fu, Huaxiang Yin, Jiang Yan
  • Patent number: 8786031
    Abstract: The present invention provides a metal nitride film that realizes an intended effective work function (for example, a high effective work function) and has EOT exhibiting no change or a reduced change, a semiconductor device using the metal nitride film, and a manufacturing method of the semiconductor device. The metal nitride film according to an embodiment of the present invention contains Ti, Al and N, wherein the metal nitride film has such molar fractions of Ti, Al and N as (N/(Ti+Al+N)) of 0.53 or more, (Ti/(Ti+Al+N)) of 0.32 or less, and (Al/(Ti+Al+N)) of 0.15 or less.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 22, 2014
    Assignee: Canon Anelva Corporation
    Inventors: Takashi Nakagawa, Naomu Kitano
  • Publication number: 20140199839
    Abstract: A film-forming method includes forming a tungsten film or a tungsten oxide film on an object to be processed, heating the object on which the tungsten film or the tungsten oxide film is formed, forming a seed layer on the tungsten film or the tungsten oxide film by supplying an aminosilane-based gas to a surface of the tungsten film or the tungsten oxide film, and forming a silicon oxide film on the seed layer by simultaneously supplying a silicon material gas including silicon and a gas including an oxidizing agent for oxidizing silicon.
    Type: Application
    Filed: February 26, 2014
    Publication date: July 17, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jun SATO, Pao-Hwa Chou
  • Patent number: 8778800
    Abstract: This invention provides a micro-supercapacitor with high energy density and high power density. In some variations, carbon nanostructures, such as carbon nanotubes, coated with a metal oxide, such as ruthenium oxide, are grown in a supercapacitor cavity that contains no separator. A lid is bonded to the cavity using a bonding process to form a hermetic seal. These micro-supercapacitors may be fabricated from silicon-on-insulator wafers according to the disclosed methods. An exemplary micro-supercapacitor is cubic with a length of about 50-100 ?m. The absence of a separator translates to higher energy storage volume and less wasted space within the supercapacitor cell. The energy density of the micro-supercapacitor may exceed 150 J/cm3 and the peak output power density may be in the range of about 2-20 W/cm3, in various embodiments.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 15, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: David T. Chang, Pamela R. Patterson, Ping Liu
  • Patent number: 8778797
    Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Juwen Gao, Rajkumar Jakkaraju, Michal Danek, Wei Lei
  • Patent number: 8772939
    Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8748313
    Abstract: A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: June 10, 2014
    Assignees: Semiconductor Manufaturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hsin Chin Chen
  • Patent number: 8716132
    Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno
  • Patent number: 8709943
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 29, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Patent number: 8698313
    Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Shosuke Fujii, Yuichiro Mitani, Naoki Yasuda
  • Patent number: 8679978
    Abstract: A method for forming a film includes the steps of: placing an object to be processed into a processing container; and generating M(BH4)4 gas by feeding H2 gas as carrier gas into a raw material container in which solid M(BH4)4 (where M is Zr or Hf) is accommodated to introduce a mixture gas of H2 gas and M(BH4)4 gas having a volume ratio of flow rates (H2/M(BH4)4) of 2 or more into the processing container, and deposit a MBx film (where M is Zr or Hf and x is 1.8 to 2.5) on the object using a thermal CVD.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Takayuki Komiya
  • Patent number: 8673769
    Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Fritz Redeker, Yezdi Dordi, Hyungsuk Alexander Yoon, Shijian Li