Abstract: A method for manufacturing a semiconductor power device may includes: performing a grinding process on a back side of a wafer, performing a first plasma process and a rapid thermal process sequentially after performing the grinding process, performing a second plasma process after performing the rapid thermal process, and performing a metal thin film process after performing the second plasma process. The method for manufacturing a semiconductor device may be capable of preventing a peeling effect from occurring on a wafer surface by removing hydrogen from the wafer surface by controlling surface roughness to a desired level by treating the wafer surface using hydrogen plasma and a rapid thermal process (RTP) after subjecting a backside of the wafer to a grinding process.

Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.

Abstract: An object of the invention is to provide a semiconductor device which includes a barrier metal having high adhesiveness and diffusion barrier properties and a method of manufacturing the semiconductor device. The invention provides a semiconductor device manufacturing method including forming a first layer made of a material containing silicon on a base substance; forming a second layer containing metal and nitrogen on the first layer; and exposing the second layer to active species obtained from plasma in an atmosphere including reducing gas.

Abstract: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Abstract: A diffusion barrier film includes a layer of compositionally graded titanium nitride, having a nitrogen-rich portion and a nitrogen-poor portion. The nitrogen-rich portion has a composition of at least about 40% (atomic) N, and resides closer to the dielectric than the nitrogen-poor portion. The nitrogen-poor portion has a composition of less than about 30% (atomic) N (e.g., between about 5-30% N) and resides in contact with the metal, e.g., copper. The diffusion barrier film can also include a layer of titanium residing between the layer of dielectric and the layer of compositionally graded titanium nitride. The layer of titanium is often partially or completely converted to titanium oxide upon contact with a dielectric layer. The barrier film having a compositionally graded titanium nitride layer provides excellent diffusion barrier properties, exhibits good adhesion to copper, and reduces uncontrolled diffusion of titanium into interconnects.

Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.

Abstract: Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating layer pattern including silicon and a metal material is coated on the nickel-coated layer. After that, a heat treatment is performed at about 200 to about 350° C. to obtain the nickel-silicide layer. Since the thin film transistor substrate of the LCD device is manufactured by applying the nickel-silicide wiring, a device having low resistivity and good ohmic contact property can be obtained.

Abstract: The invention relates to a method and device for depositing at least one layer, particularly a semiconductor layer, onto at least one substrate, which is situated inside a process chamber of a reactor while being supported by a substrate holder. The layer is comprised of at least two material components provided in a fixed stoichiometric ratio, which are each introduced into the reactor in the form of a first and a second reaction gas, and a portion of the decomposition products form the layer, whereby the supply of the first reaction gas, which has a low thermal activation energy, determines the growth rate of the layer, and the second reaction gas, which has a high thermal activation energy, is supplied in excess and is preconditioned, in particular, by an independent supply of energy. The first reaction gas flows in a direction toward the substrate holder through a multitude of openings, which are distributed over a surface of a gas inlet element, said surface being located opposite the substrate holder.

Abstract: A method for fabricating a semiconductor device includes forming a dielectric film on a semiconductor substrate; forming an opening in the dielectric film; forming a refractory metal film in the opening; performing a nitriding process to the refractory metal film; removing a nitride of the refractory metal film formed on a side wall of the opening; and depositing tungsten (W) in the opening from which the nitride is removed.

Abstract: Disclosed is an apparatus and a method for reducing flash in an injection mold (532 or 542,543) which molds a molded article between a first mold surface and a second mold surface. The apparatus includes an active material actuator (530 or 533a and 533b or 561a and 561b) configured to, in response to application or removal of an electrical actuation signal thereto, change dimension and urge the first mold surface relative to the second mold surface to reduce flash therebetween. The apparatus also includes a transmission structure (533) configured to provide in use, the electrical actuation signal to said active material actuator (530 or 533a and 533b or 561a and 561b) includes a set of active material actuators stacked one against the other to provide a varying sealing force to urge the first mold surface relative to the second mold surface.

Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.

Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.

Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.

Abstract: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In some cases, the cycle may also include contact with a dopant precursor such as phosphine or arsine.

Abstract: In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating a liquid tantalum precursor containing tertiaryamylimido-tris(dimethylamido) tantalum (TAIMATA) to a temperature of at least 30° C. to form a tantalum precursor gas and exposing the substrate to a continuous flow of a carrier gas during an atomic layer deposition process. The method further provides exposing the substrate to the tantalum precursor gas by pulsing the tantalum precursor gas into the carrier gas and adsorbing the tantalum precursor gas on the substrate to form a tantalum precursor layer thereon. Subsequently, the tantalum precursor layer is exposed to at least one secondary element-containing gas by pulsing the secondary element-containing gas into the carrier gas while forming a tantalum barrier layer on the substrate.

Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.

Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.

Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Abstract: A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.

Abstract: A radiation-emitting semiconductor chip having an absorbent brightness setting layer between a connection region and a current injection region and/or, as seen from the connection region, outside the current injection region on a front-side radiation coupling-out area of the semiconductor layer sequence. The brightness setting layer absorbs in a targeted manner part of the radiation generated in the semiconductor layer sequence. In another embodiment, a partly insulating brightness setting layer is arranged between the connection region and the active layer.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

Abstract: A method of forming a metal layer on the conductive region of a semiconductor device includes concurrently supplying a mixture gas including a hydrogen gas and a metal chloride compound gas, and a purge gas into a chamber having a sealed space for a predetermined time, thereby forming a first metal layer on the semiconductor substrate, using a plasma enhanced chemical vapor deposition (PECVD) method. The hydrogen gas and metal chloride gases are thereafter alternately supplied for a predetermined time while the purge gas is continuously supplied into the chamber, thereby forming a second metal layer on the first metal layer, using a PECVD method. Deterioration of semiconductor devices due to high heat by a conventional CVD method can be prevented using a PECVD method as a low temperature process, thereby improving a production yield.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.

Abstract: Methods for removing metal-comprising materials from semiconductor materials are provided. In accordance with an exemplary embodiment, a method comprises providing a metal-comprising material overlying a semiconductor material and exposing the metal-comprising material to an aqueous non-chlorine-comprising acid solution having a pH of about less 7.

Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: A method of forming an electronic device can include forming a metallic layer over a side of a workpiece including a substrate, a differential etch layer, and a semiconductor layer. The differential etch layer may lie between the substrate and the semiconductor layer, and the semiconductor layer may lie along the side of the workpiece. The process can further include selectively removing at least a majority of the differential etch layer from between the substrate and the semiconductor layer, and separating the semiconductor layer and the metallic layer from the substrate. The selective removal can be performed using a wet etching, dry etching, or electrochemical technique. In a particular embodiment, the same plating bath may be used for plating the metallic layer and selectively removing the differential etch layer.

Abstract: In one embodiment, a method for forming a titanium nitride barrier material on a substrate is provided which includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition (MOCVD) process, and thereafter, densifying the titanium nitride layer by exposing the substrate to a plasma process. In one example, the MOCVD process and the densifying plasma process is repeated to form a barrier stack by depositing a second titanium nitride layer on the first titanium nitride layer. In another example, a third titanium nitride layer is deposited on the second titanium nitride layer. Subsequently, the method provides depositing a conductive material on the substrate and exposing the substrate to a annealing process. In one example, each titanium nitride layer may have a thickness of about 15 ? and the titanium nitride barrier stack may have a copper diffusion potential of less than about 5×1010 atoms/cm2.

Abstract: A method of using a film formation apparatus for a semiconductor process includes processing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is arranged to supply the cleaning gas into the reaction chamber, and set an interior of the reaction chamber at a first temperature and a first pressure. The by-product film mainly contains a high-dielectric-constant material. The cleaning gas contains chlorine without containing fluorine. The first temperature and the first pressure are set to activate chlorine in the cleaning gas.

Abstract: The present invention relates to a method for fabricating thin film transistor, more particularly, to a method for fabricating thin film transistor which not only manufactures a polycrystalline silicon layer having large grain size and containing a trace of residual metal catalyst by heat treating thereby crystallizing the metal catalyst layer after forming an amorphous silicon layer on a substrate, forming a capping layer formed of nitride film having 1.78 to 1.90 of the refraction index when crystallizing the amorphous silicon layer and forming a metal catalyst layer on the capping layer, but also controls characteristics of the polycrystalline silicon layer by controlling the refraction index of the capping layer.

Abstract: Embodiments as described herein provide a method for depositing barrier layers and tungsten materials on substrates. In one embodiment, a method for depositing materials is provided which includes forming a barrier layer on a substrate, wherein the barrier layer contains a cobalt silicide layer and a metallic cobalt layer, exposing the barrier layer to a soak gas containing a reducing gas during a soak process, and forming a tungsten material over the barrier layer. In one example, the barrier layer may be formed by depositing a cobalt-containing material on a dielectric surface of the substrate and annealing the substrate to form the cobalt silicide layer from a lower portion of the cobalt-containing material and the metallic cobalt layer from an upper portion of the cobalt-containing material.

Abstract: A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

Abstract: A package-base structure of a luminescent diode and its fabricating process. The package-base structure includes a substrate having thereon a holding space; an insulating layer extending from a bottom surface of the holding space to the bottom of the substrate; an through hole defined in the insulating layer; and a conductive layer disposed over the insulating layer. The insulating layer decouples the current flow and heat flow to increase the lifetime of the package-base structure together with the luminescent diode. In the fabricating process, the insulating layer is formed by anodic etching to allow the insulating layer have a porous structure.

Abstract: Embodiments of the invention provide methods for depositing tungsten materials. In one embodiment, a method for forming a composite tungsten film is provided which includes positioning a substrate within a process chamber, forming a tungsten nucleation layer on the substrate by subsequently exposing the substrate to a tungsten precursor and a reducing gas containing hydrogen during a cyclic deposition process, and forming a tungsten bulk layer during a plasma-enhanced chemical vapor deposition (PE-CVD) process. The PE-CVD process includes exposing the substrate to a deposition gas containing the tungsten precursor while depositing the tungsten bulk layer over the tungsten nucleation layer. In some example, the tungsten nucleation layer has a thickness of less than about 100 ?, such as about 15 ?. In other examples, a carrier gas containing hydrogen is constantly flowed into the process chamber during the cyclic deposition process.

Abstract: Methods for forming passivated stoichiometric metal nitride films are provided along with structures incorporating such films. The preferred methods include contacting a substrate with alternating and sequential pulses of a metal source chemical, one or more plasma-excited species of hydrogen and a nitrogen source chemical to form a stoichiometric metal nitride film, followed by exposure of the stoichiometric metal nitride film to a source chemical of a passivating species to form a passivation layer over the stoichiometric metal nitride film.

Abstract: Methods for forming titanium nitride layers are provided herein. In some embodiments, a method of forming a titanium nitride layer on a substrate may include providing a substrate into a processing chamber having a target comprising titanium disposed therein; supplying a nitrogen-containing gas into the processing chamber; sputtering a titanium source material from the target in the presence of a plasma formed from the nitrogen-containing gas to deposit a titanium nitride layer on the substrate; and upon depositing the titanium nitride layer to a desired thickness, forming a magnetic field that biases ions in the processing chamber away from the substrate.

Abstract: The method includes providing a patterned structure in a process chamber, where the patterned structure contains a micro-feature formed in a dielectric material and a contact layer at the bottom of the micro-feature, and depositing a metal carbonitride or metal carbide film on the patterned structure, including in the micro-feature and on the contact layer. The method further includes forming an oxidation-resistant diffusion barrier by increasing the nitrogen-content of the deposited metal carbonitride or metal carbide film, depositing a Ru film on the oxidation-resistant diffusion barrier, and forming bulk Cu metal in the micro-feature. A semiconductor contact structure is described.

Abstract: A method of forming a tungsten film on a surface of an object to be processed in a vessel capable of being vacuumized, includes the steps of forming a tungsten film by alternately repeating a reduction gas supplying process for supplying a reduction gas and a tungsten gas supplying process for supplying a tungsten-containing gas with an intervening purge process therebetween for supplying an inert gas while vacuumizing the vessel. A reduction gas supplying period of a reduction gas supplying process among the repeated reduction gas supplying processes is set to be longer than that of the remaining reduction gas supplying processes.

Abstract: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino) titanium (TEMAT) precursor vapor along with an inert carrier gas at a low process chamber pressure that provides high deposition rate of conformal TiN films with good step coverage in surface reaction limited regime. Other embodiments describe cyclical TiN deposition methods using TEMAT precursor vapor and a nitrogen precursor.

Abstract: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer.

Abstract: The present invention in one embodiment provides a method of forming an electrode that includes the steps of providing at least one metal stud in a layer of an interlevel dielectric material; forming a pillar of a first dielectric material atop the at least one metal stud; depositing an electrically conductive material atop the layer of the interlevel dielectric material and an exterior surface of the pillar, wherein a portion of the electrically conductive material is in electrical communication with the at least one metal stud; forming a layer of a second dielectric material atop the electrically conductive material and the substrate; and planarizing the layer of the second dielectric material to expose an upper surface of the electrically conductive material.

Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD processing chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.

Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.

Abstract: A semiconductor device in which the diffusion of copper from a wire is prevented and a method for fabricating such a semiconductor device. For example, a via groove and a wire groove are formed in a multilayer structure including a UDC diffusion barrier film, a porous silica film, a middle UDC stopper film, a porous silica film, a UDC diffusion barrier film, and the like, and the surfaces the UDC diffusion barrier film, the middle UDC stopper film, and the UDC diffusion barrier film that get exposed in the via groove and the wire groove are irradiated with hydrogen plasma, thereby making the surface of each exposed SiC film silicon-rich. After the plasma irradiation, a Ta film is formed in the via groove and the wire groove and copper is embedded in these grooves. By making the surface of each SiC film which is to touch the Ta film silicon-rich in advance, the crystal structure of the Ta film can be controlled so that copper cannot pierce through the Ta film. This prevents copper from diffusing from a wire.

Abstract: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.

Abstract: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.

Abstract: In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.