Copper Of Copper Alloy Conductor Patents (Class 438/687)
  • Patent number: 10777495
    Abstract: A printed circuit board comprises an epoxy-containing member, a first copper pattern disposed adjacent to the epoxy-containing member, and a first adhesion promoter layer interposed between the epoxy-containing member and the first copper pattern.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Soojae Park
  • Patent number: 10770306
    Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Bar, Francois Leverd, Delia Ristoiu
  • Patent number: 10700007
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 10665503
    Abstract: A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2020
    Assignee: APPLIED Materials, Inc.
    Inventor: Ismail T. Emesh
  • Patent number: 10636702
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Patent number: 10580740
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Patent number: 10494700
    Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Robert A. May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
  • Patent number: 10410864
    Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Thomas Jongwan Kwon, Rui Cheng, Abhijit Basu Mallick, Er-Xuan Ping, Jaesoo Ahn
  • Patent number: 10394098
    Abstract: A conductive pattern structure and its manufacturing method, an array substrate and a display device are provided. The conductive pattern structure includes a first metal layer and a second metal layer stacked in turn, wherein the second metal layer covers an upper surface and all side surfaces of the first metal layer, and the metal of the first metal layer has a stronger activity than the metal of the second metal layer. A common replacement reaction is adopted according to the order of the metal reducibility in the metal activity series table to cover an upper surface and all side surfaces of the first metal layer with the second metal layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 27, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jianguo Wang
  • Patent number: 10319826
    Abstract: A method is presented for tuning work functions of transistors. The method includes forming a high-k dielectric over a semiconductor substrate, and forming a work function stack over the high-k dielectric, the work function stack including a first layer having a nitrogen (N) scavenging element, a second layer having an oxygen (O) scavenging element, and a third layer being a conducting layer.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10312181
    Abstract: A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill a portion of the through substrate via and cover the horizontal field area. A thermal anneal step to reflow a portion of the first metal layer on the horizontal field area into the through substrate via. A second metal layer is deposited over the first metal layer to fill a remaining portion of the through substrate via. Another aspect of the invention is a device created by the method.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10242865
    Abstract: A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Haigh, Jr., Son V. Nguyen, Deepika Priyadarshini, Hosadurga Shobha
  • Patent number: 10236176
    Abstract: A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Haigh, Jr., Son V. Nguyen, Deepika Priyadarshini, Hosadurga Shobha
  • Patent number: 10224275
    Abstract: Semiconductor devices include a patterned dielectric layer overlaying a semiconductor substrate; a metal layer comprising copper disposed in the patterned dielectric layer; and a barrier layer formed at an interface between the dielectric layer and the metal layer, wherein the barrier layer is AlOxNy. The patterned dielectric may define a trench and via interconnect structure or first and second trenches for a capacitor structure. Also disclosed are processes for forming the semiconductor device, which includes subjecting the dielectric surfaces to a nitridization process to form a nitrogen enriched surface. Aluminum metal is then conformally deposited onto the nitrogen enriched surfaces to form AlOxNy at the aluminum metal/dielectric interface. The patterned substrate is then metalized with copper and annealed. Upon annealing, a copper aluminum alloy is formed at the copper metal/aluminum interface.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Wei Wang, Chih-Chao Yang
  • Patent number: 10170416
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Elbert Huang, Joe Lee, Christopher J. Penny
  • Patent number: 10115670
    Abstract: A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. The set of features have a first dimension. An adhesion promoting layer disposed over the patterned dielectric is deposited. A ruthenium layer disposed over the adhesion promoting layer is deposited. A cobalt layer is deposited over the ruthenium layer. A high temperature thermal anneal is performed which creates a ruthenium cobalt alloy layer to cover surfaces of the set of features. A metal layer is deposited disposed over the ruthenium cobalt alloy layer to form a set of metal conductor structures. In another aspect of the invention, a device is created using the method.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10109585
    Abstract: An integrated circuit device includes a substrate including a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A ruthenium cobalt alloy layer is disposed over the adhesion promoting layer. A metal layer is disposed over the ruthenium cobalt alloy layer filling the set of features.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10096769
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10062658
    Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 28, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
  • Patent number: 10032642
    Abstract: Disclosed is a substrate liquid processing apparatus that includes: a liquid processing unit that performs a liquid processing on a film formed on a surface of a substrate with an etching liquid; an etching liquid supply unit that supplies an etching liquid to the liquid processing unit; and a controller that controls the etching liquid supply unit. The controller is configured to perform a control such that an etching liquid in a state of having a relatively low etching rate for the film is supplied from the etching liquid supply unit to the liquid processing unit so that the substrate is etched in the liquid processing unit, and then, an etching liquid in a state of having a relatively high etching rate for the film is supplied from the etching liquid supply unit to the liquid processing unit so that the substrate is etched in the liquid processing unit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: July 24, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Hideaki Sato, Takashi Nagai, Hiromi Hara
  • Patent number: 9954097
    Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: April 24, 2018
    Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 9926639
    Abstract: Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and bottom surface of the opening; and depositing a conductive material on the layer to fill the opening. In some embodiments, one of ruthenium (Ru) or cobalt (Co) is deposited on the sidewall and bottom surface of the opening. The materials may be deposited by chemical vapor deposition (CVD) or by physical vapor deposition (PVD).
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 27, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hoon Kim, Wei Ti Lee, Sang Ho Yu, Seshadri Ganguli, Hyoung-Chan Ha, Sang Hyeob Lee
  • Patent number: 9673090
    Abstract: One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: June 6, 2017
    Inventor: Uri Cohen
  • Patent number: 9666545
    Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Wang, Yao-Hsiang Liang
  • Patent number: 9659859
    Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin
  • Patent number: 9607891
    Abstract: An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fu Yeh, Hsiang-Huan Lee
  • Patent number: 9595601
    Abstract: A method of fabricating a thin-film transistor substrate including a thin-film semiconductor includes: forming a metal film mainly comprising Cu above a substrate; forming a source electrode and a drain electrode by processing the metal film in a predetermined shape; irradiating the source electrode and the drain electrode with nitrogen plasma; exposing surfaces of a top and an end portion of the source electrode and the drain electrode with silane (SiH4) gas; and forming an insulating layer comprising an oxide on the source electrode and the drain electrode.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 14, 2017
    Assignee: JOLED, INC.
    Inventors: Yuichiro Miyamae, Kenichirou Nishida, Toru Saito
  • Patent number: 9476140
    Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 25, 2016
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chih Chen, King-Ning Tu, Taochi Liu
  • Patent number: 9425086
    Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.
    Type: Grant
    Filed: December 21, 2013
    Date of Patent: August 23, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Fang-Hao Hsu, Hsu-Sheng Yu, Kuo-Feng Lo, Hong-Ji Lee
  • Patent number: 9412658
    Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 9, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Oleg Gluschenkov, Siddarth A. Krishnan, Joyeeta Nag, Andrew H. Simon, Shishir Ray
  • Patent number: 9399822
    Abstract: The present inventive concepts provide a liquid composition for etching a metal containing copper. The liquid composition may include hydrogen peroxide in a range of about 0.1 wt % to about 10 wt % and a buffer solution in a range of about 0.1 wt % to about 10 wt %. The buffer solution may include citrate. The liquid composition may have a pH in a range of about 4.0 to about 7.0.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: July 26, 2016
    Assignees: Samsung Electronics Co., Ltd., Samyoung Pure Chemicals Co., Ltd., Mitsubishi Gas Chemical Company, Inc.
    Inventors: Dong-Min Kang, Hyungjun Jeon, Ingoo Kang, Jeong Kwon, Jung-ig Jeon, Jungsik Choi, Young Taek Hong, Akira Hosomi, Tomoko Suzuki
  • Patent number: 9390971
    Abstract: An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 12, 2016
    Assignee: President and Fellows of Harvard College
    Inventors: Roy Gerald Gordon, Harish B. Bhandari, Yeung Au, Youbo Lin
  • Patent number: 9373586
    Abstract: The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Patent number: 9362325
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 7, 2016
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Patent number: 9304143
    Abstract: An operating movement detection device, which detects a shaking movement performed on an electronic device in a first direction, includes an acquisition unit that acquires a first acceleration value in the first direction and a second acceleration value in a second direction different from the first direction, the first acceleration value and the second acceleration value being sensed by an acceleration sensor, a calculation unit that calculates a determination threshold based on the second acceleration value acquired in a first determination period, and a determination unit that determines whether or not the shaking movement has been performed based on the first acceleration value acquired in the first determination period and the calculated determination threshold.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: April 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yoku Takahashi, Katsumi Otsuka, Tomohiro Nakajima
  • Patent number: 9281240
    Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jeong Moon, Woo-Choel Noh, Woo-Jin Jang, Hun Kim, Hong-Jae Shin
  • Patent number: 9245798
    Abstract: A method for at least partially filling a feature on a workpiece includes obtaining a workpiece including a feature having a high aspect ratio in the range of about 10 to about 80, depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 26, 2016
    Assignee: APPLIED Matrials, Inc.
    Inventors: Ismail T. Emesh, Robert C. Linke
  • Patent number: 9245841
    Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
  • Patent number: 9245794
    Abstract: An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Takeshi Nogami
  • Patent number: 9224621
    Abstract: The invention relates to an encapsulation process for an electronic component (2). The component (2) is connected to an electrical contact track composed of a metal layer (101). The process according to the invention comprises the following steps: deposition of a titanium nitride layer (102) directly on at least part of the electrical contact track (101); and deposition of an aluminum oxide layer (4) by atomic layer deposition, such that the encapsulation layer (4) directly covers the titanium nitride layer (102). The process according to the invention enables electrical contact through the encapsulation layer (4). The invention also relates to an electronic device obtained using such a process.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: December 29, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Tony Maindron, Nicolas Troc
  • Patent number: 9212419
    Abstract: A copper alloy wiring film of a flat panel display of the present invention and a sputtering target for forming the same have a composition including Mg: 0.1 to 5 atom %; either one or both of Mn and Al: 0.1 to 11 atom % in total; and Cu and inevitable impurities as the balance, and if necessary, may be further including P: 0.001 to 0.1 atom %.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: December 15, 2015
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Kazunari Maki, Kenichi Yaguchi, Yosuke Nakasato, Haruhiko Asao
  • Patent number: 9209134
    Abstract: Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 8, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Mankoo Lee
  • Patent number: 9207545
    Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes an overlay mark formed on a substrate; and a plurality of dummy features formed nearby the overlay mark. The dummy features have dimensions below a minimum resolution of an alignment detection tool. A minimum distance separating the overlay mark from its closest dummy feature is correlated to a semiconductor fabrication technology generation under which the overlay mark is formed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Chieh Huang
  • Patent number: 9202749
    Abstract: Methods for achieving advanced patterning of an interconnect dielectric material layer are provided in which the dimension, i.e., width, of an opening that is formed into a metallic hard mask layer is shrunk prior to extending the opening into the interconnect dielectric material layer. The shrinking of the dimension of the opening that is formed into the metallic hard mask layer can be achieved in the present application by forming at least a metallic hard mask spacer portion on a sidewall surface of each patterned metallic hard mask layer. The aforementioned basic principle can be applied to forming a line opening, a via opening and/or a combined via and line opening within an interconnect dielectric material layer, wherein each of the openings (line, via and/or via and line) has a reduced dimension as compared to that obtainable utilizing conventional lithography.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: December 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, Chih-Chao Yang
  • Patent number: 9196605
    Abstract: An embodiment of the present application discloses a light-emitting structure, comprising a substrate, a first unit and a second unit separately form on the substrate; a trench formed between the first unit and the second unit, and having a bottom portion exposing the substrate, a less steep sidewall and a steeper sidewall steeper than the less steep sidewall; and an electrical connection connecting the first unit and the second unit and covering the first unit, the second unit and the less steep sidewall; wherein the sidewalls directly connect to the bottom portion, and the steeper sidewall is devoid of the electrical connection covering.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 24, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Fu Shen, Chao-Hsing Chen, Tsun-Kai Ko, Schang-Jing Hon, Sheng-Jie Hsu, De-Shan Kuo, Hsin-Ying Wang, Chiu-Lin Yao, Chien-Fu Huang, Hsin-Mao Liu, Chien-Kai Chung
  • Patent number: 9190321
    Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Daniel C. Edelstein, Juntao Li, Takeshi Nogami
  • Patent number: 9177857
    Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: November 3, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke Oshida, Toshiyuki Takewaki, Shinji Yokogawa
  • Patent number: 9147574
    Abstract: A method is provided for patterning a layered substrate that includes loading a substrate into a coater-developer processing system; coating the substrate with a photoresist material layer; patterning the photoresist material layer to form a photoresist pattern; transferring the substrate to a deposition processing system; and depositing a neutral layer over the photoresist pattern and exposed portions of the substrate. The neutral layer can deposited using a gas cluster ion beam (GCIB) process, or an atomic layer deposition (ALD) process, which has minimal topography. The method may further include lifting off a portion of the neutral layer deposited over the photoresist pattern to expose a neutral layer template for subsequent directed self-assembly (DSA) patterning; depositing a DSA material layer over the neutral layer template; baking the DSA material layer to form a DSA pattern; and developing the DSA material layer to expose the final DSA pattern for subsequent feature etching.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 29, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Mark H. Somervell, Benjamen M. Rathsack
  • Patent number: 9142509
    Abstract: A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Shau-Lin Shue, Hsiang-Huan Lee, Ching-Fu Yeh
  • Patent number: 9123728
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: September 1, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takahiro Kono, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada