Copper Of Copper Alloy Conductor Patents (Class 438/687)
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Patent number: 9390971Abstract: An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces.Type: GrantFiled: July 8, 2015Date of Patent: July 12, 2016Assignee: President and Fellows of Harvard CollegeInventors: Roy Gerald Gordon, Harish B. Bhandari, Yeung Au, Youbo Lin
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Patent number: 9373586Abstract: The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.Type: GrantFiled: March 18, 2014Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
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Patent number: 9362325Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.Type: GrantFiled: September 19, 2013Date of Patent: June 7, 2016Assignee: Sony CorporationInventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
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Patent number: 9304143Abstract: An operating movement detection device, which detects a shaking movement performed on an electronic device in a first direction, includes an acquisition unit that acquires a first acceleration value in the first direction and a second acceleration value in a second direction different from the first direction, the first acceleration value and the second acceleration value being sensed by an acceleration sensor, a calculation unit that calculates a determination threshold based on the second acceleration value acquired in a first determination period, and a determination unit that determines whether or not the shaking movement has been performed based on the first acceleration value acquired in the first determination period and the calculated determination threshold.Type: GrantFiled: April 11, 2013Date of Patent: April 5, 2016Assignee: FUJITSU LIMITEDInventors: Yoku Takahashi, Katsumi Otsuka, Tomohiro Nakajima
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Patent number: 9281240Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.Type: GrantFiled: March 2, 2015Date of Patent: March 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Jeong Moon, Woo-Choel Noh, Woo-Jin Jang, Hun Kim, Hong-Jae Shin
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Patent number: 9245794Abstract: An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.Type: GrantFiled: September 13, 2012Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Chih-Chao Yang, Daniel C. Edelstein, Takeshi Nogami
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Patent number: 9245841Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.Type: GrantFiled: July 19, 2012Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
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Patent number: 9245798Abstract: A method for at least partially filling a feature on a workpiece includes obtaining a workpiece including a feature having a high aspect ratio in the range of about 10 to about 80, depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.Type: GrantFiled: March 13, 2013Date of Patent: January 26, 2016Assignee: APPLIED Matrials, Inc.Inventors: Ismail T. Emesh, Robert C. Linke
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Patent number: 9224621Abstract: The invention relates to an encapsulation process for an electronic component (2). The component (2) is connected to an electrical contact track composed of a metal layer (101). The process according to the invention comprises the following steps: deposition of a titanium nitride layer (102) directly on at least part of the electrical contact track (101); and deposition of an aluminum oxide layer (4) by atomic layer deposition, such that the encapsulation layer (4) directly covers the titanium nitride layer (102). The process according to the invention enables electrical contact through the encapsulation layer (4). The invention also relates to an electronic device obtained using such a process.Type: GrantFiled: March 18, 2014Date of Patent: December 29, 2015Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Tony Maindron, Nicolas Troc
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Patent number: 9212419Abstract: A copper alloy wiring film of a flat panel display of the present invention and a sputtering target for forming the same have a composition including Mg: 0.1 to 5 atom %; either one or both of Mn and Al: 0.1 to 11 atom % in total; and Cu and inevitable impurities as the balance, and if necessary, may be further including P: 0.001 to 0.1 atom %.Type: GrantFiled: July 31, 2009Date of Patent: December 15, 2015Assignee: MITSUBISHI MATERIALS CORPORATIONInventors: Kazunari Maki, Kenichi Yaguchi, Yosuke Nakasato, Haruhiko Asao
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Patent number: 9209134Abstract: Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material.Type: GrantFiled: May 29, 2013Date of Patent: December 8, 2015Assignee: Intermolecular, Inc.Inventor: Mankoo Lee
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Patent number: 9207545Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes an overlay mark formed on a substrate; and a plurality of dummy features formed nearby the overlay mark. The dummy features have dimensions below a minimum resolution of an alignment detection tool. A minimum distance separating the overlay mark from its closest dummy feature is correlated to a semiconductor fabrication technology generation under which the overlay mark is formed.Type: GrantFiled: March 12, 2013Date of Patent: December 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wei-Chieh Huang
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Patent number: 9202749Abstract: Methods for achieving advanced patterning of an interconnect dielectric material layer are provided in which the dimension, i.e., width, of an opening that is formed into a metallic hard mask layer is shrunk prior to extending the opening into the interconnect dielectric material layer. The shrinking of the dimension of the opening that is formed into the metallic hard mask layer can be achieved in the present application by forming at least a metallic hard mask spacer portion on a sidewall surface of each patterned metallic hard mask layer. The aforementioned basic principle can be applied to forming a line opening, a via opening and/or a combined via and line opening within an interconnect dielectric material layer, wherein each of the openings (line, via and/or via and line) has a reduced dimension as compared to that obtainable utilizing conventional lithography.Type: GrantFiled: February 6, 2014Date of Patent: December 1, 2015Assignee: International Business Machines CorporationInventors: Shom Ponoth, Chih-Chao Yang
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Patent number: 9196605Abstract: An embodiment of the present application discloses a light-emitting structure, comprising a substrate, a first unit and a second unit separately form on the substrate; a trench formed between the first unit and the second unit, and having a bottom portion exposing the substrate, a less steep sidewall and a steeper sidewall steeper than the less steep sidewall; and an electrical connection connecting the first unit and the second unit and covering the first unit, the second unit and the less steep sidewall; wherein the sidewalls directly connect to the bottom portion, and the steeper sidewall is devoid of the electrical connection covering.Type: GrantFiled: September 13, 2011Date of Patent: November 24, 2015Assignee: EPISTAR CORPORATIONInventors: Chien-Fu Shen, Chao-Hsing Chen, Tsun-Kai Ko, Schang-Jing Hon, Sheng-Jie Hsu, De-Shan Kuo, Hsin-Ying Wang, Chiu-Lin Yao, Chien-Fu Huang, Hsin-Mao Liu, Chien-Kai Chung
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Patent number: 9190321Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.Type: GrantFiled: April 8, 2013Date of Patent: November 17, 2015Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Daniel C. Edelstein, Juntao Li, Takeshi Nogami
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Patent number: 9177857Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.Type: GrantFiled: January 8, 2009Date of Patent: November 3, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke Oshida, Toshiyuki Takewaki, Shinji Yokogawa
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Patent number: 9147574Abstract: A method is provided for patterning a layered substrate that includes loading a substrate into a coater-developer processing system; coating the substrate with a photoresist material layer; patterning the photoresist material layer to form a photoresist pattern; transferring the substrate to a deposition processing system; and depositing a neutral layer over the photoresist pattern and exposed portions of the substrate. The neutral layer can deposited using a gas cluster ion beam (GCIB) process, or an atomic layer deposition (ALD) process, which has minimal topography. The method may further include lifting off a portion of the neutral layer deposited over the photoresist pattern to expose a neutral layer template for subsequent directed self-assembly (DSA) patterning; depositing a DSA material layer over the neutral layer template; baking the DSA material layer to form a DSA pattern; and developing the DSA material layer to expose the final DSA pattern for subsequent feature etching.Type: GrantFiled: March 13, 2014Date of Patent: September 29, 2015Assignee: Tokyo Electron LimitedInventors: Mark H. Somervell, Benjamen M. Rathsack
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Patent number: 9142509Abstract: A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer.Type: GrantFiled: July 16, 2014Date of Patent: September 22, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Shau-Lin Shue, Hsiang-Huan Lee, Ching-Fu Yeh
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Patent number: 9123728Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.Type: GrantFiled: January 22, 2014Date of Patent: September 1, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Takahiro Kono, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada
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Patent number: 9103000Abstract: In one example embodiment, a sputter target structure for depositing semiconducting chalcogenide films is described. The sputter target includes a target body having a target body composition that comprises Cu1-x(Se1-y-zSyTez)x, wherein the value of x is greater than or equal to approximately 0.5, the value of y is between approximately 0 and approximately 1, the value of z is between approximately 0 and approximately 1, and the total amount of Se, S, and Te phases in the target body composition comprise less than 50 volume percent of the target body composition.Type: GrantFiled: November 23, 2010Date of Patent: August 11, 2015Assignee: ZETTA RESEARCH AND DEVELOPMENT LLC—AQT SERIESInventors: Mariana Munteanu, Brian Josef Bartholomeusz, Michael Bartholomeusz, Erol Girt
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Patent number: 9101067Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.Type: GrantFiled: December 20, 2013Date of Patent: August 4, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Tadahiro Ishizaka, Toshio Hasegawa
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Patent number: 9082702Abstract: Provided are devices and methods utilizing TiN and/or TaN films doped with Si, Al, Ga, Ge, In and/or Hf. Such films may be used as a high-k dielectric cap layer, PMOS work function layer, aluminum barrier layer, and/or fluorine barrier. These TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN or TaHfN films can be used where TiN and/or TaN films are traditionally used, or they may be used in conjunction with TiN and/or TaN.Type: GrantFiled: February 20, 2013Date of Patent: July 14, 2015Assignee: Applied Materials, Inc.Inventors: Yu Lei, Srinivas Gandikota, Xinyu Fu, Wei Tang, Atif Noori
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Patent number: 9076793Abstract: In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film.Type: GrantFiled: November 6, 2012Date of Patent: July 7, 2015Assignee: PS4 LUXCO S.A.R.L.Inventor: Katsuhiko Tanaka
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Patent number: 9070750Abstract: Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. Metal oxide surfaces are reduced to form a film integrated with a metal seed layer on a substrate by exposing the metal oxide surfaces to a reducing gas atmosphere comprising radicals of a reducing gas species. The radicals of the reducing gas species can form from exposing the reducing gas species to ultraviolet radiation and/or a plasma. The substrate is maintained at a temperature below a temperature that produces agglomeration of the metal seed layer during exposure to the reducing gas atmosphere, such as below 150° C. for copper. In some embodiments, the reducing gas species can include at least one of hydrogen, ammonia, carbon monoxide, diborane, sulfite compounds, carbon and/or hydrocarbons, phosphites, and hydrazine.Type: GrantFiled: March 6, 2013Date of Patent: June 30, 2015Assignee: Novellus Systems, Inc.Inventors: Tighe A. Spurlin, Darcy E. Lambert, Durgalakshmi Singhal, George Andrew Antonelli
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Patent number: 9064875Abstract: Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer.Type: GrantFiled: November 21, 2011Date of Patent: June 23, 2015Assignee: Infineon Technologies AGInventors: Jakob Kriz, Norbert Urbansky
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Patent number: 9054163Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.Type: GrantFiled: November 6, 2013Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming Han Lee
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Patent number: 9040348Abstract: A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.Type: GrantFiled: September 7, 2012Date of Patent: May 26, 2015Assignee: Altera CorporationInventors: Nagesh Vodrahalli, Jon M. Long
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Patent number: 9040346Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.Type: GrantFiled: May 3, 2012Date of Patent: May 26, 2015Assignee: Infineon Technologies AGInventors: Ivan Nikitin, Edward Fuergut
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Patent number: 9018092Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.Type: GrantFiled: September 27, 2012Date of Patent: April 28, 2015Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
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Patent number: 9006097Abstract: A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes forming a mask layer on the UBM layer, wherein the mask layer has an opening exposing a portion of the UBM layer. The method further includes forming a copper layer in the opening of the mask layer and removing a portion of the mask layer to form a space between the copper layer and the mask layer. The method further includes performing an electrolytic process to fill the space with a metal layer and removing the mask layer.Type: GrantFiled: June 26, 2013Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Chih-Wei Lin, Jacky Chang, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 9000535Abstract: A semiconductor device includes: a semiconductor substrate; a first transistor which is formed on the semiconductor substrate and includes a source/drain region and a gate electrode; an insulating film which covers the source/drain region and the gate electrode of the first transistor; and a first contact plug which is formed in the insulating film and is connected to the source/drain region or the gate electrode of the first transistor, wherein the first contact plug includes a first column section which extends in a thickness direction of the insulating film and is in contact with the source/drain region or the gate electrode of the first transistor, and a first flange section which juts out from an upper portion of the first column section in a direction parallel to a surface of the insulating film, and an upper surface of the first flange section is planarized.Type: GrantFiled: August 17, 2012Date of Patent: April 7, 2015Assignee: Fujitsu Semiconductor LimitedInventor: Masatoshi Fukuda
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Publication number: 20150091116Abstract: A stack of layers defines a filter and is formed by copper on hydrogenated silicon nitride supported by a carrier. The filter includes a layer of hydrogenated silicon nitride, a layer of silicon oxide on the layer of hydrogenated silicon nitride and a layer of copper on the layer of silicon oxide. The layer of hydrogenated silicon nitride may have, in a vicinity of its upper side, a ratio of a number of silicon atoms per cubic centimeter to a number of nitrogen atoms per cubic centimeter lower than 0.8 (or even lower than 0.6), with a number of silicon-hydrogen bonds smaller than or equal to 6×1021 bonds per cubic centimeter (or even smaller than 0.5×1021 bonds per cubic centimeter). The filter further includes an additional layer of copper between the layer of hydrogenated silicon nitride and the carrier.Type: ApplicationFiled: October 1, 2014Publication date: April 2, 2015Applicants: STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Patrick Gros D'aillon, Michel Marty
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Patent number: 8993440Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.Type: GrantFiled: July 23, 2013Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
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Patent number: 8993442Abstract: Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %.Type: GrantFiled: August 23, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia Cheng Chou, Kuang-Yuan Hsu
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Patent number: 8987133Abstract: A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask.Type: GrantFiled: January 15, 2013Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Son V. Nguyen, Tuan A. Vo, Christopher J. Waskiewicz
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Patent number: 8987134Abstract: Semiconductor devices and methods of making thereof are disclosed. The semiconductor device includes a substrate prepared with a first dielectric layer formed thereon. The dielectric layer includes at least first, second and third contact regions. A second dielectric layer is disposed over the first dielectric layer. The device also includes at least first, second and third via contacts disposed in the second dielectric layer. The via contacts are coupled to the respective underlying contact regions and the via contacts do not extend beyond the underlying contact regions.Type: GrantFiled: June 6, 2013Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Zhehui Wang, Kwee Liang Yeo, Hai Cong, Huang Liu, Wen Zhan Zhou
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Patent number: 8987910Abstract: The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly.Type: GrantFiled: December 16, 2011Date of Patent: March 24, 2015Assignee: Atotech Deutschland GmbHInventors: Mustafa Özkök, Gustavo Ramos, Arnd Kilian
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Patent number: 8980715Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.Type: GrantFiled: August 28, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 8981466Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.Type: GrantFiled: March 11, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 8980746Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming copper filled through silicon via features in a silicon wafer is provided. Through silicon vias are etched in the wafer. An insulation layer is formed within the through silicon vias. A barrier layer is formed within the through silicon vias. An oxide free silicon, germanium, or SiGe adhesion layer is deposited over the barrier layer. A seed layer is deposited over the adhesion layer then the wafers is annealed. The features are filled with copper or copper alloy. The stack is annealed.Type: GrantFiled: August 13, 2013Date of Patent: March 17, 2015Assignee: Lam Research CorporationInventor: Artur Kolics
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Patent number: 8975749Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.Type: GrantFiled: January 10, 2014Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
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Publication number: 20150056788Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
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Patent number: 8963325Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.Type: GrantFiled: January 11, 2013Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Baik-woo Lee, Young-hun Byun, Seong-woon Booh, Chang-mo Jeong
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Patent number: 8952543Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.Type: GrantFiled: December 18, 2012Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Byung-Lyul Park, Hyun-Soo Chung, Gil-Heyun Choi
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Patent number: 8946899Abstract: An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.Type: GrantFiled: July 24, 2012Date of Patent: February 3, 2015Assignee: Invensas CorporationInventor: Cyprian Emeka Uzoh
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Patent number: 8946059Abstract: A method of producing a semiconductor device is provided, the semiconductor device including a substrate, a semiconductor layer and at least one metallization layer adjacent to at least one element chosen from the substrate and the semiconductor layer, the method including forming at least one metallization layer which, adjacent to at least one element chosen from the substrate and the semiconductor layer, includes oxygen.Type: GrantFiled: October 21, 2009Date of Patent: February 3, 2015Assignee: Applied Materials, Inc.Inventors: Evelyn Scheer, Fabio Pieralisi, Marcus Bender
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Publication number: 20150014848Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.Type: ApplicationFiled: April 22, 2014Publication date: January 15, 2015Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Fu-Tang Huang
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Patent number: 8932911Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.Type: GrantFiled: February 27, 2013Date of Patent: January 13, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Torsten Huisinga, Carsten Peters, Andreas Ott, Axel Preusse
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Patent number: 8927416Abstract: A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.Type: GrantFiled: October 14, 2011Date of Patent: January 6, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Takeshi Harada, Junichi Shibata, Akira Ueki
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Patent number: 8928105Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).Type: GrantFiled: May 27, 2011Date of Patent: January 6, 2015Assignee: Flisom AGInventors: Roger Ziltener, Roland Kern, David Bremaud, Björn Keller