Abstract: The invention relates to a method for fabricating silicon and/or germanium nanowires on a substrate, comprising a step of bringing a precursor comprising silicon and/or a precursor comprising germanium into contact with a compound comprising copper oxide present on the said substrate, by means of which growth of nanowires takes place.

Abstract: Integrated circuit dies and methods of fabricating the dies are disclosed. An embodiment of a method includes providing a die having a redistribution layer fabricated thereon. The redistribution layer has a surface located thereon that is free of any seed layers. An under bump metal layer is fabricated directly to the surface.

Abstract: In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The non-uniform top surface includes a plurality of protrusions. The method further includes removing the plurality of protrusions by exposing the layer to a fluid that has gas bubbles and a liquid.

Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.

Abstract: An abrasive liquid for a metal comprising (1) an oxidizing agent for a metal, (2) a dissolving agent for an oxidized metal, (3) a first protecting film-forming agent such as an amino acid or an azole which adsorbs physically on the surface of the metal and/or forms a chemical bond, to thereby form a protecting film, (4) a second protecting film-forming agent such as polyacrylic acid, polyamido acid or a salt thereof which assists the first protecting film-forming agent in forming a protecting film and (5) water; and a method for polishing.

Abstract: In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.

Abstract: Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.

Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.

Abstract: Provided is a Cu electrical interconnection film forming method, wherein an adhesive layer (base film) having improved adhesiveness with a Cu electrical interconnection film is used, in a semiconductor device manufacturing process. After forming a barrier film on a substrate whereupon a hole or the like is formed, a PVD-Co film or a CVD-Co film or an ALD-Co film is formed on the barrier film. Then, after filling up or burying the hole or the like, which has the Co film formed on the surface, with a CVD-Cu film or a PVD-Cu film, heat treatment is performed at a temperature of 350° C. or below, and the Cu electrical interconnection film is formed.

Abstract: The present invention discloses a method and a device for preparing a compound semiconductor film. The method comprises the steps of: providing a substrate above at least an evaporation source in a vacuum condition; heating a source material contained in the evaporation source so that the source material is vapor-deposited on the substrate; and taking out the substrate under protection of an inert gas. The substrate may be rotated around an axis of a plane where the evaporation source is positioned, and the substrate is tilted by a predetermined angle with respect to the plane. The compound semi-conductive film thus prepared has a uniform thickness with a larger area. The method provides a simplified process and enhanced efficiency.

Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.

Abstract: A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic line of the upper metallization level; etching the insulating region through the hard mask so as to form a cavity; cleaning the cavity (which forms an undercut at the interface between the hard mask and the insulating region); and completely filling the cavity. The step of completely filling includes at least partially filling the cavity with copper and plugging the undercut. The undercut is plugged by sputtering a plugging material and forming an overlying doped copper layer.

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 ?m may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.

Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.

Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Abstract: To provide a reliable, efficient method for reducing oxidized metals used upon manufacturing of the multilayer interconnection structure, semiconductor device, etc. With this method vapor containing at least a carboxylic acid ester is hydrolyzed by water vapor to reduce oxidized metal. The multilayer interconnection manufacturing method of the present invention includes at least film formation step, interconnection formation step, and reduction step using the metal reduction method of the present invention. The multilayer interconnection structure of the present invention is manufactured by the multilayer interconnection structure manufacturing method of the present invention. The semiconductor device manufacturing method of the present invention includes at least film formation step, patterning step, interconnection formation step, and reduction step using the metal reduction method.

Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.

Abstract: Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a wall of the trench or via; forming a cobalt sacrificial layer on the ruthenium-containing layer before the ruthenium-containing seed layer being exposed to an environment that is oxidizing with respect to the seed layer; and contacting the cobalt sacrificial layer with a copper plating solution, the copper plating solution dissolving the cobalt sacrificial layer and plating out copper on the unoxidized ruthenium-containing seed layer. Alternatively, the ruthenium-containing seed layer may be replaced with platinum, tungsten nitride, titanium nitride or titanium or iridium. Further alternatively, the cobalt sacrificial layer may be replaced by tin, cadmium, copper or manganese.

Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.

Abstract: There is provided a method for continual preparation of granular polycrystalline silicon using a fluidized bed reactor, enabling a stable, long-term operation of the reactor by effective removal of silicon deposit accumulated on the inner wall of the reactor tube. The method comprises (i) a silicon particle preparation step, wherein silicon deposition occurs on the surface of the silicon particles, while silicon deposit is accumulated on the inner wall of the reactor tube encompassing the reaction zone; (ii) a silicon particle partial discharging step, wherein a part of the silicon particles remaining inside the reactor tube is discharged out of the fluidized bed reactor so that the height of the bed of the silicon particles does not exceed the height of the reaction gas outlet; and (iii) a silicon deposit removal step, wherein the silicon deposit is removed by supplying an etching gas into the reaction zone.

Abstract: A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An electrically conductive material is formed within the opening and elevationally over the insulative material. Some of the conductive material is removed effective to recess an outermost surface of the conductive material to from about 100 Angstroms to about 200 Angstroms from an outermost surface of the insulative material after said removing of some of the conductive material. After removing some of the conductive material, remaining volume of the opening over the conductive material is overfilled with an electrically conductive metal material different from that of the conductive material. The metal material is polished effective to form an electrically conductive plug within the opening comprising the conductive material and the metal material. Other aspects and implementations are contemplated.

Abstract: A copper wiring material surface protective liquid for production of a semiconductor device is provided, containing an oxyalkylene adduct of an acetylenediol containing an acetylenediol having an oxyalkylene having 2 or 3 carbon atoms added thereto. A method for producing a semiconductor circuit device is provided, containing: forming an insulating film and/or a diffusion preventing film on a silicon substrate; then forming a copper film by a sputtering method; then forming a copper wiring containing 80% by mass or more of copper thereon by a plating method; and flattening the wiring by a chemical mechanical polishing (CMP) method, thereby providing a semiconductor substrate containing a copper wiring, the semiconductor substrate having an exposed surface of a copper wiring material being treated by making in contact with the copper wiring material surface protective liquid.

Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.

Abstract: A copper wiring material surface protective liquid is provided that is used in production of a semiconductor circuit device containing copper wiring, and consists of an aqueous solvent and an acetylene alcohol compound containing at least 3-phenyl-2-propyn-1-ol. A method for producing a semiconductor circuit device is provided that contains: forming an insulating film and/or a diffusion preventing film on a silicon substrate; then forming a copper film by a sputtering; then forming a copper film or a copper alloy film containing 80% by mass or more of copper thereon by a plating method; and flattening the film by a chemical mechanical polishing (CMP) method, thereby providing a semiconductor substrate containing a flattened copper wiring, in which the semiconductor substrate having an exposed surface of a copper wiring material is treated by making in contact with the copper wiring material surface protective liquid.

Abstract: An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.

Abstract: A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide(CuO) to copper(Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.

Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.

Abstract: A method for manufacturing a capacitor on an integrated circuit includes providing an inter-metal dielectric layer on a substrate, a bottom layer having a first and second portions, a first insulating layer having via plug openings on the bottom layer, and via plugs disposed in the via plug openings. The via plugs include a first and second via plugs and are electrically coupled to the first portion of the bottom layer. The method further includes providing a capacitor layer having a first barrier metal layer coupled to the first via plug. The capacitor layer also has a capacitor dielectric layer overlying the first barrier metal layer and a second barrier metal overlying the capacitor dielectric layer. The method further includes defining a first and second capacitor layer portions. The first capacitor layer portion has two opposite sides and spacers disposed on their surface.

Abstract: An organic light emitting display apparatus and a method of manufacturing the organic light emitting display apparatus, whereby the manufacturing process is simplified and the electric characteristics of the organic light emitting display apparatus are improved. The organic light emitting display apparatus includes: a gate electrode that includes a first conductive layer including ITO, a second conductive layer on the first conductive layer, a third conductive layer on the second conductive layer and including ITO, and a fourth conductive layer on the third conductive layer and including IZO or AZO; and a pixel electrode formed in the same layer level as the gate electrode and including a first electrode layer that includes ITO, a second electrode layer on the first electrode layer, a third electrode layer on the second electrode layer and including ITO, and a fourth electrode layer on the third electrode layer and including IZO or AZO.

Abstract: An integrated circuit with a rectifier element. One embodiment provides a signal source, an electronic circuit and a rectifier element with a copper layer and a cuprous oxide layer adjacent to and in direct contact with the copper layer. The signal source is configured to drive a signal on a signal output terminal that is electrically coupled to the copper layer. The electronic circuit is electrically coupled to the cuprous oxide layer. The rectifier element may be formed between wiring layers of an integrated circuit.

Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: The method comprises affixing a thin sheet of crystal (8) onto metal (6) of same type as the sheet but amorphous or of small grain size, deposited in trenches of a substrate (1) to form interconnect lines for example. Annealing progressively imposes the crystalline structure of the sheet onto the lines. When the crystal (8) is removed, highly conductive crystalline lines are obtained since the grains thereof have been greatly enlarged.

Abstract: A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance.

Abstract: The present invention provides the technology for burying metal even in a fine concave portion such as trench and via. According to an embodiment of the present invention, a vapor of the metal as the objective material, a gas containing halogen for etching the metal, and a metal halide vapor made up of the metal element and the halogen element are supplied to the substrate, which thus forms a metal halide layer in the concave portion, and thereby deposits the metal under the metal halide layer. The procedure can achieve the above object.

Abstract: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device including forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350° C. to 400° C. for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150° C. to 300° C. for a time duration between about 24 to about 400 hours.

Abstract: Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first metal ring surrounding the semiconductor element; an insulation film formed to cover the semiconductor element and having the first metal ring disposed therein; and a groove formed in the insulation film; wherein: the first metal ring is formed by laminating multiple metal layers in such a manner that respective outside lateral faces of the multiple metal layers are flush with each other, or that outside lateral face of each of the multiple metal layers which is positioned above an underlying metal layer is positioned more inside than outside lateral face of the underlying metal layer; and the groove has first bottom which is disposed inside the first metal ring and extending to a depth of upper surface of an uppermost metal layer of the first metal ring.

Abstract: Metal contact formation for molecular device junctions by surface-diffusion-mediated deposition (SDMD) is described. In an example, a method of fabricating a molecular device junction by surface-diffusion-mediated deposition (SDMD) includes forming a molecular layer above a first region of a substrate. A region of metal atoms is formed above a second region of the substrate proximate to, but separate from, the first region of the substrate. A metal contact is then formed by migrating metal atoms from the region of metal atoms onto the molecular layer.

Abstract: A CMP slurry for metallic film is provided, which includes water, 0.01 to 0.3 wt %, based on a total quantity of the slurry, of polyvinylpyrrolidone having a weight average molecular weight of not less than 20,000, an oxidizing agent, a protective film-forming agent containing a first complexing agent for forming a water-insoluble complex and a second complexing agent for forming a water-soluble complex, and colloidal silica having a primary particle diameter ranging from 5 to 50 nm.

Abstract: A method induces plasma vapor deposition of metal into a recess in a workpiece. The method achieves re-sputtering of the metal at the base of the recess with a sputter gas by utilizing a mixture of Ar and He and/or Ne as the sputter gas with a ratio of He and/or Ne:Ar of at least about 10:1.

Abstract: The present invention relates to a manufacturing method for a semiconductor device, the method includes a process for forming an interlayer film on a substrate, a process for forming an opening in the interlayer, a process for forming a conductive layer which fills the opening, and a process for forming a cap film on the surface of the conductive layer. In the process for forming the cap film, a reduction process for the surface of the conductive layer and the forming of the film are performed simultaneously.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Abstract: The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.

Abstract: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Abstract: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.