Abstract: According to one embodiment, a pattern forming method includes forming a first film on an object to be processed, forming a first opening pattern and a second opening pattern in the first film, forming a second film, forming a third opening pattern and a fourth opening pattern in the second film, and processing the object to be processed. The second opening pattern is provided in a position where the second opening pattern does not overlap the first opening pattern in plan view. The third opening pattern is provided in a position where the third opening pattern partly overlaps the first opening pattern and does not overlap the second opening pattern in plan view. The fourth opening pattern is provided in a position where the fourth opening pattern does not overlap the first opening pattern, the second opening pattern, and the third opening pattern.

Abstract: Methods for selective deposition of silicon oxide films on dielectric surfaces relative to metal surfaces are provided. A metal surface of a substrate may be selectively passivated relative to the dielectric surface, such as with a polyimide layer or thiol SAM. Silicon oxide is selectively deposited on the dielectric surface relative to the passivated metal surface by contacting the dielectric surface with a metal catalyst and a silicon precursor comprising a silanol.

Abstract: A method includes forming fins extending over a semiconductor substrate; forming a photoresist structure over the fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends over the fins, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends in a first direction, wherein each bridge region extends between adjacent cut regions in a second direction, wherein the second direction is within 30° of being orthogonal to the first direction; and performing an etching process using the cut mask as an etching mask.

Abstract: A method of forming a film on a substrate that includes an etching layer and a mask formed on the etching layer. The method comprises (a) exposing the substrate, in a reaction chamber, to a precursor to dispose precursor particles on at least a sidewall of a recess in the etching layer; (b) supplying an inhibitor gas and a modification gas to the reaction chamber to generate a plasma; and (c) modifying the precursor particles on the sidewall into a protective film while the inhibitor gas and the modification gas are supplied in the reaction chamber.

Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes depositing a hard mask. A multi-layer structure is deposited over the hard mark. The multi-layer structure includes a bottom layer, a first middle layer over the bottom layer, a second middle layer over the first middle layer, and a top layer over the second middle layer. The first middle layer comprises a SiCxHyOz material in which the SiCxHyOz material has a silicon-to-silicon bond content in a range from about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first middle layer having openings. The hard mask is etched through the openings in the patterned first middle layer.

Abstract: Provided is a polishing composition that includes a cellulose derivative and is effective for reducing surface defects after polishing. According to the present application, a polishing composition comprising an abrasive, a basic compound and a surface protective agent is provided. The surface protective agent contains a cellulose derivative and a vinyl alcohol-based dispersant. The surface protective agent has a dispersibility parameter ? of less than 100.

Abstract: A method according to an embodiment includes: (a) a first step of etching a workpiece held by a holding structure in a state in which a first direction and a second direction are maintained to form a first angle, by a plasma generated in a processing container; and (a) a second step of, after execution of the first step, etching the workpiece held by the holding structure in a state in which the first direction and the second direction are maintained to form a second angle, by the plasma generated in the processing container.

Abstract: A method for selective plasma etching of silicon oxide relative to silicon nitride is described. The method includes providing a substrate containing a silicon oxide film and a silicon nitride film, and selectively etching the silicon oxide film relative to the silicon nitride film by: a1) exposing the substrate to a plasma-excited passivation gas containing carbon, sulfur, or both carbon and sulfur, where the plasma-excited passivation gas does not contain fluorine or hydrogen, and b1) exposing the substrate to a plasma-excited etching gas containing a fluorine-containing gas. The method can further include, between a1) and b1), an additional step of a2) exposing the substrate to a plasma-excited additional passivation gas containing a fluorocarbon gas, hydrofluorocarbon gas, a hydrochlorocarbon gas, a hydrochlorofluorocarbon gas, or a hydrocarbon gas, or a combination thereof.

Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.

Abstract: In an embodiment, a wafer W includes a layer EL to be etched and a mask MK4 provided on the layer EL to be etched, and a method MT of an embodiment, the layer EL to be etched is etched by removing the layer EL to be etched for each atomic layer, by repeating sequence SQ3 including step ST9a of irradiating the mask MK4 with secondary electrons by generating plasma and applying a DC voltage to an upper electrode 30 of a parallel plate electrode, and covering the mask MK4 with silicon oxide compound, step ST9b of generating plasma of fluorocarbon-based gas and forming a mixed layer MX2 including radicals on an atomic layer of the layer EL to be etched, and ST9d of generating plasma of Ar gas and applying a bias voltage to remove the mixed layer MX2.

Abstract: There is provided an etching method which includes: forming a blocking film configured to prevent an etching gas for etching a silicon-containing film from passing through each pore of a porous film and prevent the etching gas from being supplied to a film not to be etched, by supplying at least one film-forming gas to a substrate in which the silicon-containing film, the porous film, and the film not to be etched are sequentially formed adjacent to each other in a lateral direction; and etching the silicon-containing film by supplying the etching gas.

Abstract: A method includes anisotropically etching an etching target layer of a target object through an opening of the target object by generating plasma of a first gas within a processing vessel in which the target object is accommodated; and then forming a film on an inner surface of the opening by repeating a sequence comprising: a first process of supplying a second gas into the processing vessel; a second process of purging a space within the processing vessel; a third process of generating plasma of a third gas containing an oxygen atom within the processing vessel; and a fourth process of purging the space within the processing vessel. The first gas contains a carbon atom and a fluorine atom. The second gas contains an aminosilane-based gas. The etching target layer is a hydrophilic insulating layer containing silicon. Plasma of the first gas is not generated in the first process.

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Abstract: Material structures and methods for etching hexagonal, single-crystal silicon carbide (SiC) materials are provided, which include selection of on-axis or near on-axis hexagonal single-crystal SiC material as the material to be etched. The methods include etching of SiC bulk substrate material, etching of SiC material layers bonded to a silicon oxide layer, etching of suspended SiC material layers, and etching of a SiC material layer anodically bonded to a glass layer. Plasma-etched hexagonal single-crystal SiC materials of the invention may be used to form structures that include, but are not limited to, microelectromechanical beams, microelectromechanical membranes, microelectromechanical cantilevers, microelectromechanical bridges, and microelectromechanical field effect transistor devices.

Abstract: There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.

Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.

Abstract: A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.

Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.

Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.

Abstract: A method for etching features in a silicon oxide containing etch layer disposed below a patterned mask in a chamber is provided. An etch gas comprising a tungsten containing gas is flowed into the chamber. The etch gas comprising the tungsten containing gas is formed into a plasma. The silicon oxide etch layer is exposed to the plasma formed from the etch gas comprising the tungsten containing gas. Features are etched in the silicon oxide etch layer while exposed to the plasma formed from the etch gas comprising the tungsten containing gas.

Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.

Abstract: An etching method of etching a multilayered film includes etching a multilayered film by generating plasma within a processing vessel of a plasma processing apparatus. In the etching of the multilayered film, a first processing gas containing a hydrogen gas, a hydrogen bromide gas, a fluorine-containing gas, a hydrocarbon gas, a hydrofluorocarbon gas and a fluorocarbon gas is supplied from a first supply unit configured to supply a gas toward a central region of the processing target object and a second supply unit configured to supply a gas toward outer region than the central region; a second processing gas containing a hydrocarbon gas and a fluorocarbon gas is supplied from either one of the first supply unit and the second supply unit; and the first processing gas and the second processing gas are excited.

Abstract: Methods, systems, and devices are disclosed for precision fabrication of nanoscale materials and devices. In one aspect, a method to manufacture a nanoscale structure include a process to dissociate a feedstock substance including a gas or a vapor into constituents, in which the constituents include individual atoms and/or molecules. The method includes a process to deposit the constituents on a surface at a particular location. The method includes a process to grow layers layer by layer using two or more particle and/or energy beams to form a material structure, in which the energy beams include at least one of a laser beam or an atomic particle beam.

Abstract: A device wafer includes a device area where a plurality of devices are formed on the front side of the device wafer and a peripheral marginal area surrounding the device area. Each device has an adhesion disliking region disliking adhesion to an adhesive tape. An ultraviolet curable protective tape is attached as the adhesive tape to the front side of the device wafer. Ultraviolet radiation is applied to a first area of the protective tape corresponding to the adhesion disliking region of the device wafer to thereby reduce the adhesive force in the first area. The ultraviolet radiation is not applied to a second area of the protective tape corresponding to the peripheral marginal area of the device wafer to thereby maintain the adhesive force in the second area. The device wafer is held through the protective tape while the back side of the device wafer is ground.

Abstract: The present invention refers to a method for selectively structuring of a polymer matrix comprising AgNW (silver nano wires) or CNTs (carbon nano tubes) or comprising mixtures of AgNW and CNTs on a flexible plastic substructure or solid glass sheet. The method also includes a suitable etching composition, which allows to proceed the method in a mass production.

Abstract: An etching processing method for etching a substrate formed with a target film and a mask film is performed in a substrate processing apparatus including a first and a second power supply for respectively supplying a higher and a lower high frequency power to a processing space and a mounting table, and a DC power supply for supplying a DC power to an electrode. The method includes a modification step for modifying a shape of a pattern formed on the mask film; and an etching step for etching the target film by using the mask film. The mask film is etched by the plasma in the modification step. Further, in the etching step, the DC power is applied to the electrode and the lower high frequency power is applied to the mounting table in a pulse wave form in which a higher and a lower power level are repeated.

Abstract: A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.

Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.

Abstract: An etching apparatus includes: a chamber configured to accommodate a substrate to be processed having an etching target film; a gas exhaust mechanism configured to exhaust an inside of the chamber; an etching gas supply mechanism configured to supply an etching gas into the chamber; and a gas cluster generation mechanism configured to generate a gas cluster in the chamber by spraying a cluster gas into the chamber, wherein a gas produced by a reaction when the etching target film is etched with the etching gas is discharged from the chamber by the gas cluster generated by the gas cluster generation mechanism.

Abstract: A method for etching a tungsten containing layer in an etch chamber is provided. A substrate is placed with a tungsten containing layer in the etch chamber. A plurality of cycles is provided. Each cycle comprises a passivation phase for forming a passivation layer on sidewalls and bottoms of features in the tungsten containing layer. Additionally, each cycle comprises an etch phase for etching features in the tungsten containing layer.

Abstract: A method of patterning a semiconductor device using a tri-layer photoresist is disclosed. A material layer is formed over a substrate. A tri-layer photoresist is formed over the material layer. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive layer disposed over the middle layer. A lithography process is performed to pattern the photo-sensitive layer into a mask having one or more openings. Undesired portions of the mask are removed via a first etching process. Thereafter, the middle layer is patterned via a second etching process. The second etching process includes forming a coating layer around the mask while the middle layer is being etched. In some embodiments, the second etching process includes a continuous plasma etching process. The plasma etching process is performed using at least a CxHyFz gas and an H2 gas.

Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode.

Abstract: An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.

Abstract: A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate.

Abstract: A dry etching agent according to the present invention contains (A) a fluorinated propyne represented by the chemical formula: CF3C?CX where X is H, F, Cl, Br, I, CH3, CFH2 or CF2H; and either of: (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2 and COF2; (C) at least one kind of gas selected from the group consisting of F2, NF3, Cl2, Br2, I2 and YFn where Y is Cl, Br or I; and n is an integer of 1 to 5; and (D) at least one kind of gas selected from the group consisting of CF4, CHF3, C2F6, C2F5H, C2F4H2, C3F8, C3F4H2, C3ClF3H and C4F8. This dry etching agent has a small environmental load and a wide process window and can be applied for high-aspect-ratio processing without special operations such as substrate excitation.

Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.

Abstract: A silicon layer is etched through a patterned mask formed thereon using an etch chamber. A fluorine (F) containing etch gas and a silicon (Si) containing chemical vapor deposition gas are provided in the etch chamber. The fluorine (F) containing etch gas is used to etch features into the silicon layer, and the silicon (Si) containing chemical vapor deposition gas is used to form a silicon-containing deposition layer on sidewalls of the features. A plasma is generated from the etch gas and the chemical vapor deposition gas, and a bias voltage is provided. Features are etched into the silicon layer using the plasma, and a silicon-containing passivation layer is deposited on the sidewalls of the features which are being etched. Silicon in the passivation layer primarily comes from the chemical vapor deposition gas. The etch gas and the chemical vapor deposition gas are then stopped.

Abstract: A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus.

Abstract: An object is to provide a compound semiconductor substrate and a surface-treatment method thereof, in which, even after the treated substrate is stored for a long period of time, resistance-value defects do not occur. Even when the compound semiconductor substrate is stored for a long period of time and an epitaxial film is then formed thereon, electrical-characteristic defects do not occur. The semiconductor substrate according to the present invention is a compound semiconductor substrate at least one major surface of which is mirror-polished, the mirror-polished surface being covered with an organic substance containing hydrogen (H), carbon (C), and oxygen (O) and alternatively a compound semiconductor substrate at least one major surface of which is mirror-finished, wherein a silicon (Si) peak concentration at an interface between an epitaxial film grown at a growth temperature of 550° C. and the compound semiconductor substrate is 2×1017 cm?3 or less.

Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.

Abstract: Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer.

Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.

Abstract: Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a backside process gas between a substrate and a substrate support assembly, and cyclically etching a layer on the substrate.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.