Simultaneous Etching And Coating Patents (Class 438/695)
  • Patent number: 10343900
    Abstract: Material structures and methods for etching hexagonal, single-crystal silicon carbide (SiC) materials are provided, which include selection of on-axis or near on-axis hexagonal single-crystal SiC material as the material to be etched. The methods include etching of SiC bulk substrate material, etching of SiC material layers bonded to a silicon oxide layer, etching of suspended SiC material layers, and etching of a SiC material layer anodically bonded to a glass layer. Plasma-etched hexagonal single-crystal SiC materials of the invention may be used to form structures that include, but are not limited to, microelectromechanical beams, microelectromechanical membranes, microelectromechanical cantilevers, microelectromechanical bridges, and microelectromechanical field effect transistor devices.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 9, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Eugene A. Imhoff, Francis J. Kub, Karl D. Hobart, Rachael L. Myers-Ward
  • Patent number: 10211050
    Abstract: There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: February 19, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hidetami Yaegashi, Kenichi Oyama, Masatoshi Yamato, Tomohiro Iseki, Toyohisa Tsuruda
  • Patent number: 10176992
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: January 8, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 10170310
    Abstract: A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan
  • Patent number: 9941121
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian U. Engelmann, Ashish V. Jagtiani, Hiroyuki Miyazoe, Hsinyu Tsai
  • Patent number: 9911648
    Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brett C. Baker-O'Neal, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9673058
    Abstract: A method for etching features in a silicon oxide containing etch layer disposed below a patterned mask in a chamber is provided. An etch gas comprising a tungsten containing gas is flowed into the chamber. The etch gas comprising the tungsten containing gas is formed into a plasma. The silicon oxide etch layer is exposed to the plasma formed from the etch gas comprising the tungsten containing gas. Features are etched in the silicon oxide etch layer while exposed to the plasma formed from the etch gas comprising the tungsten containing gas.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 6, 2017
    Assignee: Lam Research Corporation
    Inventors: Scott Briggs, Eric Hudson, Leonid Belau, John Holland, Mark Wilcoxson
  • Patent number: 9601346
    Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
  • Patent number: 9536707
    Abstract: An etching method of etching a multilayered film includes etching a multilayered film by generating plasma within a processing vessel of a plasma processing apparatus. In the etching of the multilayered film, a first processing gas containing a hydrogen gas, a hydrogen bromide gas, a fluorine-containing gas, a hydrocarbon gas, a hydrofluorocarbon gas and a fluorocarbon gas is supplied from a first supply unit configured to supply a gas toward a central region of the processing target object and a second supply unit configured to supply a gas toward outer region than the central region; a second processing gas containing a hydrocarbon gas and a fluorocarbon gas is supplied from either one of the first supply unit and the second supply unit; and the first processing gas and the second processing gas are excited.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: January 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ryuuu Ishita, Yusuke Saitoh
  • Patent number: 9534296
    Abstract: Methods, systems, and devices are disclosed for precision fabrication of nanoscale materials and devices. In one aspect, a method to manufacture a nanoscale structure include a process to dissociate a feedstock substance including a gas or a vapor into constituents, in which the constituents include individual atoms and/or molecules. The method includes a process to deposit the constituents on a surface at a particular location. The method includes a process to grow layers layer by layer using two or more particle and/or energy beams to form a material structure, in which the energy beams include at least one of a laser beam or an atomic particle beam.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: January 3, 2017
    Assignee: McAlister Technologies, LLC
    Inventor: Roy Edward McAlister
  • Patent number: 9412637
    Abstract: A device wafer includes a device area where a plurality of devices are formed on the front side of the device wafer and a peripheral marginal area surrounding the device area. Each device has an adhesion disliking region disliking adhesion to an adhesive tape. An ultraviolet curable protective tape is attached as the adhesive tape to the front side of the device wafer. Ultraviolet radiation is applied to a first area of the protective tape corresponding to the adhesion disliking region of the device wafer to thereby reduce the adhesive force in the first area. The ultraviolet radiation is not applied to a second area of the protective tape corresponding to the peripheral marginal area of the device wafer to thereby maintain the adhesive force in the second area. The device wafer is held through the protective tape while the back side of the device wafer is ground.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 9, 2016
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 9379326
    Abstract: The present invention refers to a method for selectively structuring of a polymer matrix comprising AgNW (silver nano wires) or CNTs (carbon nano tubes) or comprising mixtures of AgNW and CNTs on a flexible plastic substructure or solid glass sheet. The method also includes a suitable etching composition, which allows to proceed the method in a mass production.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 28, 2016
    Assignee: MERCK PATENT GMBH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler, Christian Matuschek
  • Patent number: 9373521
    Abstract: An etching processing method for etching a substrate formed with a target film and a mask film is performed in a substrate processing apparatus including a first and a second power supply for respectively supplying a higher and a lower high frequency power to a processing space and a mounting table, and a DC power supply for supplying a DC power to an electrode. The method includes a modification step for modifying a shape of a pattern formed on the mask film; and an etching step for etching the target film by using the mask film. The mask film is etched by the plasma in the modification step. Further, in the etching step, the DC power is applied to the electrode and the lower high frequency power is applied to the mounting table in a pulse wave form in which a higher and a lower power level are repeated.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 21, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiromasa Mochiki, Shin Okamoto, Takashi Nishijima, Fumio Yamazaki
  • Patent number: 9337029
    Abstract: A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xianyu Wenxu, Yeon-hee Kim, Chang-youl Moon, Yong-young Park
  • Patent number: 9257280
    Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akiteru Ko, Angelique D. Raley, Kiyohito Ito
  • Patent number: 9236272
    Abstract: An etching apparatus includes: a chamber configured to accommodate a substrate to be processed having an etching target film; a gas exhaust mechanism configured to exhaust an inside of the chamber; an etching gas supply mechanism configured to supply an etching gas into the chamber; and a gas cluster generation mechanism configured to generate a gas cluster in the chamber by spraying a cluster gas into the chamber, wherein a gas produced by a reaction when the etching target film is etched with the etching gas is discharged from the chamber by the gas cluster generated by the gas cluster generation mechanism.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: January 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shuji Moriya
  • Patent number: 9230825
    Abstract: A method for etching a tungsten containing layer in an etch chamber is provided. A substrate is placed with a tungsten containing layer in the etch chamber. A plurality of cycles is provided. Each cycle comprises a passivation phase for forming a passivation layer on sidewalls and bottoms of features in the tungsten containing layer. Additionally, each cycle comprises an etch phase for etching features in the tungsten containing layer.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: January 5, 2016
    Assignee: Lam Research Corporation
    Inventors: Ramkumar Subramanian, Anne Le Gouil, Yoko Yamaguchi
  • Patent number: 9159561
    Abstract: A method of patterning a semiconductor device using a tri-layer photoresist is disclosed. A material layer is formed over a substrate. A tri-layer photoresist is formed over the material layer. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive layer disposed over the middle layer. A lithography process is performed to pattern the photo-sensitive layer into a mask having one or more openings. Undesired portions of the mask are removed via a first etching process. Thereafter, the middle layer is patterned via a second etching process. The second etching process includes forming a coating layer around the mask while the middle layer is being etched. In some embodiments, the second etching process includes a continuous plasma etching process. The plasma etching process is performed using at least a CxHyFz gas and an H2 gas.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yen Chen, Kuan Nan Liu
  • Patent number: 9159912
    Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode.
    Type: Grant
    Filed: May 10, 2014
    Date of Patent: October 13, 2015
    Assignee: SK hynix Inc.
    Inventors: Min-Suk Lee, Chang-Hyup Shin
  • Patent number: 9147688
    Abstract: An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 29, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hitoshi Saito
  • Patent number: 9136340
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: September 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
  • Patent number: 9093471
    Abstract: A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: July 28, 2015
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Chin-Te Kuo, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 9093388
    Abstract: A dry etching agent according to the present invention contains (A) a fluorinated propyne represented by the chemical formula: CF3C?CX where X is H, F, Cl, Br, I, CH3, CFH2 or CF2H; and either of: (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2 and COF2; (C) at least one kind of gas selected from the group consisting of F2, NF3, Cl2, Br2, I2 and YFn where Y is Cl, Br or I; and n is an integer of 1 to 5; and (D) at least one kind of gas selected from the group consisting of CF4, CHF3, C2F6, C2F5H, C2F4H2, C3F8, C3F4H2, C3ClF3H and C4F8. This dry etching agent has a small environmental load and a wide process window and can be applied for high-aspect-ratio processing without special operations such as substrate excitation.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: July 28, 2015
    Assignee: Central Glass Company, Limited
    Inventors: Yasuo Hibino, Tomonori Umezaki, Akiou Kikuchi, Isamu Mori, Satoru Okamoto
  • Patent number: 9029264
    Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 9018098
    Abstract: A silicon layer is etched through a patterned mask formed thereon using an etch chamber. A fluorine (F) containing etch gas and a silicon (Si) containing chemical vapor deposition gas are provided in the etch chamber. The fluorine (F) containing etch gas is used to etch features into the silicon layer, and the silicon (Si) containing chemical vapor deposition gas is used to form a silicon-containing deposition layer on sidewalls of the features. A plasma is generated from the etch gas and the chemical vapor deposition gas, and a bias voltage is provided. Features are etched into the silicon layer using the plasma, and a silicon-containing passivation layer is deposited on the sidewalls of the features which are being etched. Silicon in the passivation layer primarily comes from the chemical vapor deposition gas. The etch gas and the chemical vapor deposition gas are then stopped.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: April 28, 2015
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Robert P. Chebi
  • Publication number: 20150104942
    Abstract: A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus.
    Type: Application
    Filed: March 10, 2014
    Publication date: April 16, 2015
    Inventors: Toshiyuki SASAKI, Mitsuhiro OMURA, Kazuhito FURUMOTO
  • Patent number: 9000567
    Abstract: An object is to provide a compound semiconductor substrate and a surface-treatment method thereof, in which, even after the treated substrate is stored for a long period of time, resistance-value defects do not occur. Even when the compound semiconductor substrate is stored for a long period of time and an epitaxial film is then formed thereon, electrical-characteristic defects do not occur. The semiconductor substrate according to the present invention is a compound semiconductor substrate at least one major surface of which is mirror-polished, the mirror-polished surface being covered with an organic substance containing hydrogen (H), carbon (C), and oxygen (O) and alternatively a compound semiconductor substrate at least one major surface of which is mirror-finished, wherein a silicon (Si) peak concentration at an interface between an epitaxial film grown at a growth temperature of 550° C. and the compound semiconductor substrate is 2×1017 cm?3 or less.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: April 7, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kenichi Miyahara, Takayuki Nishiura, Mitsutaka Tsubokura, Shinya Fujiwara
  • Patent number: 8993448
    Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Terry L. Gilton
  • Patent number: 8993440
    Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
  • Patent number: 8987139
    Abstract: Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Chia-Ling Kao, Sean S. Kang, Srinivas D. Nemani
  • Patent number: 8980754
    Abstract: Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Yifeng Zhou, Srinivas D. Nemani, Khoi Doan, Jeremiah T. P. Pender
  • Patent number: 8956882
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 17, 2015
    Inventors: Kazuhiro Tomioka, Satoshi Seto, Masatoshi Yoshikawa, Satoshi Inada
  • Patent number: 8946030
    Abstract: Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Motoki Noro, Tai-Chuan Lin, Shinji Kawada
  • Patent number: 8940650
    Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan
  • Patent number: 8937017
    Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a backside process gas between a substrate and a substrate support assembly, and cyclically etching a layer on the substrate.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 20, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Alan Cheshire, Stanley Detmar
  • Patent number: 8932955
    Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: January 13, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Jongsun Sel, Yuji Takahashi
  • Publication number: 20140363975
    Abstract: A substrate etching method and a substrate processing device, the substrate etching method includes: S1: placing a substrate to be processed into a reaction chamber; S2: supplying etching gas into the reaction chamber; S3: turning on an excitation power supply to generate plasma in the reaction chamber; S4: turning on a bias power supply to apply bias power to the substrate; S5: turning off the bias power supply, and meanwhile, starting to supply deposition gas into the reaction chamber; S6: stopping supply of the deposition gas into the reaction chamber, and meanwhile, turning on the bias power supply; S7: repeating steps S5-S6, until the etching process is completed. In the whole etching process, the etching operation is always performed, and the deposition operation is performed sometimes.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 11, 2014
    Applicant: Beijing NMC Co., Ltd.
    Inventors: Gang Wei, Chun Wang, Dongsan Li
  • Patent number: 8900981
    Abstract: A feedstock of semiconductor material is placed in a crucible. A closed sacrificial recipient containing a dopant material is placed in the crucible. The content of the crucible is melted resulting in incorporation of the dopant in the molten material bath. The temperature increase is performed under a reduced pressure.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 2, 2014
    Assignees: Apollon Solar, Siltronix
    Inventors: Maxime Forster, Erwann Fourmond, Jacky Stadler, Roland Einhaus, Hubert Lauvray
  • Patent number: 8883645
    Abstract: Methods for fabrication of nanopillar field effect transistors are described. These transistors can have high height-to-width aspect ratios and be CMOS compatible. Silicon nitride may be used as a masking material. These transistors have a variety of applications, for example they can be used for molecular sensing if the nanopillar has a functionalized layer contacted to the gate electrode. The functional layer can bind molecules, causing an electrical signal in the transistor.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 11, 2014
    Assignee: California Institute of Technology
    Inventors: Chieh-Feng Chang, Aditya Rajagopal, Axel Scherer
  • Patent number: 8859430
    Abstract: A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 14, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yuki Chiba
  • Patent number: 8853086
    Abstract: Embodiments of the present disclosure relate to methods for pretreatment of substrates and group III-nitride layers for manufacturing devices such as light emitting diodes (LEDs), laser diodes (LDs) or power electronic devices. One embodiment of the present disclosure provides a method including providing one or more substrates having an aluminum containing surface in a processing chamber and exposing a surface of each of the one or more substrates having an aluminum containing surface to a pretreatment gas mixture to form a pretreated surface. The pretreatment gas mixture includes ammonia (NH3), an aluminum halide gas (e.g., AlCl3, AlCl) and an etchant containing gas that includes a halogen gas (e.g., Cl2) or hydrogen halide gas (e.g., HCl).
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: October 7, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
  • Patent number: 8846451
    Abstract: Methods for depositing metal in high aspect ratio features formed on a substrate are provided herein. In some embodiments, a method includes applying first RF power at VHF frequency to target comprising metal disposed above substrate to form plasma, applying DC power to target to direct plasma towards target, sputtering metal atoms from target using plasma while maintaining pressure in PVD chamber sufficient to ionize predominant portion of metal atoms, depositing first plurality of metal atoms on bottom surface of opening and on first surface of substrate, applying second RF power to redistribute at least some of first plurality from bottom surface to lower portion of sidewalls of the opening, and depositing second plurality of metal atoms on upper portion of sidewalls by reducing amount of ionized metal atoms in PVD chamber, wherein first and second pluralities form a first layer deposited on substantially all surfaces of opening.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Alan Ritchie, Karl Brown, John Pipitone
  • Patent number: 8846518
    Abstract: A multilayer construction is disclosed. The multilayer construction includes a -II-VI semiconductor layer (110)x and a Si3N4 layer (120) disposed directly on the II-VI semiconductor layer. To improve the adhesion of the Si3N4 layer (120) a native oxide on the II-VI semiconductor layer is removed.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: September 30, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Jun-Ying Zhang, Michael A. Haase, Todd A. Ballen, Terry L. Smith
  • Patent number: 8835320
    Abstract: An etching method can prevent adverse effects of oxygen plasma from arising under an insulating film when etching the insulating film formed on a substrate. The etching method includes: a first etching step for exposing the insulating film to processing gas that has been turned into a plasma to etch the insulating film to a portion in the thickness direction; a deposition material removing step for exposing the insulating film remaining after completion of the first etching to oxygen plasma to remove deposition material deposited on the surface of the remaining insulating film; and a second etching of exposing the remaining insulating film to processing gas that has been turned into a plasma to etch the remaining insulating film.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: September 16, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Toshihisa Ozu
  • Patent number: 8828742
    Abstract: A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihisa Iba
  • Patent number: 8822341
    Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Ho Jeon, Dong-Hyun Kim, Je-Woo Han, Kyoung-Sub Shin
  • Patent number: 8822299
    Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangwook Lee, Inseak Hwang
  • Publication number: 20140227876
    Abstract: In a semiconductor device manufacturing method having a plasma etching process, a substrate is plasma etched using a resist layer as a mask. The plasma etching process has: a first etching step wherein a mixed gas having a deposition gas and an etching gas mixed at a ratio is introduced into the processing chamber, and the substrate is plasma etched in the mixed gas atmosphere; and a step of repeating multiple times a deposition step, wherein the deposition gas is introduced into the processing chamber, and the plasma-etched substrate is subjected to deposition treatment in an atmosphere having the deposition gas as a main component, and a second etching step, wherein the etching gas is introduced into the processing chamber, and the substrate that has been subjected to the deposition treatment in the deposition step is plasma etched in an atmosphere having the etching gas as a main component.
    Type: Application
    Filed: October 5, 2012
    Publication date: August 14, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Kazuhito Tohnoe
  • Publication number: 20140203447
    Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Wai-Kin Li
  • Patent number: 8778804
    Abstract: A method and apparatus for selective etching a substrate using a focused beam. For example, multiple gases may be used that are involved in competing beam-induced and spontaneous reactions, with the result depending on the materials on the substrate. The gases may include, for example, an etchant gas and an auxiliary gas that inhibits etching.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: July 15, 2014
    Assignee: FEI Company
    Inventors: Steven Randolph, Clive D. Chandler