Abstract: A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different nFET and pFET gate electrode materials.

Abstract: A method and a plasma system are provided for anisotropically etching structures into a substrate positioned in an etching chamber, e.g., structures defined using an etching mask in a silicon substrate, using a plasma. For this purpose, the etching chamber is supplied at least intermittently with an etching gas and at least intermittently with a passivation gas, the passivation gas being supplied to the etching chamber in cycles having a time period between 0.05 second and 1 second. In the plasma system, in addition to a plasma source, via which the plasma acting on the substrate may be produced, an arrangement is provided for at least temporary supply of the etching gas and at least temporary supply of the passivation gas to the etching chamber, which arrangement is designed in such a way that the passivation gas may be supplied to the etching chamber in cycles having a time period between 0.05 second and 1 second.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a halogen and carbon containing gas source. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Abstract: A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate.

Abstract: A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is then etched using an acidic solution. Lastly, a conductive layer is formed on an exposed surface of the etched conductive interconnect.

Abstract: For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By using the low-reactivity halogen element, change to the composition of the phase change material and formation of undercut and deleterious halogen by-product are avoided.

Abstract: Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source at a first temperature and pressure and then exposing the substrate to an etchant at a second higher temperature and a higher pressure than during deposition.

Abstract: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition structures for calibrating a plasma process. The selective-redeposition structures receive a controllable and/or measurable amount of redeposited material during the plasma process.

Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.

Abstract: Etching and protective-film deposition operations E and D are in alternation repeatedly executed on a silicon substrate carried on a platform within a processing chamber. With gas inside the processing chamber having been exhausted to pump down the chamber interior, in the etching operation E, the substrate is etched by supplying etching gas into the chamber and converting it into plasma and applying a bias potential to the platform, and in the protective-film deposition operation D, a protective film is formed on the silicon substrate by supplying protective-film deposition gas into the processing chamber and converting it into plasma. When a predetermined time prior to the close of operations E and D (time intervals indicated by reference marks Ee and De) is reached, the supply of etching or protective-film deposition gas is halted, and the exhaust flow rate of gas exhausted from the chamber is made greater than that previously.

Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.

Abstract: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.

Abstract: In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: Provided herein are chemical mechanical polishing (CMP) slurries and methods for producing the same. Embodiments of the invention include CMP slurries that include (a) a metal oxide; (b) a quaternary ammonium base; and (c) a fluorinated surfactant. In some embodiments, the fluorinated surfactant is a non-ionic perfluoroalkyl sulfonyl compound. Also provided herein are methods of polishing a polycrystalline silicon surface, including providing a slurry composition according to an embodiment of the invention to a polycrystalline silicon surface and performing a CMP process to polish the polycrystalline silicon surface.

Abstract: A silicon layer is etched through a patterned mask formed thereon using an etch chamber. A fluorine (F) containing etch gas and a silicon (Si) containing chemical vapor deposition gas are provided in the etch chamber. The fluorine (F) containing etch gas is used to etch features into the silicon layer, and the silicon (Si) containing chemical vapor deposition gas is used to form a silicon-containing deposition layer on sidewalls of the features. A plasma is generated from the etch gas and the chemical vapor deposition gas, and a bias voltage is provided. Features are etched into the silicon layer using the plasma, and a silicon-containing passivation layer is deposited on the sidewalls of the features which are being etched. Silicon in the passivation layer primarily comes from the chemical vapor deposition gas. The etch gas and the chemical vapor deposition gas are then stopped.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a top layer (24) as a polysilicon; and etching the etching layer (17) using the mask layer (20) as a mask, and eliminating the top layer (24).

Abstract: A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition contains a boron surface-modified abrasive, a nitro-substituted sulfonic acid compound, a per-compound oxidizing agent, and water. The composition affords high removal rates for barrier layer materials in metal CMP processes. The composition is particularly useful in conjunction with the associated method for metal CMP applications (e.g., step 2 copper CMP processes).

Abstract: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.

Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is then hydrophilized. Silicon wafer produced thereby have a maximum local flatness value SFQRmax of 0.01 ?m to 0.035 ?m relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm2 on the front side of the silicon wafer with an edge exclusion of 2 mm.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device that includes performing an O2 plasma treatment step after forming a Si-containing photoresist film.

Abstract: After cleaning the front and back sides of a silicon wafer with a liquid SC-1 and liquid SC-2, the front and back sides of the silicon wafer are cleaned with an HF solution to be water-repellent surfaces. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced stacking faults after formation of the epitaxial layer and occurrence of cloud on the back side. Alternatively, the front and back sides of a silicon wafer are cleaned with the liquid SC-1 and liquid SC-2, and then the back side of the silicon wafer is cleaned with an HF solution to be a water-repellent surface while the front side is cleaned with purified water to be a hydrophilic surf ace. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced mounds on the front side and occurrence of cloud on the back side.

Abstract: Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon ions, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.

Abstract: Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.

Abstract: An etching method which makes it possible to obtain a desired etching shape with ease, and a computer-readable storage medium storing a program for implementing the method. The etching method is executed by a substrate processing apparatus that performs plasma processing on a semiconductor wafer by plasma. The apparatus comprises a substrate accommodating chamber for accommodating the semiconductor wafer which has an oxide film and a resist film formed on the oxide film, and an upper electrode plate disposed in the substrate accommodating chamber and exposed in a processing space in the substrate accommodating chamber. At least part of the upper electrode plate is formed of a silicon-containing material. The upper electrode plate is sputtered by plasma, and the oxide film is etched by plasma.

Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.

Abstract: A method of filling a gap on a substrate comprises disposing the substrate, on which the gap is formed, on a susceptor in a chamber; applying a source power to the chamber to generate plasmas into the chamber; supplying a process gas into the chamber; filling a thin film into a gap by applying a first bias power to the susceptor, an amplitude of the first bias power being periodically modulated; stopping supply of the process gas and cutting off the first bias power; and extinguish the plasmas in the chamber.

Abstract: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.

Abstract: A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.

Abstract: Disclosed is a method for manufacturing an optoelectronic semiconductor device having a p-n junction diode, which includes the steps of: (a) etching at least one surface of the p-n junction diode in a depth direction to form a plurality of continuous, isolated or mixed type electrode pattern grooves with a certain array; and (b) filling the formed grooves with a conductive ink containing a transparent conducting particle through an inkjet and then performing heat treatment to form a buried transparent electrode, the optoelectronic semiconductor device, and an apparatus for manufacturing the optoelectronic semiconductor device. In the present invention, covering loss is significantly reduced due to a buried transparent electrode so that the high efficiency of photoelectric conversion can be implemented, and there can be provided the easiness of a manufacturing process and the enhancement of productivity through the unification of etching and electrode forming processes.

Abstract: A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Abstract: Methods for forming an ultra thin structure. The method includes a polymer deposition and etching process. In one embodiment, the methods may be utilized to form fabricate submicron structure having a critical dimension less than 30 nm and beyond. The method further includes a multiple etching processes. The processes may be varied to meet different process requirements. In one embodiment, the process gently etches the substrate while shrinking critical dimension of the structures formed within the substrate. The dimension of the structures may be shank by coating a photoresist like polymer to sidewalls of the formed structure, but substantially no polymer accumulation on the bottom surface of the formed structure on the substrate. The embodiments described herein also provide high selectivity in between each layers formed on the substrate during the fabricating process and preserving a good control of profile formed within the structure.

Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Abstract: In a dry etching method in which clusters formed by agglomeration of atoms or molecules are ionized and accelerated as a cluster ion beam for irradiation of an object surface to etch away therefrom its constituent atoms, the clusters are mixed clusters 42 formed by agglomeration of two or more kinds of atoms or molecules, and the mixed clusters 42 contain atoms 43 of at least one of argon, neon, xenon and krypton, and a component 44 that is deposited on the object surface to form a thin film by reaction therewith. With this method, it is possible to provide an extremely reduced sidewall surface roughness and high vertical machining accuracy.

Abstract: A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively form and etch a buffer layer that protects underlying etch stop materials thereby providing highly selective etch processes.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: A process for digging deep trenches in a body of semiconductor material includes forming a mask having an opening, above a surface of a semiconductor body. A passivating layer is conformally formed on the mask and on the semiconductor body within the opening. A directional etch is extended to first remove the passivating layer from on top of the semiconductor body and then etch the semiconductor body through the opening. Forming the passivating layer and executing the directional etch are carried out repeatedly in sequence so as to form a trench through the opening. A tapered portion of the trench is formed, which has a transverse dimension decreasing as a distance from the surface of the semiconductor body increases.

Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least one valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: Plasma etch processes incorporating H2/Noble gas etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen and one or more Noble gases as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Abstract: A method for enhancing the reliability of copper interconnects and/or contacts, such as the bottom of vias exposing top surfaces of buried copper, or at the top of copper lines just after CMP. The method comprises contacting the exposed copper surface with a vapor phase compound of a noble metal and selectively forming a layer of the noble metal on the exposed copper surface, either by a copper replacement reaction or selective deposition (e.g., ALD or CVD) of the noble metal.