Plural Coating Steps Patents (Class 438/699)
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Patent number: 8513131Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.Type: GrantFiled: March 17, 2011Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Chung-hsun Lin, Chun-chen Yeh
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Publication number: 20130178067Abstract: A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.Type: ApplicationFiled: December 19, 2012Publication date: July 11, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: SAMSUNG ELECTRONICS CO., LTD.
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Patent number: 8470714Abstract: A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.Type: GrantFiled: May 22, 2012Date of Patent: June 25, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Ssu-I Fu, Chien-Liang Lin, Ying-Tsung Chen, Ted Ming-Lang Guo, Chin-Cheng Chien, Chien-Ting Lin, Wen-Tai Chiang
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Publication number: 20130143410Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.Type: ApplicationFiled: February 4, 2013Publication date: June 6, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
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Patent number: 8435900Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.Type: GrantFiled: September 23, 2011Date of Patent: May 7, 2013Assignee: Semiconductor Manufacturing International Corp.Inventors: Qun Shao, Zhongshan Hong
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Patent number: 8399774Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.Type: GrantFiled: November 23, 2011Date of Patent: March 19, 2013Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yoichi Hitomi, Hiroaki Miyazawa, Shinji Kumon, Terutoshi Momose
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Patent number: 8372513Abstract: The subject of the invention is a transparent substrate (6) having at least one antireflection coating, made from a film (A) comprising multiple thin layers of alternately high and low refractive indexes. The multilayer film comprises, in succession, a high-index first layer (1), having a refractive index n1 of between 1.8 and 2.3 and a geometrical thickness e1 of between 5 and 50 nm, a low-index second layer (2), having a refractive index n2 of between 1.30 and 1.70 and a geometrical thickness e2 of between 5 and 50 nm, a high-index third layer (3), having a refractive index n3 of between 1.8 and 2.3 and a geometrical thickness e3 of at least 100 nm, and a low-index fourth layer (4), having a refractive index n4 of between 1.30 and 1.70 and a geometrical thickness e4 of at least 80 nm. This antireflection coating can be used in solar modules.Type: GrantFiled: September 29, 2010Date of Patent: February 12, 2013Assignee: Saint-Gobain Glass FranceInventors: Charles Anderson, Ulf Blieske
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Publication number: 20130032929Abstract: Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Effendi Leobandung
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Patent number: 8338291Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.Type: GrantFiled: January 7, 2011Date of Patent: December 25, 2012Assignee: Eastman Kodak CompanyInventors: Lee W. Tutt, Shelby F. Nelson
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Publication number: 20120302066Abstract: A method of manufacturing a semiconductor device, which includes forming a resist layer on a substrate, performing an exposure and development process on the resist layer to form a resist pattern, performing a slimming process to slim the resist pattern, forming a mask material layer on side walls of the slimmed resist pattern, and removing the slimmed resist pattern. The slimming process further includes coating an extensive agent on the substrate, expanding the expansive agent, and removing the expanded expansive agent.Type: ApplicationFiled: May 6, 2011Publication date: November 29, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Fumiko Iwao
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Publication number: 20120282778Abstract: A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating pattern of four second lines is formed elevationally over and crossing the repeating pattern of four first lines. First alternating of the four second lines are removed from being received over the first lines. After the first alternating of the four second lines have been removed, elevationally exposed portions of alternating of the four first lines are removed to the underlying substrate using a remaining second alternating of the four second lines as a mask. Additional embodiments are disclosed and contemplated.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Inventors: Scott L. Light, Anton J. deVilliers
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Patent number: 8304347Abstract: A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer. An electrically insulating material layer is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A third electrically conductive material layer is nonconformally positioned over and in contact with a first portion of the semiconductor material layer.Type: GrantFiled: January 7, 2011Date of Patent: November 6, 2012Assignee: Eastman Kodak CompanyInventors: Lee W. Tutt, Shelby F. Nelson
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Publication number: 20120270398Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shun-Wei LAN, Jieh-Jang CHEN, Shih-Wei LIN, Feng-Jia SHIU, Hung Chang HSIEH
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Patent number: 8288271Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.Type: GrantFiled: November 2, 2009Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Hakeem Akinmade Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
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Patent number: 8282847Abstract: A method for etching an etch layer formed on a substrate is provided. A first photoresist (PR) mask with first mask features is provided on the etch layer. A protective coating is provided on the first PR mask by a process including at least one cycle. Each cycle includes (a) a deposition phase for depositing a deposition layer over the surface of the first mask features using a deposition gas, and (b) a profile shaping phase for shaping the profile of the deposition layer using a profile shaping gas. A liquid PR material is applied over the first PR mask having the protective coating. The PR material is patterned into a second mask features, where the first and second mask features form a second PR mask. The etch layer is etched though the second PR mask.Type: GrantFiled: December 18, 2008Date of Patent: October 9, 2012Assignee: Lam Research CorporationInventors: Andrew R. Romano, S. M. Reza Sadjadi
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Publication number: 20120220128Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.Type: ApplicationFiled: September 23, 2011Publication date: August 30, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Qun Shao, Zhongshan Hong
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Patent number: 8227350Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.Type: GrantFiled: January 2, 2009Date of Patent: July 24, 2012Assignee: Advanced Diamond Technologies, Inc.Inventors: Charles West, John Carlisle, James Netzel, Ian Wylie, Neil Kane
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Patent number: 8216944Abstract: Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.Type: GrantFiled: March 2, 2010Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hyun Kwon, Jun Seo, Jae-Seung Hwang, Ji-Young Lee
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Publication number: 20120149185Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.Type: ApplicationFiled: December 7, 2011Publication date: June 14, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Jung Kim, Ki-Hyun Hwang, Kyung-Hyun Kim, Han-Mei Choi, Dong-Chul Yoo, Chan-Jin Park, Jong-Heun Lim, Myung-Jung Pyo, Byoung-Moon Yoon, Chang-Sup Mun
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Patent number: 8183152Abstract: A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.Type: GrantFiled: October 14, 2010Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Yoon-Moon Park, Keon-Soo Kim, Min-Sung Song, Young-Ho Lee
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Patent number: 8173548Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.Type: GrantFiled: May 28, 2010Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Cheng Hung, Yung-Sung Yen, Chun-Kuang Chen
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Patent number: 8143137Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.Type: GrantFiled: February 17, 2010Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Guan Chew, Ming Zhu, Lee-Wee Teo, Harry-Hak-Lay Chuang
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Patent number: 8097811Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.Type: GrantFiled: April 4, 2008Date of Patent: January 17, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yoichi Hitomi, Hiroaki Miyazawa, Shinji Kumon, Terutoshi Momose
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Publication number: 20120009787Abstract: A method for forming a masking layer of a semiconductor device includes forming a plurality of pillar structures separated by a trench, forming a gap-fill material partially filling the trench and exposing an upper sidewall of each pillar structure, forming a masking layer that covers the pillar structures and the gap-fill material, performing an ion implantation to the masking layer to form an implanted portion covering upper portion of the gap-fill material and one side of the upper sidewalls of each pillar structure and a non-implanted portion covering the other side of the upper sidewalls of each pillar structure, forming a sacrificial layer over the masking layer, exposing the non-implanted portion of the masking layer, and selectively removing the exposed non-implanted portion.Type: ApplicationFiled: November 17, 2010Publication date: January 12, 2012Inventor: Won-Kyu KIM
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Publication number: 20110291243Abstract: Methods for manufacturing a semiconductor device in a processing chamber are provided.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Martin Jay Seamons, Kwangduk Douglas Lee, Chiu Chan, Patrick Reilly, Sudha Rathi
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Publication number: 20110260332Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.Type: ApplicationFiled: April 21, 2011Publication date: October 27, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Antonio Di Franco, Silvio Cristofalo, Marco Bonifacio
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Patent number: 8039389Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.Type: GrantFiled: February 16, 2007Date of Patent: October 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Douglas M. Reber, Mark D. Hall, Kurt H. Junker, Kyle W. Patterson, Tab Allen Stephens, Edward K. Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Irene Wright
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Patent number: 8030217Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: April 30, 2010Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 8017464Abstract: As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.Type: GrantFiled: September 12, 2009Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Masao Sugiyama, Yoshiyuki Kaneko, Yoshinori Kondo, Masayoshi Hirasawa
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Publication number: 20110212620Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.Type: ApplicationFiled: March 8, 2011Publication date: September 1, 2011Applicant: Applied Materials, Inc.Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
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Patent number: 8008205Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.Type: GrantFiled: October 13, 2006Date of Patent: August 30, 2011Assignee: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Yutaka Takafuji, Michiko Takei, Kazuhide Tomiyasu
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Publication number: 20110201202Abstract: A method of forming fine patterns of a semiconductor device, the method including providing a patternable layer; forming a plurality of first photoresist layer patterns on the patternable layer; forming an interfacial layer on the patternable layer and the plurality of first photoresist layer patterns; forming a planarization layer on the interfacial layer; forming a plurality of second photoresist layer patterns on the planarization layer; forming a plurality of planarization layer patterns using the plurality of second photoresist layer patterns; and forming a plurality of layer patterns using the plurality of planarization layer patterns and the plurality of first photoresist layer patterns.Type: ApplicationFiled: January 14, 2011Publication date: August 18, 2011Inventors: Chong-Kwang CHANG, Young-Mook OH, Seo-Woo NAM, Woo-Cheol JEON, Ju-Beom YI, Myung-Joo LEE
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Patent number: 7998868Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.Type: GrantFiled: February 26, 2010Date of Patent: August 16, 2011Assignee: Palo Alto Research Center IncorporatedInventor: Scott Jong Ho Limb
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Patent number: 7985684Abstract: A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer.Type: GrantFiled: January 7, 2011Date of Patent: July 26, 2011Assignee: Eastman Kodak CompanyInventors: Lee W. Tutt, Shelby F. Nelson
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Patent number: 7968468Abstract: In a substrate treatment method for supplying a coating solution to a substrate with projections and depressions on a front surface thereof to form a coating film on the front surface of the substrate, the coating solution is supplied to the rotating substrate to form a coating film on the front surface of the substrate, and the substrate having the coating film formed thereon is heated to adjust an etching condition of the coating film. Next, the etching solution is supplied to the rotating substrate to etch the coating film, and thereafter the coating solution is supplied to the substrate to form a flat coating film on the front surface of the substrate. Thereafter, the substrate is heated to cure the coating film. This flattens the coating film with uniformity and high accuracy without undergoing a high-load process such as chemical mechanical polishing.Type: GrantFiled: November 22, 2006Date of Patent: June 28, 2011Assignee: Tokyo Electron LimitedInventors: Shouichi Terada, Tsuyoshi Mizuno, Takeshi Uehara
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Patent number: 7947569Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.Type: GrantFiled: June 30, 2008Date of Patent: May 24, 2011Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Frank Pfirsch, Rudolf Berger, Stefan Sedlmaier, Wolfgang Lehnert, Raimund Foerg
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Patent number: 7915064Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: GrantFiled: August 10, 2009Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Guy A. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Patent number: 7911001Abstract: CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.Type: GrantFiled: July 15, 2007Date of Patent: March 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung Woo Lee, Ja Hum Ku, Taehoon Lee, Seung-Man Choi, Thomas W. Dyer
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Patent number: 7902074Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.Type: GrantFiled: April 7, 2006Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 7879645Abstract: A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.Type: GrantFiled: January 28, 2008Date of Patent: February 1, 2011Assignees: Macronix International Co., Ltd., International Business MachinesInventors: Hsiang-Lan Lung, Chung Hon Lam, Matthew J. Breitwisch, Chieh Fang Chen
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Patent number: 7879643Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion. A memory element is on the top surface of the pillar portion and comprises memory material having at least two solid phases. A top electrode is on the memory element.Type: GrantFiled: January 18, 2008Date of Patent: February 1, 2011Assignee: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Patent number: 7867902Abstract: In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments.Type: GrantFiled: July 9, 2009Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Hun Choi, Chang-Ki Hong, Hyun-Jun Sim, Yoon-Ho Son
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Patent number: 7863196Abstract: A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate.Type: GrantFiled: May 10, 2007Date of Patent: January 4, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hulin Chang, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 7855148Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.Type: GrantFiled: April 13, 2010Date of Patent: December 21, 2010Assignee: Micron Technology, Inc.Inventor: Adam L. Olson
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Patent number: 7846756Abstract: A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.Type: GrantFiled: December 31, 2008Date of Patent: December 7, 2010Assignee: SanDisk 3D LLCInventors: Bing K. Yen, Chun-Ming Wang, Yung-Tin Chen, Steven Maxwell
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Patent number: 7833872Abstract: Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.Type: GrantFiled: October 31, 2007Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Johnathan E. Faltermeier, Xi Li
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Patent number: 7799690Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: June 13, 2007Date of Patent: September 21, 2010Assignee: Renesas Electronics CorporationInventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Publication number: 20100221921Abstract: Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.Type: ApplicationFiled: March 2, 2010Publication date: September 2, 2010Inventors: Yong-Hyun Kwon, Jun Seo, Jae-Seung Hwang, Ji-Young Lee
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Patent number: 7772122Abstract: An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.Type: GrantFiled: September 18, 2008Date of Patent: August 10, 2010Assignee: Lam Research CorporationInventors: Peter Cirigliano, Helen Zhu, Ji Soo Kim, S. M. Reza Sadjadi
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Patent number: 7759261Abstract: A method for obtaining layers defined on a hybrid circuit. The hybrid circuit including a substrate and at least one elementary circuit that includes a first facet and a second facet, being hybridized via the second facet to a facet of the substrate. This facet of the substrate and each elementary circuit are coated with a first layer, the first layer is removed from the first facet of the elementary circuit, the first facet and the subsisting part of the first layer are coated with a second layer, and the subsisting part and the second layer covering it are removed. Such a method may, for example, find application to obtaining an antireflection or metal layer on a chip.Type: GrantFiled: October 13, 2004Date of Patent: July 20, 2010Assignee: Commissariat a l'Energie AtomiqueInventors: Francois Marion, Philippe Rambaud, Lydie Mathieu