Plural Coating Steps Patents (Class 438/703)
  • Patent number: 11060188
    Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 13, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sang Ho Yu, Seshadri Ganguli
  • Patent number: 11062939
    Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high quality gapfill. Some embodiments utilize chemical vapor deposition, plasma vapor deposition, physical vapor deposition and combinations thereof to deposit the gapfill. The gapfill is of high quality and similar in properties to similarly composed bulk materials.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 13, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Samuel E. Gottheim, Eswaranand Venkatasubramanian, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 11024511
    Abstract: Provided is a patterning method including: providing a strip layer with a plurality of strips A, in combination with a plurality of strips B and strips C arranged alternately between the strips A; forming a first mask layer having a first opening on the strip layer; removing the strips A and B exposed by the first opening; forming a plurality of first spacers on sidewalls defined by the first opening; forming a plurality of second spacers on sidewalls of the first spacers respectively; forming a second mask layer having a second opening on the strip layer; removing the strips A and C exposed by the second opening; forming a plurality of third spacers defined by the second opening; forming a plurality of fourth spacers on sidewalls of the third spacers respectively; and removing the strips A, the first spacers, and the third spacers to form a pattern layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 1, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Frederick Chen
  • Patent number: 10988490
    Abstract: Provided are certain amino triiodosilanes useful as silicon precursor compounds for the vapor deposition of silicon species onto the surfaces of microelectronic devices. In this regard, such precursors can be utilized, along with optional co-reactants, to deposit silicon-containing films such as silicon nitride, silicon oxide, silicon oxynitride, SiOCN, SiCN, and silicon carbide. The silicon precursors of the invention are free of Si—H bonds. Also provided is a process for preparing such silicon precursor compounds by the displacement of a halogen from tetrahalosilane compounds with secondary amines.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 27, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Manish Khandelwal, David Kuiper, Thomas H. Baum
  • Patent number: 10943048
    Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Nojima, Tomohide Tezuka, Atsushi Onishi, Kazuhiro Yamada, Shigeki Nojima, Akira Hamaguchi
  • Patent number: 10923352
    Abstract: A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 16, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier
  • Patent number: 10871712
    Abstract: A stepped substrate-coating composition having high properties of filling a pattern and capable of forming on a substrate a coating film that can be formed by photocuring, has flattening properties, and has high heat resistance after irradiation with light. A photocurable composition for coating a stepped substrate, the photocurable composition containing a polymer containing a unit structure of Formula (1): wherein A1, A2, and A3 are each independently an aromatic C6-100 ring optionally containing a heteroatom or a hydrocarbon group containing an aromatic C6-100 ring optionally containing a heteroatom, B1, B2, and B3 are each independently Formula (2): wherein R1 is a C1-10 alkylene group, a C1-10 alkenylene group, a C1-10 alkynylene group, a C6-40 arylene group, an oxygen atom, a carbonyl group, a sulfur atom, —C(O)—O—, —C(O)—NRa—, —NRb—, or a group including a combination thereof, R2 is a hydrogen atom or a C1-10 alkyl group.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 22, 2020
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Hikaru Tokunaga, Takafumi Endo, Keisuke Hashimoto, Rikimaru Sakamoto
  • Patent number: 10840097
    Abstract: In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yi-Nien Su
  • Patent number: 10818598
    Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Wang, Chung-Chi Ko, Po-Cheng Shih
  • Patent number: 10796947
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jack Liu, Wei-Cheng Wu, Charles Chew-Yuen Young, Sing-Kai Huang
  • Patent number: 10787744
    Abstract: The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. In other embodiments, the etching rate is increased by removing residual species bound to and/or adsorbed onto the surface.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 29, 2020
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Steven McClellan George, Nicholas Ray Johnson, Jaime Willadean Dumont, Amy Elizabeth Marquardt, Younghee Lee, David Richard Zywotko, Aziz Abdulagatov
  • Patent number: 10777559
    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
  • Patent number: 10748768
    Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • Patent number: 10741391
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary, and the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. The method also includes exposing a portion of the resist layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process. The method further includes etching a portion of the resist layer to form a patterned resist layer and patterning the material layer by using the patterned resist layer as a mask. The method also includes removing the patterned resist layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Patent number: 10741392
    Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Teng-Chun Tsai
  • Patent number: 10707119
    Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl, Vimal K. Kamineni
  • Patent number: 10689514
    Abstract: A silicon-containing resin composition with which it is possible to form a silica-based coating film in which generation of cracks is minimized, a method for forming a silica-based coating film using the silicon-containing resin composition, and a crack-free silica-based coating film formed using the silicon-containing resin composition. The silicon-containing resin composition includes a silicon-containing resin and a solvent, in which one or more of siloxane resins and polysilanes is used as the silicon-containing resin, and the solvent contains a cycloalkyl acetate having a specific structure.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 23, 2020
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Hiroki Chisaka, Mayumi Kuroko, Kunihiro Noda, Dai Shiota
  • Patent number: 10676554
    Abstract: A polymer compound comprising a repeating unit having at least one group selected from the group consisting of a blocked isocyanato group and a blocked isothiocyanato group, a repeating unit having at least one group selected from the group consisting of a hydroxy group and a carboxy group and a repeating unit represented by the following formula (1), wherein the content of the repeating unit having at least one group selected from the group consisting of a blocked isocyanato group and a blocked isothiocyanato group in the polymer compound is 1% by mol or more and 30% by mol or less when the total content of all repeating units contained in the above-described polymer compound is taken as 100% by mol: in the formula (1), R2, R2 and R3 each independently represent a hydrogen atom or a methyl group.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 9, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Yuki Yokoi
  • Patent number: 10672790
    Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Geun Yu, Daehyun Jang
  • Patent number: 10670969
    Abstract: [Problem] To provide a composition, which is a reverse pattern formation composition comprising an aqueous solvent having little influence on a resist pattern, and which is excellent in flatness and filling properties after coating and has excellent etching resistance. Furthermore, a method for forming a pattern using the same is provided. [Means for Solution] A reverse pattern formation composition comprising a polysiloxane compound comprising a repeating unit having a nitrogen-containing group and a solvent comprising water, and a method for forming a fine pattern using the same.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: June 2, 2020
    Assignee: AZ Electronic Materials (Luxembourg) S.A.R.L.
    Inventors: Xiaowei Wang, Tatsuro Nagahara
  • Patent number: 10629436
    Abstract: A method for providing an etch mask for microelectronic processing that includes forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer. If a following step, the material stack may be patterned and etched to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer. A sidewall spacer is formed on sidewalls of the double mandrel structures.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Mignot, Yongan Xu
  • Patent number: 10556986
    Abstract: A polymer including a structural unit represented by Chemical Formula 1, and an organic layer composition including the polymer, and method of forming patterns are provided. The Chemical Formula 1 is the same as defined in the detailed description.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Youjung Park, Sunyoung Yang, Hyo Young Kwon
  • Patent number: 10522550
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
  • Patent number: 10515816
    Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Keren Jacobs Kanarik, Jeffrey Marks, Harmeet Singh, Samantha SiamHwa Tan, Alexander Kabansky, Wenbing Yang, Taeseung Kim, Dennis M. Hausmann, Thorsten Lill
  • Patent number: 10504775
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Patent number: 10490406
    Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 26, 2019
    Assignee: Appled Materials, Inc.
    Inventors: Mandar B. Pandit, Mang-Mang Ling, Tom Choi, Nitin K. Ingle
  • Patent number: 10468251
    Abstract: A method of forming spacers for spacer-defined multiple pattering (SDMP), includes: depositing a pattern transfer film by PEALD on the entire patterned surface of a template using halogenated silane as a precursor and nitrogen as a reactant at a temperature of 200° C. or less, which pattern transfer film is a silicon nitride film; dry-etching the template using a fluorocarbon as an etchant, and thereby selectively removing a portion of the pattern transfer film formed on a top of a core material and a horizontal portion of the pattern transfer film while leaving the core material and a vertical portion of the pattern transfer film as a vertical spacer, wherein a top of the vertical spacer is substantially flat; and dry-etching the core material, whereby the template has a surface patterned by the vertical spacer on a underlying layer.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 5, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Toshiharu Watarai
  • Patent number: 10453699
    Abstract: An etching method includes a loading step of loading into a chamber a target substrate in which a mask film is laminated on an organic film; a first etching step of etching the organic film below the mask film by plasma of a processing gas in which a flow rate ratio of a second gas containing sulfur to a first gas containing oxygen is set to a first flow rate ratio; and a second etching step of further etching the organic film by plasma of a processing gas in which a flow rate ratio of the second gas to the first gas is set to a second flow rate ratio different from the first flow rate ratio. The first etching step and the second etching step are alternately performed multiple times.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 22, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kosuke Koiwa
  • Patent number: 10373827
    Abstract: A method of pattern transfer is provided, comprising: providing a target layer; forming a first pattern above the target layer; forming a second pattern (such as spacer loops) above the target layer and above the first pattern, wherein one closed end of the second pattern partially overlaps with the first pattern; and transferring the second pattern to the target layer, wherein the first pattern stops transferring pattern of the closed end of the second pattern to the target layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10366996
    Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert C. Wong, Lei Zhuang, Ananthan Raghunathan
  • Patent number: 10332836
    Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Wang, Chung-Chi Ko, Po-Cheng Shih
  • Patent number: 10329144
    Abstract: A substrate treatment method using a block copolymer containing a hydrophilic polymer and a hydrophobic polymer includes a polymer separating step, wherein a ratio of a molecular weight of the hydrophilic polymer in the block copolymer is adjusted to 20% to 40% so that the hydrophilic polymers align at positions corresponding to a hexagonal close-packed structure in a plan view after the polymer separating step, and at the polymer separating step, a columnar first hydrophilic polymer is phase-separated on each of circular patterns of hydrophobic coating films and a columnar second hydrophilic polymer is phase-separated between the first hydrophilic polymers, and a diameter of the circular pattern is set so that the first hydrophilic polymers and the second hydrophilic polymers align at positions corresponding to the hexagonal close-packed structure in a plan view.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 25, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Muramatsu, Tadatoshi Tomita, Hisashi Genjima, Gen You, Takahiro Kitano, Takanori Nishi
  • Patent number: 10319592
    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a hard mask film on a lower film and forming first spacers on the hard mask film. The first spacers may define an exposure region of the hard mask film, and the exposure region may include a patterning portion and a non-patterning portion. The methods may also include forming a mold film on the first spacers and forming a blocking pattern in the mold film. The blocking pattern may vertically overlap the non-patterning portion. The methods may further include exposing the first spacers by removing the mold film after forming the blocking pattern.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jaewoo Kim
  • Patent number: 10319636
    Abstract: Methods comprising depositing a film material to form an initial film in a trench in a substrate surface are described. The film is treated to expand the film to grow beyond the substrate surface.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 11, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Atashi Basu, Abhijit Basu Mallick, Ziqing Duan, Srinivas Gandikota
  • Patent number: 10276379
    Abstract: In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Yihong Chen
  • Patent number: 10260150
    Abstract: Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 16, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Vinh Luong, Akiteru Ko
  • Patent number: 10204783
    Abstract: A method of forming fine island patterns of semiconductor devices includes: forming first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; forming first linear patterns each extending along a first direction, second linear patterns each extending along a second direction, and third linear patterns each extending along a third direction in the hard mask layer by at least one patterning process; etching the upper buffer mask layer to form second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: February 12, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Patent number: 10197917
    Abstract: The present invention provides a resist underlayer film-forming composition for lithography for forming a resist underlayer film that can be used as a hard mask with use of hydrolysis-condensation product of a hydrolyzable silane which also absorbs KrF laser. A resist underlayer film-forming composition for lithography comprising, as a silane, a hydrolyzable silane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein the hydrolyzable silane includes a hydrolyzable silane of Formula (1): R1aR2bSi(R3)4?(a+b)??Formula (1) [where R1 is an organic group of Formula (2): and is bonded to a silicon atom through a Si?C bond; R3 is an alkoxy group, an acyloxy group, or a halogen group; a is an integer of 1; b is an integer of 0 to 2; and a+b is an integer of 1 to 3], and a ratio of sulfur atoms to silicon atoms is 7% by mole or more in the whole of the silane.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: February 5, 2019
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Makoto Nakajima, Wataru Shibayama, Satoshi Takeda, Kenji Takase
  • Patent number: 10191374
    Abstract: The present invention provides a novel resist underlayer film-forming composition capable of forming a resist underlayer film that has etching resistance and excellent embeddability in a surface having concave portions and/or convex portions. A resist underlayer film-forming composition comprising a polymer having a structural unit represented by formula (1) or formula (2): (wherein X is an arylene group, n is 1 or 2, and R1, R2, R3, and R4 are each independently a hydrogen atom, a hydroxy group, a C1-3 alkyl group, or a phenyl group), and a solvent.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: January 29, 2019
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Hirokazu Nishimaki, Keisuke Hashimoto, Takafumi Endo, Rikimaru Sakamoto
  • Patent number: 10177002
    Abstract: Improved methods for chemically etching silicon are provided herein. In some embodiments, a method of etching a silicon material includes: (a) exposing the silicon material to a halogen-containing gas; (b) evacuating the halogen-containing gas from the semiconductor processing chamber; (c) exposing the silicon material to an amine vapor to etch a monolayer of the silicon material; (d) evacuating the amine vapor from the semiconductor processing chamber and; (e) optionally repeating (a)-(d) to etch the silicon material to a predetermined thickness.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Geetika Bajaj, Ravindra Patil, Prerna Goradia, Robert Jan Visser
  • Patent number: 10163648
    Abstract: Provided is a material composition and method for that includes providing a primer material including a surface interaction enhancement component, and a cross-linkable component. A cross-linking process is performed on the deposited primer material. The cross-linkable component self-cross-links in response to the cross-linking process to form a cross-linked primer material. The cross-lined primer material can protect an underlying layer while performing at least one process on the cross-linked primer material.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10162265
    Abstract: Pattern treatment methods comprise: (a) providing a semiconductor substrate comprising a patterned feature on a surface thereof; (b) applying a pattern treatment composition to the patterned feature, wherein the pattern treatment composition comprises a polymer comprising a surface attachment group for forming a bond with a surface of the patterned feature and a solvent, and wherein the pattern treatment composition is free of crosslinkers; (c) removing residual pattern treatment composition from the substrate with a first rinse agent, leaving a coating of the polymer over and bonded to the surface of the patterned feature; and (d) rinsing the polymer-coated patterned feature with a second rinse agent that is different from the first rinse agent, wherein the polymer has a solubility that is greater in the first rinse agent than in the second rinse agent. The methods find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: December 25, 2018
    Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Jong Keun Park, Mingqi Li, Amy M. Kwok, Phillip D. Hustad
  • Patent number: 10151977
    Abstract: A resin composition comprising a binder resin (A), a compound (B) having an acidic group or latent acidic group, an organic solvent (C), and a compound (D) having one atom selected from a silicon atom, titanium atom, aluminum atom, and zirconium atom and having a hydrocarbyloxy group or hydroxy group bonded with that atom, wherein the compound (B) is at least one type selected from the group consisting of an aliphatic compound, aromatic compound, and heterocyclic compound, and a content of the compound (B) is 0.1 to 2.5 parts by weight and a content of the compound (D) is 2.2 to 7.0 parts by weight with respect to 100 parts by weight of the binder resin (A) is provided.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: December 11, 2018
    Assignee: ZEON CORPORATION
    Inventors: Takashi Tsutsumi, Yumi Osaku
  • Patent number: 10115726
    Abstract: Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A multiline layer is formed of three or more different materials that provide differing etch characteristics. Etch masks, including interwoven etch masks, are used to selectively etch cuts within selected, exposed materials. Structures can then be cut and formed. Forming structures and cuts can be recorded in a memorization layer, which can also be used as an etch mask.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Hoyoung Kang, Anton J. deVilliers
  • Patent number: 10114286
    Abstract: A photoresist with a group which will decompose bonded to a high etching resistance moiety is provided. Alternatively, the group which will decompose can additionally be attached to a re-attachment group that will re-attach to the polymer after the group which will decompose has cleaved from the polymer. The photoresist may also comprise a non-leaving monomer with a cross-linking site and a cross-linking agent.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hau Wu, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 10096476
    Abstract: A composition for manufacturing a semiconductor device includes at least one carbon-based compound that includes at least one of an alkyne group and an azide group, and a solvent. A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, coating the feature layer with a composition including alkyne and azide, forming a carbon-containing layer including a triazole compound by performing a heat treatment on the coated composition, forming a photoresist film on the carbon-containing layer, forming photoresist patterns by exposing and developing the photoresist film, and patterning the carbon-containing layer and the feature layer using the photoresist patterns.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Park, Hyun-woo Kim, Myeong-koo Kim
  • Patent number: 10095115
    Abstract: Methods of forming edge etch protection using dual layers of positive-negative tone resists. According to a method, a wafer substrate is provided. A first type resist is deposited on a surface of the wafer substrate. The first type resist is patterned and a resist ring is created around a peripheral edge of the wafer substrate. The resist ring is cured. A second type resist is deposited on the surface of the wafer substrate and the resist ring. The second type resist is different from the first type resist.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher B. Shing, Joyce C. Liu, Richard D. Kaplan, Timothy J. Wiltshire, Darius Brown
  • Patent number: 10090398
    Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
  • Patent number: 10079142
    Abstract: An apparatus for treating a substrate includes an injecting member having a first nozzle configured to supply a first chemical to the substrate that is mounted on the supporting unit, and a second nozzle configured to supply a second chemical, which is different from the first chemical, to the substrate that is mounted on the supporting unit, and a controller configured to supply the first chemical before supplying the second chemicals and to control the first chemical, which is variable according to a type of thin film on the substrate mounted on the supporting unit, to be supplied.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 18, 2018
    Assignee: SEMES CO., LTD.
    Inventors: Dae Min Kim, Sul Lee, Bok Kyu Lee, Jae Myoung Lee
  • Patent number: 10079154
    Abstract: A method for selectively etching SiN with respect to SiO or SiGe or Si of a structure is provided comprising providing a plurality of cycles of atomic layer etching. Each cycle comprises a fluorinated polymer deposition phase comprising flowing a fluorinated polymer deposition gas comprising a hydrofluorocarbon gas into the plasma processing chamber, forming the fluorinated polymer deposition gas into a plasma, which deposits a hydrofluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas into the plasma processing chamber and an activation phase comprising flowing an activation gas comprising at least one of NH3 or H2 into the plasma processing chamber, forming the activation gas into a plasma, wherein plasma components from NH3 or H2 cause SiN to be selectively etched with respect to SiO or SiGe or Si, and stopping the flow of the activation gas into the plasma processing chamber.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 18, 2018
    Assignee: Lam Research Corporation
    Inventors: Daniel Le, Gerardo Delgadino