Plural Coating Steps Patents (Class 438/703)
  • Patent number: 11977331
    Abstract: A resist underlayer film that exhibits removability and preferably solubility only in wet etching reagent solutions, while exhibiting good resistance to resist developers that are resist solvents or aqueous alkali solutions. The composition for forming a resist underlayer film includes a dicyanostyryl group-bearing polymer (P) or dicyanostyryl group-bearing compound (C) and includes solvent, and does not contain a protonic acid curing catalyst and does not contain an alkylated aminoplast crosslinking agent derived from melamine, urea, benzoguanamine, or glycoluril.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 7, 2024
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Takafumi Endo, Yuki Endo
  • Patent number: 11955337
    Abstract: A substrate processing method includes: providing a substrate including a mask; forming a film on the mask; forming a reaction layer on a surface layer of the film; and removing the reaction layer by applying energy to the reaction layer.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: April 9, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Takayuki Katsunuma, Shinya Ishikawa, Yoshihide Kihara, Masanobu Honda
  • Patent number: 11894236
    Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Jun Xia, Kangshu Zhan, Tao Liu, Penghui Xu, Sen Li, Yanghao Liu
  • Patent number: 11868044
    Abstract: The invention relates to a crosslinkable prepolymer composition for use as a contrast layer. It also relates to a method for structuring an interface material. This method is characterized in particular by the following steps: depositing, on a block copolymer film, a prepolymer composition layer comprising a plurality of functional monomers and at least one crosslinkable functional group within its polymer chain and, on the other hand, two chemically different crosslinking agents, each agent being capable of initiating the crosslinking of said prepolymer in response to a stimulation specific thereto, subjecting the stack to a first stimulation localized on first areas, so as to cause a crosslinking reaction of the molecular chains of said prepolymer, and subjecting the stack to a second stimulation, so as to cause crosslinking of the molecular chains of said prepolymer by the action of said second crosslinking agent in secondary areas.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 9, 2024
    Assignee: Arkema France
    Inventor: Xavier Chevalier
  • Patent number: 11822247
    Abstract: The present invention is a material for forming an organic film, including: a compound shown by the following general formula (1); and an organic solvent, where in the general formula (1), X represents an organic group with a valency of “n” having 2 to 50 carbon atoms or an oxygen atom, “n” represents an integer of 1 to 10, and R1 independently represents any of the following general formulae (2), where in the general formulae (2), broken lines represent attachment points to X, and Q1 represents a monovalent organic group containing a carbonyl group, at least a part of which is a group shown by the following general formulae (3), where in the general formulae (3), broken lines represent attachment points, X1 represents a single bond or a divalent organic group having 1 to 20 carbon atoms optionally having a substituent when the organic group has an aromatic ring, R2 represents a hydrogen atom, a methyl group, an ethyl group, or a phenyl group, and ** represents an attachment point.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 21, 2023
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takayoshi Nakahara, Daisuke Kori, Yusuke Biyajima
  • Patent number: 11810786
    Abstract: A method for fabricating a semiconductor device includes following steps: A patterned mask layer including a plurality of standing walls and a covering part is formed on a surface of a semiconductor substrate, wherein two adjacent standing walls define a first opening exposing a part of the surface, and the covering part blankets the surface. A first patterned photoresist layer is formed to partially cover the covering part. A first etching process is performed to form a first trench in the substrate, passing through the surface and aligning with the first opening. A portion of the patterned mask layer is removed to form a second opening exposing another portion of the surface. A second etching process is performed to form a second trench in the substrate and define an active area on the surface. The depth of the first trench is greater than that of the second trench.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: November 7, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Cheng-Han Lu
  • Patent number: 11791209
    Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Heon Lee, Munjun Kim, Jaekang Koh, Tae-Jong Han
  • Patent number: 11765911
    Abstract: A spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device includes a SOT MRAM cell containing a first two terminal selector element, a nonmagnetic metallic assist plate, and a magnetic tunnel junction located between the first two terminal selector element and the nonmagnetic metallic assist plate, and a circuit selection element selected from a transistor or a second two terminal selector element electrically connected to the nonmagnetic metallic assist plate of the SOT MRAM cell.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: September 19, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lei Wan, Jordan Katine, Neil Robertson
  • Patent number: 11747728
    Abstract: An object of the present invention is to provide a new compound that is useful as a film forming material for lithography and the like. The above object can be achieved by a compound represented by the following formula (1).
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: September 5, 2023
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Junya Horiuchi, Yu Okada, Takashi Makinoshima, Masatoshi Echigo
  • Patent number: 11751384
    Abstract: A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11749529
    Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 5, 2023
    Assignee: International Business Machines Corporation
    Inventors: Rasit Onur Topaloglu, Kafai Lai, Dongbing Shao, Zheng Xu
  • Patent number: 11651961
    Abstract: A lithography method includes forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer; coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation; performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer; performing an exposure process using the EUV radiation to the MePR layer; and developing the MePR layer to form a patterned photoresist layer.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chien-Chih Chen
  • Patent number: 11653493
    Abstract: A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Jeong, Sangjun Hong, Sunil Shim, Kyunghyun Kim, Changsup Mun
  • Patent number: 11631705
    Abstract: A method of manufacturing a display substrate, a display substrate and a display panel are provided. The method of manufacturing a display substrate includes: infiltrating an etching point of a film group with an etching solution, to form an infiltration groove at the etching point of a film group; and patterning a remaining part of the film group at the infiltration groove, to obtain a via hole penetrating the remaining part of the film group.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 18, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongda Sun, Wenjun Hou
  • Patent number: 11621277
    Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 4, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Monica Titus, Zhixin Cui, Senaka Kanakamedala, Yao-Sheng Lee, Chih-Yu Lee
  • Patent number: 11569089
    Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
  • Patent number: 11545364
    Abstract: A method includes performing a first on phase including applying an SP pulse to an SP electrode to generate plasma, performing a second on phase after the first on phase, performing a corner etch phase after the second on phase, and performing a by-product management phase after the corner etch phase. The SP pulse terminates at the end of the first on phase. The second on phase includes applying a first BP pulse to a BP electrode coupled to a target substrate. The first BP pulse includes a first BP power level and accelerates ions of the plasma toward to target substrate. The corner etch phase includes applying a BP spike including a second BP power level greater than the first BP power level. The duration of the BP spike is less than the duration of the first BP pulse.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 3, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Peter Ventzek, Alok Ranjan, Kensuke Taniguchi, Shinya Morikita
  • Patent number: 11521855
    Abstract: A pattern formation method includes forming an organic film on a substrate, processing the organic film to form an organic film pattern, exposing the organic film pattern to an organic gas, and exposing the organic film pattern to a metal-containing gas, and after (i) exposing the organic film pattern to the organic gas and (ii) exposing the organic film pattern to the metal-containing gas, treating the organic film pattern with an oxidizing agent.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Ryosuke Yamamoto, Koji Asakawa, Ayaka Suko
  • Patent number: 11495460
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate, and forming a first layer over the material layer. The method also includes forming a second layer over the first layer, and the second layer includes an auxiliary. The method further includes forming a third layer over the second layer, and the third layer includes an inorganic material, the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. A topmost surface of the second layer is in direct contact with a bottommost surface of the third layer. The method includes exposing a portion of the second layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Patent number: 11462406
    Abstract: The present disclosure provides a semiconductor device structure with fine boron nitride spacer patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first boron nitride spacer disposed over the first target structure, wherein a topmost point of the first boron nitride spacer is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Pei Cheng Fan
  • Patent number: 11456173
    Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 27, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Meenakshi Gupta, Rui Cheng, Srinivas Guggilla, Karthik Janakiraman, Diwakar N. Kedlaya, Zubin Huang
  • Patent number: 11421324
    Abstract: Embodiments of the present disclosure generally relate to hardmasks and to processes for forming hardmasks by plasma-enhanced chemical vapor deposition (PECVD). In an embodiment, a process for forming a hardmask layer on a substrate is provided. The process includes introducing a substrate to a processing volume of a PECVD chamber, the substrate on a substrate support, the substrate support comprising an electrostatic chuck, and flowing a process gas into the processing volume within the PECVD chamber, the process gas comprising a carbon-containing gas. The process further includes forming, under plasma conditions, an energized process gas from the process gas in the processing volume, electrostatically chucking the substrate to the substrate support, depositing a first carbon-containing layer on the substrate while electrostatically chucking the substrate, and forming the hardmask layer by depositing a second carbon-containing layer on the substrate.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 23, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jui-Yuan Hsu, Krishna Nittala, Pramit Manna, Karthik Janakiraman
  • Patent number: 11380553
    Abstract: The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method for fabricating the semiconductor device includes providing a target layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers. The first tilted etch process and the second tilted etch process use the second hard mask layers as pattern guides and the first hard mask layer is turned into a patterned first hard mask layer by the first openings and the second openings.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 5, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Huan-Yung Yeh
  • Patent number: 11378882
    Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
  • Patent number: 11361967
    Abstract: New lithographic compositions for use as EUV silicon hardmask layers are provided. The present invention provides methods of fabricating microelectronic structures and the resulting structures formed thereby using EUV lithographic processes. The method involves utilizing a silicon hardmask layer immediately below the photoresist layer. The silicon hardmask layer can either be directly applied to the substrate, or it can be applied to any intermediate layer(s) that may be applied to the substrate. The preferred silicon hardmask layers are formed from spin-coatable, polymeric compositions. The inventive method improves adhesion and reduces or eliminates pattern collapse issues.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Brewer Science, Inc.
    Inventors: Yichen Liang, Andrea M. Chacko, Yubao Wang, Douglas J. Guerrero
  • Patent number: 11348800
    Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsuan Chen, Yuan-Sheng Huang
  • Patent number: 11322353
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a layer to-be-etched including a first sub-trench region and a second sub-trench region. The method also includes forming a first mask layer over the layer to-be-etched and a second mask layer over the first mask layer, and forming a first sub-trench disposed over the first sub-trench region in the second mask layer. In addition, the method includes forming a first divided trench in the first mask layer and forming a second sub-trench disposed over the second sub-trench region in the second mask layer. Further, the method includes forming a first divided filling layer in the first divided trench, and forming a first middle trench in the first mask layer. The first divided filling layer divides the first middle trench in a second direction.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 3, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jisong Jin, Zejun He, Jia Ni, Yanhua Wu, Junling Pang
  • Patent number: 11287742
    Abstract: A method for reducing the level difference (iso-dense bias) (reverse bump) of a resist underlayer film formed on a semiconductor substrate having a stepped portion and a non-stepped portion by 5 nm or more, which comprises a step of applying the composition to an upper surface of the semiconductor substrate having a stepped portion and a non-stepped portion. A method for reducing the level difference (iso-dense bias) of a resist underlayer film, comprising the steps of adding a fluorine-containing surfactant to a resist underlayer film-forming composition containing a polymer and a solvent and applying the composition containing the fluorine-containing surfactant to an upper surface of a semiconductor substrate having a stepped portion and a non-stepped portion. The level difference of a resist underlayer film formed on a semiconductor substrate between a stepped portion and a non-stepped portion (i.e., reverse bump) is reduced by 5 nm or more.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 29, 2022
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Hirokazu Nishimaki, Takafumi Endo
  • Patent number: 11257681
    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Stuart Sieg, Daniel James Dechene, Eric Miller
  • Patent number: 11248086
    Abstract: A hard-mask forming composition, which is used for forming a hard mask used in lithography, including a first resin and a second resin, in which an amount of carbon contained in the first resin is 85% by mass or more with respect to the total mass of all elements constituting the first resin, and the amount of carbon contained in the second resin is 70% by mass or more with respect to the total mass of all elements constituting the second resin and less than the amount of carbon contained in the first resin.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 15, 2022
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Keiichi Ibata, Ryoji Watanabe
  • Patent number: 11232952
    Abstract: The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: January 25, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Yi-Hsien Chou
  • Patent number: 11220570
    Abstract: A polymer, a hardmask composition, and a method of forming patterns, the polymer including structural units obtained by a reaction of a reaction mixture that includes a substituted or unsubstituted indole compound, a first aromatic aldehyde compound including a substituted or unsubstituted C3 to C20 branched alkyl group thereon, and a second aromatic aldehyde compound that is different from the first aromatic aldehyde compound.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Soyeon Park, Youngmin Kim, Yongsik Yoo
  • Patent number: 11169441
    Abstract: A resist underlayer film forming composition characterized by containing (A) a compound represented by formula (1) (in formula (1), independently, R1 represents a C1 to C30 divalent group; each of R2 to R7 represents a C1 to C10 linear, branched, or cyclic alkyl group, a C6 to C10 aryl group, a C2 to C10 alkenyl group, a thiol group, or a hydroxyl group; at least one R5 is a hydroxyl group or a thiol group; each of m2, m3, and m6 is an integer of 0 to 9; each of m4 and m7 is an integer of 0 to 8; m5 is an integer of 1 to 9; n is an integer of 0 to 4; and each of p2 to p7 is an integer of 0 to 2) and a cross-linkable compound represented by formula (2-1) or (2-2) (in formula (2), Q1 represents a single bond or an m12-valent organic group; each of R12 and R15 independently represents a C2 to C10 alkyl group or a C2 to C10 alkyl group having a C1 to C10 alkoxy group; each of R13 and R16 represents a hydrogen atom or a methyl group; each of R14 and R17 represents a C1 to C10 alkyl group or a C6 to C40 aryl group;
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 9, 2021
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Daigo Saito, Keisuke Hashimoto, Rikimaru Sakamoto
  • Patent number: 11139205
    Abstract: Described are semiconductor devices, methods of manufacturing, and methods for device patterning. More particularly, a subtractive interconnect patterning method is described. A subtractive interconnect patterning is used in place of damascene interconnect patterning.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 5, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lei Zhong, Ho-yung David Hwang
  • Patent number: 11107723
    Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 31, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Long Wang, Zijun Sun, Chin-Chun Huang, Hailong Gu, Penghui Lu, Wen Yi Tan
  • Patent number: 11062939
    Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high quality gapfill. Some embodiments utilize chemical vapor deposition, plasma vapor deposition, physical vapor deposition and combinations thereof to deposit the gapfill. The gapfill is of high quality and similar in properties to similarly composed bulk materials.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 13, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Samuel E. Gottheim, Eswaranand Venkatasubramanian, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 11060188
    Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 13, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sang Ho Yu, Seshadri Ganguli
  • Patent number: 11024511
    Abstract: Provided is a patterning method including: providing a strip layer with a plurality of strips A, in combination with a plurality of strips B and strips C arranged alternately between the strips A; forming a first mask layer having a first opening on the strip layer; removing the strips A and B exposed by the first opening; forming a plurality of first spacers on sidewalls defined by the first opening; forming a plurality of second spacers on sidewalls of the first spacers respectively; forming a second mask layer having a second opening on the strip layer; removing the strips A and C exposed by the second opening; forming a plurality of third spacers defined by the second opening; forming a plurality of fourth spacers on sidewalls of the third spacers respectively; and removing the strips A, the first spacers, and the third spacers to form a pattern layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 1, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Frederick Chen
  • Patent number: 10988490
    Abstract: Provided are certain amino triiodosilanes useful as silicon precursor compounds for the vapor deposition of silicon species onto the surfaces of microelectronic devices. In this regard, such precursors can be utilized, along with optional co-reactants, to deposit silicon-containing films such as silicon nitride, silicon oxide, silicon oxynitride, SiOCN, SiCN, and silicon carbide. The silicon precursors of the invention are free of Si—H bonds. Also provided is a process for preparing such silicon precursor compounds by the displacement of a halogen from tetrahalosilane compounds with secondary amines.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 27, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Manish Khandelwal, David Kuiper, Thomas H. Baum
  • Patent number: 10943048
    Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Nojima, Tomohide Tezuka, Atsushi Onishi, Kazuhiro Yamada, Shigeki Nojima, Akira Hamaguchi
  • Patent number: 10923352
    Abstract: A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 16, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier
  • Patent number: 10871712
    Abstract: A stepped substrate-coating composition having high properties of filling a pattern and capable of forming on a substrate a coating film that can be formed by photocuring, has flattening properties, and has high heat resistance after irradiation with light. A photocurable composition for coating a stepped substrate, the photocurable composition containing a polymer containing a unit structure of Formula (1): wherein A1, A2, and A3 are each independently an aromatic C6-100 ring optionally containing a heteroatom or a hydrocarbon group containing an aromatic C6-100 ring optionally containing a heteroatom, B1, B2, and B3 are each independently Formula (2): wherein R1 is a C1-10 alkylene group, a C1-10 alkenylene group, a C1-10 alkynylene group, a C6-40 arylene group, an oxygen atom, a carbonyl group, a sulfur atom, —C(O)—O—, —C(O)—NRa—, —NRb—, or a group including a combination thereof, R2 is a hydrogen atom or a C1-10 alkyl group.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 22, 2020
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Hikaru Tokunaga, Takafumi Endo, Keisuke Hashimoto, Rikimaru Sakamoto
  • Patent number: 10840097
    Abstract: In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yi-Nien Su
  • Patent number: 10818598
    Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Wang, Chung-Chi Ko, Po-Cheng Shih
  • Patent number: 10796947
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jack Liu, Wei-Cheng Wu, Charles Chew-Yuen Young, Sing-Kai Huang
  • Patent number: 10787744
    Abstract: The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. In other embodiments, the etching rate is increased by removing residual species bound to and/or adsorbed onto the surface.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 29, 2020
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Steven McClellan George, Nicholas Ray Johnson, Jaime Willadean Dumont, Amy Elizabeth Marquardt, Younghee Lee, David Richard Zywotko, Aziz Abdulagatov
  • Patent number: 10777559
    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
  • Patent number: 10748768
    Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • Patent number: 10741392
    Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Teng-Chun Tsai
  • Patent number: 10741391
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary, and the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. The method also includes exposing a portion of the resist layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process. The method further includes etching a portion of the resist layer to form a patterned resist layer and patterning the material layer by using the patterned resist layer as a mask. The method also includes removing the patterned resist layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang