Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The method includes providing a substrate, forming a first material layer on the substrate, forming a second material layer on the first material layer and forming a first PR layer on the second material layer. The method includes exposing a portion of the first PR layer to a first radiation beam and forming a second PR layer on the first PR layer. The method includes exposing a portion of the second PR layer to a second radiation beam and developing the first PR layer and the second PR layer to form a patterned first PR layer and a patterned second PR layer. The method includes etching a portion of the first material layer and the second material layer by using the patterned first PR layer and the patterned second PR layer as a mask.

Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

Abstract: In a patterning method according to the present embodiment, a guide pattern is formed on a processing target film. The guide pattern is configured by concave portions and convex portions extending in a predetermined direction. A block copolymer layer is formed on the guide pattern. The block copolymer layer contains at least two block chains. A layer of microphase-separated structures is formed on the concave portions and the convex portions, respectively, by microphase-separating the block copolymer layer. The processing target film is formed into predetermined patterns by selectively removing the processing target film. At least a part of the block copolymer layer is used as a mask.

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract: An article includes a substrate; and a coating disposed on the substrate that includes a microporous layer; a gradient in a density of a volume of the microporous layer, and a plurality of dendritic veins that are anisotropically disposed in the coating. A process for forming a coating includes disposing an activating catalyst on a substrate; introducing an activatable etchant; introducing an etchant oxidizer, performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst, the oxidation-reduction reaction occurring in a liquid medium including the activatable etchant; and the etchant oxidizer, forming an etchant product comprising atoms from the substrate; removing a portion of the etchant product from the substrate; and forming a dendritic vein in the substrate to form the coating, the dendritic vein being anisotropically disposed in the coating.

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

Abstract: Techniques, systems, and apparatuses for performing carbon gap-fill in semiconductor wafers are provided. The techniques may include performing deposition-etching operations in a cyclic fashion to fill a gap feature with carbon. A plurality of such deposition-etching cycles may be performed, resulting in a localized build-up of carbon film on the top surface of the semiconductor wafer near the gap feature. An ashing operation may then be performed to preferentially remove the built-up material from the top surface of the semiconductor wafer. Further groups of deposition-etching cycles may then be performed, interspersed with further ashing cycles.

Abstract: A method of forming a pattern of a semiconductor device includes providing a substrate, forming a photoresist layer by coating a resist composition including an acid generator and a first resin, the first resin having an acid-labile group, exposing the photoresist layer, forming a photoresist pattern by negatively developing the photoresist layer using a developing solution including an organic solvent, coating a capping composition including a second resin and the organic solvent on the substrate having the photoresist pattern formed thereon, and attaching a capping layer on upper and side surfaces of the photoresist pattern, by baking the capping composition and developing the capping composition using the developing solution including the organic solvent.

Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

Abstract: In directed self-assembly (DSA) of a block copolymer (BCP), a patterned sublayer on a substrate serves as a guiding chemical prepattern on which BCPs form more uniform and/or denser patterns. A layer of a blend of a BCP and functional homopolymers, referred to as inks, is deposited on the patterned sublayer and annealed to change the initial chemical prepattern to a 1:1-like chemical pattern that is more favorable to DSA. After annealing, the inks selectively distribute into blocks by DSA, and part of the inks graft on the substrate underneath the blocks. The BCP blend layer is then rinsed away, leaving the grafted inks A second layer of BCP is then deposited and annealed as a second DSA step to form alternating lines of the BCP components. One of the BCP components is removed, leaving lines of the other BCP component as a mask for patterning the substrate.

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract: A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer.

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.

Abstract: A hard mask composition includes a solvent and an aromatic ring-containing compound represented by the following Chemical Formula 1:

Abstract: A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) is formed surrounding the exposed topography. Further to the method, the exposed template surfaces are chemically treated. In one embodiment, the surfaces are treated with a hydrogen-containing reducing chemistry to alter the surfaces to a less oxidized state. In another embodiment, the surfaces are coated with a first phase of a block copolymer (BCP) to render the surfaces more attractive to the first phase than prior to the coating. The template is then filled with the BCP to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.

Abstract: A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) surrounds the exposed topography. Further to the method, the template is filled with a block copolymer (BCP) to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.

Abstract: Embodiments of the present disclosure provide methods for patterning rectangular features with a sequence of lithography, atomic layer deposition (ALD) and etching. Embodiment of the present disclosure includes forming first line clusters along a first direction and second line clusters over the first line clusters in a direction traversing the first direction. The first and second line clusters both include core lines formed from a core material, spacers formed from first and second materials by ALD and etching. After formation of the first and second line clusters, rectangular openings can be formed by selectively etching one or two of the core material, the first material or the second material.

Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.

Abstract: The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns.

Abstract: Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

Abstract: There is provided a method of forming patterns for a semiconductor device. The method sequentially forming a first mask layer and a second mask layer on a substrate. The method also includes forming a second mask pattern layer by patterning the second mask layer. The method further includes forming a first mask pattern layer having a negative slope portion, by etching the first mask layer exposed through the second mask pattern layer. The method also includes forming a thin film layer on the substrate exposed through the first mask pattern layer.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

Abstract: A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer.

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract: A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two adjacent first mandrels and a second spacing is defined between the two adjacent second mandrels, the first spacing being wider than the second spacing; forming a cover layer to cover the first mandrels while exposing the second mandrels; etching the cover layer and the second mandrels; removing the cover layer; concurrently forming first spacers on the sides of the first mandrels and a second spacers on the sides of the second mandrels after removing the cover layer; and transferring a layout of the first and second spacers to the substrate so as to form fin-shaped structures.

Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.

Abstract: A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.

Abstract: Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.

Abstract: Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a resist and a layer to be etched on a substrate, forming a non-cured layer on the resist by supplying a metal compound containing Ru, forming a cured layer on a surface layer of the resist by using the non-cured layer, and etching the layer to be etched by reactive ion etching using the cured layer and the resist as a mask.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.

Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.

Abstract: There is provided an etching method which can form trenches or via holes having desired aspect ratios and shapes in a to-be-processed object made of silicon. The etching method includes: a hydrogen halide-containing gas-based etching step of etching a silicon substrate by introducing a hydrogen halide-containing gas into a vacuum chamber; a fluorine-containing gas-based etching step of etching the silicon substrate by introducing a fluorine-containing gas into the vacuum chamber; a protective film formation step forming a protective film on the silicon substrate by sputtering a solid material; and a protective film removal step of removing part of the protective film by applying radio frequency bias power to a substrate electrode. The fluorine-containing gas-based etching step, the protective film formation step, and the protective film removal step are repeatedly performed in this order.

Abstract: A carbazole polymer including a repeating unit represented by Formula 1 and having excellent one electron oxidation-state stability, wherein, in Formula 1, R1-R4 each independently represents an alkyl group having 1-60 carbon atoms, a haloalkyl group having 1-60 carbon atoms, or similar, Cz represents a divalent group including a carbazole skeleton represented by Formula 2, and Ar represents a divalent aromatic ring or similar; wherein, in Formula 2, R5 represents a hydrogen atom, an alkyl group having 1-60 carbon atoms, or similar, R6-R11 each independently represents a hydrogen atom, a halogen atom, or similar, and m represents an integer 1-10.

Abstract: A composition forms a resist underlayer film showing improved adhesiveness to a resist pattern. A resist underlayer film-forming composition for lithography, including: a polymer that has a structure of Formula (1a), Formula (1b), or Formula (2) below on an end of the polymer; and an organic solvent: (where R1 is a hydrogen atom or a methyl group; each of R2 and R3 is independently a hydrogen atom or an organic group such as a hydrocarbon group, etc., the hydrocarbon group optionally has at least one of a hydroxy group and a methylthio group as substituent(s); R4 is a hydrogen atom or a hydroxy group; Q1 is an arylene group; v is 0 or 1; y is an integer of 1 to 4; w is an integer of 1 to 4; x1 is 0 or 1; and x2 is an integer of 1 to 5).

Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract: A method for making a hollow-structure metal grating is provided. The method includes the following steps. First, a substrate is provided. Second, a metal layer is located on a surface of the substrate. Third, a patterned mask layer is formed on a surface of the metal layer. The patterned mask layer is made of a chemical amplified photoresist. Fourth, the surface of the metal layer exposed out of the patterned mask layer is plasma etched. Lastly, the patterned mask layer on the surface of the metal layer is dissolved.

Abstract: Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.

Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

Abstract: There is provided a composition for forming an EUV resist underlayer film which shows a good resit form. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (A) containing a hydrolyzed condensate of hydrolyzable silane (a); and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (B) containing a hydrolyzed condensate of hydrolyzable silane (a) and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. The polysiloxane (A) is preferably a co-hydrolyzed condensate of a tetraalkoxysilane, an alkyltrialkoxysilane and an aryltrialkoxysilane.

Abstract: A pattern forming method includes forming a coating film containing a hydrophilic first homopolymer having a first bonding group and a hydrophobic second homopolymer having a second bonding group capable of bonding with the first bonding group, forming a bond between the first and second bonding group to produce a block copolymer of the first and second homopolymners, and heating the coating film to microphase-separating the copolymer into a hydrophilic domain and a hydrophobic domain. The hydrophilic and hydrophobic domains are arranged alternately. The bond is broken, then selectively dissolving-removing either domain by a solvent to provide a polymer pattern of a remainder domain.

Abstract: Provided is an adhesion-promoting composition between a curable composition for imprints and a substrate, which excellent in adhesiveness and can control pattern failure. An adhesion-promoting composition used between a curable composition for imprints and a substrate, which comprises a compound having a molecular weight of 500 or larger and having a reactive group, and has a content of a compound, with a molecular weight of 200 or smaller, of more than 1% by mass and not more than 10% by mass of a total solid content.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern.

Abstract: The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.