Plural Coating Steps Patents (Class 438/703)
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Patent number: 8288284Abstract: To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer 1 into discrete semiconductor chips 1e by means of etching using plasma processing, there is adopted a method including printing a lyophobic liquid in an area on a rear surface 1b that is to be an objective of etching, thereby forming a lyophobic pattern made up of lyophobic films 3; supplying a low viscosity resin 4a and a high viscosity resin 4b, in this sequence, to the rear surface 1b on which the lyophobic pattern is formed, thereby forming a resin film 4 that is thicker than the lyophobic films 3 in an area where the lyophobic films 3 are not present; and curing the resin film 4, to thus form a mask 4* that covers an area except for the area to be etched.Type: GrantFiled: April 9, 2010Date of Patent: October 16, 2012Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Hiroshi Haji
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Publication number: 20120256299Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.Type: ApplicationFiled: April 6, 2011Publication date: October 11, 2012Inventors: Xiang HU, Richard S. WISE, Habib HICHRI, Catherine LABELLE
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Patent number: 8283253Abstract: A pattern forming method for forming a pattern serving as a mask, includes a process for forming a first pattern 105, a process for trimming a width of the first pattern 105, a process for forming a boundary layer 106 on a surface of the first pattern 105, a process for forming a second mask material layer 107 on a surface of the boundary layer 106, a process for removing a part of the second mask material layer 107 to expose top portions of the boundary layer 106, and a process for exposing the first pattern 105 and forming a second pattern having the second mask material layer 107 at a top portion thereof by etching the boundary layer 106.Type: GrantFiled: February 13, 2009Date of Patent: October 9, 2012Assignee: Tokyo Electron LimitedInventors: Hidetami Yaegashi, Satoru Shimura, Takashi Hayakawa
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Patent number: 8283254Abstract: There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF4 gas, a COS gas and an O2 gas into a processing chamber and etching the antireflection coating layer by the etching gas while using the resist film as a mask.Type: GrantFiled: December 23, 2010Date of Patent: October 9, 2012Assignee: Tokyo Electron LimitedInventor: Takahito Mukawa
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Publication number: 20120252185Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.Type: ApplicationFiled: May 14, 2012Publication date: October 4, 2012Inventors: Young-Ho LEE, Jae-Kwan PARK, Jae-Hwang SIM, Sang-Yong PARK
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Publication number: 20120252217Abstract: A resist underlayer film-forming composition includes (A) a polymer that includes a repeating unit shown by a formula (1), and has a polystyrene-reduced weight average molecular weight of 3000 to 10,000, and (B) a solvent, wherein R3 to R8 individually represent a group shown by the following formula (2) or the like, —O—R1?R2 ??(2) wherein R1 represents a single bond or the like, and R2 represents a hydrogen atom or the like.Type: ApplicationFiled: August 30, 2011Publication date: October 4, 2012Applicant: JSR CorporationInventors: Shin-ya MINEGISHI, Yushi MATSUMURA, Shinya NAKAFUJI, Kazuhiko KOMURA, Takanori NAKANO, Satoru MURAKAMI, Kyoyu YASUDA, Makoto SUGIURA
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Publication number: 20120252218Abstract: A biphenyl derivative having formula (1) is provided wherein Ar1 and Ar2 denote a benzene or naphthalene ring, and x and z each are 0 or 1. A material comprising the biphenyl derivative or a polymer comprising recurring units of the biphenyl derivative is spin coated and heat treated to form a resist bottom layer having improved properties, optimum values of n and k, step coverage, etch resistance, heat resistance, solvent resistance, and minimized outgassing.Type: ApplicationFiled: March 20, 2012Publication date: October 4, 2012Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Daisuke Kori, Takeshi Kinsho, Katsuya Takemura, Tsutomu Ogihara, Takeru Watanabe, Hiroyuki Urano
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Publication number: 20120252216Abstract: Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.Type: ApplicationFiled: March 30, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Stephen W. Bedell, Alexander Reznicek, Devendra K. Sadana
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Publication number: 20120244712Abstract: According to one embodiment, a stacked film including at least a silicon oxide film is formed by stacking a plurality of films formed of different materials and a hard mask pattern is formed on the stacked film. Then, a stacked film pattern of a predetermined shape is formed by performing anisotropic etching on the stacked film by using the hard mask pattern as an etching mask and the hard mask pattern is removed. The hard mask pattern is formed by stacking at least one first hard mask layer and at least one second hard mask layer. The first hard mask layer is formed of a material having a higher removability in wet etching than the second hard mask layer. The first hard mask layer is arranged immediately above the stacked film.Type: ApplicationFiled: November 18, 2011Publication date: September 27, 2012Inventors: Shuichi TSUBATA, Hirotaka Ogihara
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Publication number: 20120244711Abstract: An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Applicant: International Business Machines CorporationInventors: Yunpeng Yin, John C. Arnold, Matthew E. Colburn, Sean D. Burns
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Publication number: 20120244714Abstract: An exposure mask includes: an insulative substrate; a light reflecting film provided on the substrate; a light absorbing film provided on the light reflecting film and forming a pattern in a center region on the substrate; and an interconnect provided on the substrate, the light reflecting film and the light absorbing film not being provided in a frame-shaped region surrounding the center region, and the interconnect being placed so that a portion of a laminated film composed of the light reflecting film and the light absorbing film located inside the frame-shaped region is electrically connected to a portion of the laminated film located outside the frame-shaped region.Type: ApplicationFiled: June 8, 2012Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Masamitsu Itoh
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Publication number: 20120244713Abstract: A method for fabricating a semiconductor device, comprising forming a first photoresist pattern having a hole on a first layer, forming a surface curing layer in the hole and curing the first photoresist pattern on an inner sidewall of the hole to form a first curing pattern, removing the surface curing layer, forming a second photoresist pattern in the hole and curing the second photoresist pattern that contacts with the first curing pattern to form a second curing pattern, removing the first and second photoresist patterns, and etching the first layer using the first and second curing patterns as an etch barrier.Type: ApplicationFiled: December 23, 2011Publication date: September 27, 2012Inventor: Sung Koo LEE
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Patent number: 8273663Abstract: A method is provided for anisotropically etching semiconductor materials such as II-VI and III-V semiconductors. The method involves repeated cycles of plasma sputter etching of semiconductor material with a non-reactive gas through an etch mask, followed by passivation of the side walls by plasma polymerization using a polymer former. Using this procedure small pixels in down-converted light-emitting diode devices can be fabricated.Type: GrantFiled: November 5, 2010Date of Patent: September 25, 2012Assignee: 3M Innovative Properties CompanyInventors: Terry L. Smith, Jun-Ying Zhang
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Patent number: 8273665Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.Type: GrantFiled: August 20, 2009Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Charles T. Black, Kathryn Wilder Guarini
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Patent number: 8273662Abstract: A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed.Type: GrantFiled: October 15, 2010Date of Patent: September 25, 2012Assignee: Hynix Semiconductor Inc.Inventor: Hyung Kyu Kim
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Patent number: 8273661Abstract: Provided is a pattern forming method for forming a pattern serving as a mask, which includes: a process for forming a first pattern 105 made of a photoresist; a process for forming a boundary layer 106 at sidewall portions and top portions of the first pattern 105; a process for forming a second mask material layer 107 to cover a surface of the boundary layer 106; a process for removing a part of the second mask material layer 107 to expose top portions of the boundary layer 106; a process for forming a second pattern made of the second mask material layer 107 by etching and removing the boundary layer 106; and a trimming process for reducing a width of the first pattern 105 and a width of the second pattern to predetermined widths.Type: GrantFiled: February 13, 2009Date of Patent: September 25, 2012Assignee: Tokyo Electron LimitedInventors: Hidetami Yaegashi, Satoru Shimura
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Publication number: 20120235247Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.Type: ApplicationFiled: March 17, 2011Publication date: September 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ming Cai, Dechao Guo, Chung-hsun Lin, Chun-chen Yeh
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Publication number: 20120238099Abstract: According to one embodiment, a process target above a substrate is processed in order to produce a wiring pattern including dense wirings and sparse wirings. Next, a sacrificial film filled between wirings is formed in a region where the dense wirings are formed, and then an insulation film is formed above the substrate. A mask is formed such that a part of the region where the dense wirings are formed is exposed and a region where the sparse wirings are formed is exposed, and the insulation film is etched using the mask. Then, the sacrificial film is removed through a part of the region where the dense wirings are formed. Thereafter, an embedded insulation film is formed above the substrate to fill a gap between adjacent wirings in the region where the sparse wirings are formed.Type: ApplicationFiled: September 18, 2011Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi SHUNDO, Fumiki Aiso
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Publication number: 20120236369Abstract: A system for the long-term storage and high-speed retrieval of color images stored on semiconductor substrates. The images are stored on semiconductor substrates by utilizing semiconductor fabrication techniques to produce a plurality of images. A transparent thin-film dielectric varies in thickness to product a color palette.Type: ApplicationFiled: March 26, 2012Publication date: September 20, 2012Applicant: Nanoark CorporationInventor: Ajay Pasupuleti
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Patent number: 8268184Abstract: A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiNy) layer overlying silicon in a plasma etching system, and transferring a pattern to the silicon nitride layer using a plasma etch process, wherein the plasma etch process utilizes a process composition having as incipient ingredients a process gas containing C, H and F, and an additive gas including CO2. The method further includes: selecting an amount of the additive gas in the plasma etch process to achieve: (1) a silicon recess formed in the silicon having a depth less than 10 nanometers (nm), and (2) a sidewall profile in the pattern having an angular deviation from 90 degrees less than 2 degrees.Type: GrantFiled: June 29, 2010Date of Patent: September 18, 2012Assignee: Tokyo Electron LimitedInventors: Akiteru Ko, Christopher Cole
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Publication number: 20120228743Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.Type: ApplicationFiled: May 24, 2012Publication date: September 13, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: O Seo Park, Wai-Kin Li
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Publication number: 20120225560Abstract: The disclosure relates to a method for etching a target layer, comprising: depositing a hard mask layer onto a target layer and onto the hard mask layer, a first photosensitive layer, exposing the first photosensitive layer through a first mask to transfer first patterns into the photosensitive layer, transferring the first patterns into the hard mask layer, depositing onto the hard mask layer etched a second photosensitive layer, exposing the second photosensitive layer through a second mask to transfer second patterns into the second photosensitive layer, transferring the second patterns into the hard mask layer by etching this layer, and transferring the first and second patterns into the target layer through the hard mask, the second patterns forming lines, and the first patterns forming trenches cutting the lines in the hard mask.Type: ApplicationFiled: March 2, 2012Publication date: September 6, 2012Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Pascal Gouraud, Bertrand Le-Gratiet
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Publication number: 20120220132Abstract: A semiconductor device manufacturing method includes: forming a core layer, an anti-reflection film and a photoresist layer on a layer to be etched of a substrate; trimming first line patterns of the photoresist layer; forming a first film on the first line patterns; removing the first film such that the first film is left in sidewall portions of the first line patterns of the photoresist layer; removing the photoresist layer; producing the core layer into second line patterns by etching the anti-reflection film and the core layer; forming a second film on the core layer produced into the second line patterns; removing the second film such that the second film is left in sidewall portions of the second line patterns of the core layer; and producing the layer to be etched into third line patterns by etching the layer to be etched.Type: ApplicationFiled: February 23, 2012Publication date: August 30, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Kenichi OYAMA, Shohei YAMAUCHI, Hidetami YAEGASHI
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Publication number: 20120220133Abstract: A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.Type: ApplicationFiled: April 16, 2012Publication date: August 30, 2012Applicant: Texas Instruments IncorporatedInventors: Thomas J. Aton, Donald Plumton
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Publication number: 20120220091Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.Type: ApplicationFiled: March 12, 2012Publication date: August 30, 2012Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Patent number: 8252692Abstract: A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer.Type: GrantFiled: June 27, 2011Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Inohara
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Patent number: 8252690Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.Type: GrantFiled: February 14, 2008Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Lin Su, Cheng-Lin Huang, Shing-Chyang Pan, Ching-Hua Hsieh
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Patent number: 8247330Abstract: A micropattern is joined to a substrate (W1) by: a first group of covering step and micropattern forming step by etching in a transfer step; and a second group of covering step and micropattern forming step by etching in the transfer step.Type: GrantFiled: March 6, 2008Date of Patent: August 21, 2012Assignee: Toshiba Kikai Kabushiki KaishaInventors: Hiroshi Goto, Hiroshi Okuyama, Mitsunori Kokubo, Kentaro Ishibashi
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Patent number: 8247305Abstract: A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth.Type: GrantFiled: December 3, 2010Date of Patent: August 21, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Kuo-Chang Liao, Weijun Song, Dang Quan Liao
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Publication number: 20120205750Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.Type: ApplicationFiled: September 15, 2011Publication date: August 16, 2012Inventor: Gaku SUDO
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Publication number: 20120208368Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.Type: ApplicationFiled: February 25, 2011Publication date: August 16, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takeyoshi Masuda, Keiji Wada, Satomi Itoh, Toru Hiyoshi
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Publication number: 20120208356Abstract: Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III, Qiqing C. Ouyang
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Publication number: 20120208367Abstract: A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using CxHy gas to perform the primary thermal treatment; performing a secondary thermal treatment on the substrate on which the carbon hard mask layer is deposited; and performing an oxygen treatment on the carbon hard mask layer.Type: ApplicationFiled: June 15, 2011Publication date: August 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Tai Ho KIM
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Patent number: 8242029Abstract: An atomic layer deposition-deposited silicon dioxide/metal oxide-nanolaminate, comprising at least one layer of silicon dioxide and at least one layer of a metal oxide, and having a wet etch rate in an etchant, said wet etch rate being either greater or smaller than both a wet etch rate of a film of silicon dioxide and a wet etch rate of a film of said metal oxide in said etchant. Also provided is a method for manufacturing the same.Type: GrantFiled: November 23, 2009Date of Patent: August 14, 2012Assignee: ASM International N.V.Inventors: Peter Zagwijn, Hyung-Sang Park, Stijn De Vusser
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Patent number: 8242021Abstract: A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having a pad type overlapping a side of the spacer pattern, and etching an underlying layer, with the photoresist pattern and the spacer pattern as a mask, to form an isolated pattern. The method improves resolution and process margins to obtain a highly-integrated transistor.Type: GrantFiled: May 8, 2008Date of Patent: August 14, 2012Assignee: Hynix Semiconductor Inc.Inventor: Jae In Moon
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Publication number: 20120202350Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: Micron Technology, Inc.Inventors: Sanket Sant, Gurtej Sandhu, Neal R. Rueger
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Patent number: 8237167Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.Type: GrantFiled: January 25, 2012Date of Patent: August 7, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8236697Abstract: A method for manufacturing a semiconductor device which includes fine patterns having various critical dimensions (CDs) by adjusting a thickness of spacer used as an etching mask in Spacer Patterning Technology (SPT). The method for manufacturing a semiconductor device includes forming spacers at a different level over an etching target layer and etching the etching target layer exposed among the spacers.Type: GrantFiled: June 5, 2008Date of Patent: August 7, 2012Assignee: Hynix Semiconductor Inc.Inventors: Dong Sook Chang, Hyoung Soon Yune
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Publication number: 20120193753Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.Type: ApplicationFiled: January 20, 2012Publication date: August 2, 2012Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Alexis Grabbe, Larry Flannery
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Publication number: 20120196444Abstract: A method of selective delivery of material to locations on a substrate using a continuous stream deposition device to deposit the material at selected locations on the substrate. This is achieved by creating a mask with an opening, locating the mask over the substrate and depositing the material through the opening onto the substrate. When locating the mask, over the substrate, a portion of the substrate is exposed through the opening and when the continuous stream deposition device is moved relative to the substrate and the mask, the continuous stream deposition device follows a path relative to the mask which intersects the opening. While the continuous stream deposition device moves, it discharges a continuous stream comprising the material to be delivered, to deposit the material through the mask at a discrete location on the substrate, at the intersection of the opening and the path of the continuous stream deposition device.Type: ApplicationFiled: August 6, 2010Publication date: August 2, 2012Applicant: New South Innovations PTY LimitedInventors: Alison Joan Lennon, Stuart Ross Wenham
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Publication number: 20120193763Abstract: To provide a method of manufacturing a semiconductor device with reduced generation of humps, a semiconductor device with reduced generation of humps, and a resist coater. An inactive liquid such as pure water is discharged at a predetermined pressure from a nozzle for discharging fluid for processing hump while spinning the semiconductor substrate to spray a region where a hump is generated. The hump is crushed by spraying the inactive liquid at a high pressure onto the hump, and the film thickness of the bottom-layer resist becomes almost uniform across the entire semiconductor substrate.Type: ApplicationFiled: January 11, 2012Publication date: August 2, 2012Inventor: Atsumi YAMAGUCHI
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Publication number: 20120196433Abstract: Provided is a manufacturing method for a semiconductor device having reduced leakage current and increased capacitance while improving interface characteristics. The manufacturing method includes forming a silicon oxide layer on a base layer including silicon, forming a silicon oxynitride layer by implanting nitrogen into the silicon oxide layer, and forming hydroxy groups on a surface of the silicon oxynitride layer while etching the silicon oxynitride layer.Type: ApplicationFiled: August 12, 2011Publication date: August 2, 2012Inventors: Jeong-Hee Han, Hyeok-Jun Son, Sang-Jin Hyun, Hoon-Joo Na
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Patent number: 8232210Abstract: A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor deviceType: GrantFiled: September 18, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Haining S. Yang
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Patent number: 8232164Abstract: Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.Type: GrantFiled: October 29, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
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Publication number: 20120187471Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.Type: ApplicationFiled: December 8, 2011Publication date: July 26, 2012Inventors: Han-Geun YU, Gyung-Jin MIN, Seong-Soo LEE, Suk-Ho JOO, Yoo-Chul KONG, Dae-Hyun JANG
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Publication number: 20120190205Abstract: Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.Type: ApplicationFiled: January 20, 2011Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Larry Clevenger, Timothy J. Dalton, Carl J. Radens
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Publication number: 20120190184Abstract: A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Inventors: Mark Fischer, T. Earl Allen, H. Montgomery Manning
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Publication number: 20120190206Abstract: A semiconductor device manufacturing method includes forming a first organic film pattern on a to-be-etched layer on a substrate, forming a silicon oxide film coating the first organic film pattern-etching the silicon oxide film to form a first mask pattern to cause the width of the line part of the first organic film pattern to have a fixed proportion with respect forming a second organic film pattern coating the silicon oxide film, forming a second mask pattern including the silicon oxide film on a side face part in an area coated by the second organic film pattern, and forming, in an area other than the area coated by the second organic film pattern, a third mask pattern in which an even number of the silicon oxide films are arranged.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: Tokyo Electron LimitedInventors: Koichi YATSUDA, Eiichi NISHIMURA
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Publication number: 20120187467Abstract: The present invention generally relates to a floating gate structure and method of forming the same. The floating gate structure has an upper portion which is wider than a middle portion of the floating gate structure. The upper portion may have a flared, rounded or bulbous shape instead of being pointed or having sharp corners. The reduction in pointed or sharp features of the upper portion reduces the electric field intensity near the upper portion, which decreases current leakage through the interpoly dielectric. The method includes forming a nitride cap on the upper surface of the floating gate structure to assist in shaping the floating gate. The floating gate is then formed using multiple selective oxidation and etching processes.Type: ApplicationFiled: July 28, 2011Publication date: July 26, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Matthew Scott Rogers, Po-Ta Chen, Jing Tang
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Patent number: 8227352Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer.Type: GrantFiled: April 25, 2011Date of Patent: July 24, 2012Assignee: Applied Materials, Inc.Inventors: Hang Yu, Deenesh Padhi, Man-Ping Cai, Naomi Yoshida, Li Yan Miao, Siu F. Cheng, Shahid Shaikh, Sohyun Park, Heung Lak Park, Bok Hoen Kim