Abstract: A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.

Abstract: Structure including nano-ribbons and method thereof. The structure include multiple nano-ribbons. Each of the multiple nano-ribbons corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 ?m. Each of the multiple nano-ribbons corresponds to a cross-sectional area associated with a ribbon thickness, and the ribbon thickness ranges from 5 nm to 500 nm. Each of the multiple nano-ribbons is separated from at least another nano-ribbon selected from the multiple nano-ribbons by a second distance ranging from 5 nm to 500 nm.

Abstract: There is provided a resist underlayer film forming composition for forming a resist underlayer film providing heat resistance properties and hardmask characteristics. A resist underlayer film forming composition for lithography, comprising: a polymer containing a unit structure of Formula (1): ?O—Ar1???Formula (1) (in Formula (1), Ar1 is a C6-50 arylene group or an organic group containing a heterocyclic group), a unit structure of Formula (2): ?O—Ar2—O—Ar3-T-Ar4???Formula (2) (in Formula (2), Ar2, Ar3, and Ar4 are individually a C6-50 arylene group or an organic group containing a heterocyclic group; and T is a carbonyl group or a sulfonyl group), or a combination of the unit structure of Formula (1) and the unit structure of Formula (2). The organic groups of Ar1 and Ar2 containing arylene group may be organic groups containing a fluorene structure.

Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.

Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.

Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Abstract: Described herein are compositions for forming an underlayer film for a solvent-developable resist. These compositions can include a hydrolyzable organosilane having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof and a solvent. The composition can form a resist underlayer film including, a hydrolyzable organosilane, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof, the silicon atom in the silane compound having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group in a ratio of 0.1 to 40% by mol based on the total amount of silicon atoms. Also described is a method for applying the composition onto a semiconductor substrate and baking the composition to form a resist underlayer film.

Abstract: A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface.

Abstract: A test structure is presented test structure on a substrate for monitoring a LER and/or LWR effect, said test structure comprising an array of features manufactured with amplified LER and/or LWR effect.

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.

Abstract: A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems.

Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: A method for fabricating a semiconductor device includes forming an etch-target layer over a substrate having a first region and a second region, stacking first and second hard mask layers over the etch-target layer, forming spacer patterns over the second hard mask layer of the first area, etching the second hard mask layer using the spacer patterns as an etch barrier, forming a hard mask pattern over the first hard mask layer of the second region, etching the first hard mask layer using the second hard mask layer of the first region and the hard mask pattern of the second region as etch barriers, removing the hard mask pattern of the second region, and etching the etch-target layer using the first and second hard mask layers of the first region and the first hard mask layer of the second region as etch barriers.

Abstract: According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.

Abstract: A fluorocarbon layer is formed on a silicon substrate that is a to-be-processed substrate (step A). A resist layer is formed on the thus-formed fluorocarbon layer (step B). Then, the resist layer is patterned into a predetermined shape by exposing the resist layer to light by means of a photoresist layer (step C). The fluorocarbon layer is etched using the resist layer, which has been patterned into a predetermined shape, as a mask (step D). Next, the resist layer served as a mask is removed (step E). After that, the silicon substrate is etched using the remained fluorocarbon layer as a mask (step F). Since the fluorocarbon layer by itself functions as an antireflective film and a harm mask, the reliability of processing can be improved, while reducing the cost.

Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Abstract: In an etching method of an embodiment, a film to be etched, which includes a first metallic element, is formed on a semiconductor substrate. A carbide layer, which includes a second metallic element, is formed on the film to be etched. The carbide layer is etched. The film to be etched is etched by using the carbide layer as a mask.

Abstract: A fabrication method of a minute pattern at least includes following steps. A first crystallizable material layer is formed on a base material. The first crystallizable material layer is patterned to form a plurality of first patterns on the base material. A distance between every two adjacent first patterns is greater than a width of each of the first patterns. A first treatment process is performed to crystallize the first patterns. A second crystallizable material layer is formed on the base material and covers the first patterns. The second crystallizable material layer is patterned to form a plurality of second patterns on the base material. Each of the second patterns is located between the first patterns adjacent thereto, respectively.

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone.

Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.

Abstract: Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.

Abstract: There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1): wherein each of R1, R2, R3, and R5 may be a hydrogen atom, R4 may be phenyl group or naphthyl group. A resist underlayer film forming composition comprising the polymer, and a resist underlayer film formed from the composition. A high refractive index film forming composition comprising the polymer, and a high refractive index film formed from the composition.

Abstract: The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient.

Abstract: A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate.

Abstract: In an embodiment, a method of fabricating an integrated orifice plate and cap structure includes forming an orifice bore on the front side of a product wafer, coating side walls of the orifice bore with a protective material, grinding the product wafer from its back side to a final thickness, forming a first hardmask for subsequent cavity formation, forming a second hardmask over the first hardmask for subsequent descender formation, forming a softmask over the second hardmask for subsequent convergent bore formation, etching a latent convergent bore using the softmask as an etch delineation feature, etching a descender using the second hardmask as an etch delineation feature, and anisotropic etching of convergent bore walls and cavities using the first hardmask as an etch delineation feature.

Abstract: Provided methods of etching and/or patterning films. Certain methods comprise exposing at least part of a film on a substrate, the film comprising one or more of HfO2, HfBxOy, ZrO2, ZrBxOy, to a plasma comprising BCl3 and argon to etch away said at least part of the film. Certain other methods relate to patterning substrates using said methods of etching films.

Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.

Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Abstract: The present invention provides a method of forming semiconductor devices using SMT. The method comprises providing a substrate; depositing an SiO2 buffer film and a low tensile stress SiN film on the substrate; applying photoresist over the low tensile stress SiN film and exposing the low tensile stress SiN film on the NMOS region through photoresist exposure; applying UV radiation to the exposed low tensile stress SiN film; removing some hydrogen in the low tensile stress SiN film on the NMOS region and removing photoresist over the PMOS region; performing a rapid thermal annealing process to induce tensile stress in the NMOS channel region; and removing the SiN film and the SiO2 buffer film. According to the method of forming semiconductor devices using SMT of the present invention, the conventional SMT is greatly simplified.

Abstract: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.

Abstract: A method for forming a semiconductor device is disclosed.

Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.

Abstract: A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.

Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.

Abstract: A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.

Abstract: Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.

Abstract: According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film.

Abstract: There is provided a method of making a semiconductor device utilizing a resist underlayer film forming composition comprising a silane compound containing an anion group, wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The anion group may be a carboxylic acid anion, a phenolate anion, a sulfonic acid anion, or a phosphonic acid anion. The hydrolyzable organosilane may be a compound of Formula (1): R1aR2bSi(R3)4?(a+b)(1).

Abstract: A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure.

Abstract: A novel process technique and mask design based on the optimized self-aligned triple patterning are invented for the semiconductor manufacturing. This invention pertains to methods of forming one and/or two dimensional features on a substrate having the feature density increased to three times of what is possible using optical lithography, and methods to release the overlay requirement when patterning the critical layers of semiconductor devices.

Abstract: Methods of patterning a material are disclosed. A first resist pattern is formed on a field. A protective layer is formed over the first resist pattern and at least a portion of the field. A second resist pattern is formed over a portion of the protective layer. A portion of a material to be patterned deposited adjacent to the first and second resist patterns is removed.

Abstract: A sidewall core that is slimmed is formed in a memory cell array area by patterning a polysilicon layer formed over a silicon nitride layer. A silicon oxide layer that at least covers side surfaces of the sidewall core and the polysilicon layer are sequentially formed and an embedded hard mask is formed by etching back the polysilicon layer. Thereafter, the silicon nitride layer within the memory cell array area that does not overlap with the sidewall core or the embedded hard mask and the silicon nitride layer within a peripheral circuit area that overlaps with a positioning monitor mark are exposed by etching the silicon oxide layer, and then the silicon nitride layer that is to be etched is patterned.

Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

Abstract: A method for patterning a multi-layer film in a semiconductor device is provided. The semiconductor device comprises a substrate and a multi-layer film on the substrate. The multi-layer film comprises N conductive layers and N dielectric layers alternatingly stacked, and 2N contact plugs. The Nth dielectric layer is formed at the top of the multi-layer film. The distances between the centers of each adjacent contact plugs are the same.

Abstract: A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer.

Abstract: A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.