Abstract: The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively.

Abstract: A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer.

Abstract: A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.

Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.

Abstract: A method of forming a semiconductor device can be provided by forming a mask pattern including non-metallic first spaced-apart portions that extend in a first direction on a lower target layer and non-metallic second spaced-apart portions that extend in a second direction on the lower target layer to cross-over the non-metallic first spaced-apart portions at locations. The lower target layer can be etched using the mask pattern.

Abstract: A substrate is successively provided with a support, an electrically insulating layer, and a semi-conductor material layer. A first protective mask completely covers a second area of the semi-conductor material layer and leaves a first area of the semi-conductor material layer uncovered. A second etching mask partially covers the first area and at least partially covers the second area, so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask so as to form a third etching mask. The semi-conductor material layer is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area, the first etching mask protecting the second area.

Abstract: A composition for forming a lithographic resist underlayer film, including, as a silane, a hydrolyzable organosilane, a hydrolysate thereof, or a hydrolytic condensate thereof, wherein the silane includes a hydrolyzable organosilane of Formula (1) below: [(R1)aSi(R2)(3-a)]b(R3)??Formula (1) [where R3 is a group of Formula (2), (3), or (4): (in Formulae (2), (3), and (4), at least one from among R4, R5, and R6 is a group bonded to a silicon atom directly or through a linking group.), R1 is an alkyl group, an aryl group, an aralkyl group, an alkyl halide group, an aryl halide group, an aralkyl halide group, an alkenyl group, or an organic group having an epoxy group, an acryloyl group, a methacryloyl group, a mercapto group, an amino group, or a cyano group, or a combination thereof, R2 is an alkoxy group, an acyloxy group, or a halogen atom].

Abstract: The invention provides an organic film composition comprises (A) a heat-decomposable polymer, (B) an organic solvent, and (C) an aromatic ring containing resin, with the weight reduction rate of (A) the heat-decomposable polymer from 30° C. to 250° C. being 40% or more by mass. There can be provided an organic film composition having not only a high dry etching resistance but also an excellent filling-up or flattening characteristics.

Abstract: When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.

Abstract: A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating pattern of four second lines is formed elevationally over and crossing the repeating pattern of four first lines. First alternating of the four second lines are removed from being received over the first lines. After the first alternating of the four second lines have been removed, elevationally exposed portions of alternating of the four first lines are removed to the underlying substrate using a remaining second alternating of the four second lines as a mask. Additional embodiments are disclosed and contemplated.

Abstract: In a method of forming a pattern, a photoresist pattern is formed on a substrate including an etching target layer. A surface treatment is performed on the photoresist pattern to form a guide pattern having a higher heat-resistance than the photoresist pattern. A material layer including a block copolymer including at least two polymer blocks is coated on a portion of the substrate exposed by the guide pattern. A micro-phase separation is performed on the material layer to form a minute pattern layer including different polymer blocks arranged alternately. At least one polymer block is removed from the minute pattern layer to form a minute pattern mask. The etching target layer is etched by using the minute pattern mask to form a pattern. Minute patterns may be formed utilizing a less complex process that those employed during conventional processes of forming a minute pattern.

Abstract: When forming sophisticated circuit elements, such as transistors, capacitors and the like, using a combination of a conventional dielectric material and a high-k dielectric material, superior performance and reliability may be achieved by forming a hafnium oxide-based high-k dielectric material on a conventional dielectric layer with a preceding surface treatment, for instance using APM at room temperature. In this manner, sophisticated transistors of superior performance and with improved uniformity of threshold voltage characteristics may be obtained, while also premature failure due to dielectric breakdown, hot carrier injection and the like may be reduced.

Abstract: A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has an end portion in the contact area and a conductive layer is filled in the trench. A mask layer is formed covering the conductive layer in the contact area. The conductive layer is etched back using the mask layer as a mask.

Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Abstract: Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Abstract: A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence.

Abstract: A process to form a lens on a semiconductor material is disclosed. The process includes steps of: forming double layers of an intermediate layer on the semiconductor material and a mask layer made of hard-baked photoresist on the semiconductor substrate; the first transcribing the convex shape of the mask layer on the intermediate layer; and the second scribing the convex shape of the intermediate layer on the semiconductor material.

Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.

Abstract: Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF.

Abstract: A semiconductor device including contact holes and method for forming the same are provided. A dual-stress liner is formed on a substrate. A first, second and third dielectric layers are then formed over the dual-stress liner. The second dielectric layer has a top surface leveling with that of an overlapping portion of the dual-stress liner. The third dielectric layer is etched to form first openings to have the etching stop at the second dielectric layer and at the upper stress liner of the overlapping portion. The second dielectric layer, the first dielectric layer and the upper stress liner are etched along the first openings to form second openings having the etching stop at the lower stress liner of the overlapping portion and the dual-stress liner in other regions. The stress liners are etched to form contact holes.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a plurality of bodies isolated by a first trench, forming a buried bit line gap-filling a portion of the first trench, etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench, forming a passivation layer gap-filling a portion of the second trenches, forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer, and filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line.

Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane (5) on a substrate (3), and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion (7a) and a second back-volume portion (7b), the first back-volume portion (7a) being separated from the second back-volume portion (7b) by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion (7b) can be made greater than the cross-sectional area of the membrane (5), thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane (5). The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately.

Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.

Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

Abstract: One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers.

Abstract: A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post template can be removed after directing self-assembly and, therefore, is not incorporated into the final microdomain pattern. The sacrificial posts can be a material removable using a selective etchant that will not remove the material of the final pattern block(s). The sacrificial posts may be removable, at least in part, using a same etchant as for removing one of the blocks of the BCP, for example, a negative tone polymethylmethacrylate (PMMA) when a non-final pattern block of polystyrene is removed and polydimethylsiloxane (PDMS) remains on the substrate.

Abstract: A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate.

Abstract: Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices.

Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.

Abstract: A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.

Abstract: Self-aligned sextuple patterning (SASP) processes and mask design methods for the semiconductor manufacturing are invented. The inventions pertain to methods of forming one and/or two dimensional features on a substrate having the feature density increased to six times of what is possible using the standard optical lithographic technique; and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. Our inventions provide production-worthy methods for the semiconductor industry to continue device scaling beyond 15 nm (half pitch).

Abstract: A resist underlayer film forming composition for lithography includes: as a component (I), a fluorine-containing highly branched polymer obtained by polymerizing a monomer A having two or more radical polymerizable double bonds in the molecule thereof, a monomer B having a fluoroalkyl group and at least one radical polymerizable double bond in the molecule thereof, and a monomer D having a silicon atom-containing organic group and at least one radical polymerizable double bond in the molecule thereof, in the presence of a polymerization initiator C in a content of 5% by mole or more and 200% by mole or less, based on the total mole of the monomer A, the monomer B, and the monomer D; and as a component (II), a hydrolyzable silane compound, a hydrolysis product thereof, a hydrolysis-condensation product thereof, or a silicon-containing compound that is a combination of these compounds.

Abstract: A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions.

Abstract: According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.

Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.

Abstract: According to one embodiment, a pattern forming method is disclosed. A resist pattern having a top surface is formed pattern on a substrate. A coating film having a first thickness distribution is formed on the substrate. The coating film covers the resist pattern. The coating film is thinned to expose the top surface of the resist pattern. The first thickness distribution is changed into a second thickness distribution which is more uniform than the first thickness distribution. The resist pattern is removed without removing the coating film. A pattern is formed in the substrate by processing the substrate by using the coating film as a mask.

Abstract: Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.

Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.

Abstract: A resist underlayer film-forming composition includes (A) a polymer that includes a repeating unit shown by a formula (1), and has a polystyrene-reduced weight average molecular weight of 3000 to 10,000, and (B) a solvent, wherein R3 to R8 individually represent a group shown by the following formula (2) or the like, —O—R1?R2??(2) wherein R1 represents a single bond or the like, and R2 represents a hydrogen atom or the like.

Abstract: Lithography processes are provided. The lithography process includes installing a reticle masking (REMA) part having a REMA open region in a lithography apparatus, loading a reticle including at least one reticle chip region in which circuit patterns are disposed into the lithography apparatus, and sequentially exposing a first wafer field, which includes a first chip region corresponding to the reticle chip region, and a second wafer field, which includes a second chip region corresponding to the reticle chip region, of a wafer to rays using the reticle and the REMA part to transfer images of the circuit patterns onto the wafer. An edge boundary of the REMA open region transferred on the first wafer field is located on a scribe lane region between the first and second chip regions while the first wafer field is exposed. Methods of manufacturing a semiconductor device using the lithography process are also provided.

Abstract: Methods for removing particles from a wafer for photolithography. A method is provided including providing a semiconductor wafer; attaching a polyimide layer to a backside of the semiconductor wafer; and performing an etch on an active surface of the semiconductor wafer; wherein particles that impinge on the backside during the etch are captured by the polyimide layer. In another method, includes attaching a layer of polyimide film to a backside of a semiconductor wafer; dry etching a material on an active surface of the semiconductor wafer; depositing of an additional layer of material on the active surface of the semiconductor wafer; removing the layer of polyimide film from the backside of the semiconductor wafer; patterning the layer of material using an immersion photolithography process to expose a photoresist on the active surface of the wafer; and repeating the attaching, dry etching, depositing, removing and patterning steps.

Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Abstract: A method for processing a thin film micro device on a substrate includes: 1) depositing a carbon film on the substrate as a sacrificial layer; 2) photolithographically defining a first predetermined pattern in the carbon film; 3) etching an unwanted portion of the carbon film outside the first predetermined pattern; 4) depositing a structural film including a single or multiple layers of solid state materials; 5) photolithographically defining a second predetermined pattern in the structural film; 6) etching the discarded portion of the structural film outside the second predetermined pattern; 7) selectively removing the remaining portion of the sacrificial carbon film by using a selective etch process gas in a reactor chamber, so that the overlapped portion of the remaining structural element with the first predetermined pattern is suspended above an underneath cavity above the substrate.

Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer, forming a plurality of elongated protrusions in a third layer above the first and second layers, and forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. The method also includes forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.

Abstract: Provided is a method of forming a nanogap pattern of a biosensor. First, an oxide layer is formed on a substrate and a first nitride layer is formed on the oxide layer. The first nitride layer is partially etched to form a first nitride layer pattern having a first gap that gradually narrows from a top portion to a bottom portion thereof and exposes the oxide layer. A second nitride layer is formed along the first nitride layer and along sidewalls and a bottom surface of the first gap. The second nitride layer is etched to form a second nitride layer pattern having a second gap narrower than the first gap on the sidewalls of the first gap. The oxide layer is etched by using the second nitride layer pattern as an etching mask to form an oxide layer pattern having a third gap, and thus, the nanogap pattern is completed.

Abstract: Disclosed is an image sensor including a photo-sensing device, a color filter positioned on the photo-sensing device, a microlens positioned on the color filter, and an insulation layer positioned between the photo-sensing device and the color filter, and including a trench exposing the photo-sensing device and a filler filled in the trench. The filler has light transmittance of about 85% or more at a visible ray region, and a higher refractive index than the insulation layer. A method of manufacturing the image sensor is also provided.

Abstract: A method is provided for forming FinFETS with improved alignment features. Embodiments include forming on a Si substrate pillars of TEOS on poly-Si; conformally depositing a first TEOS liner over the entire substrate; etching the first TEOS liner and substrate through the pillars, forming first trenches; filling the first trenches and spaces between the pillars with an oxide; removing the TEOS from the pillars and the oxide therebetween; removing the poly-Si; conformally depositing a second TEOS liner over the entire Si substrate; etching the second TEOS liner and Si between the oxide, forming second trenches having a larger depth than the first trenches; filling the second trenches with oxide; removing the oxide and the first and second TEOS liners down to an upper surface of the Si substrate; and recessing the oxide below the upper surface of the Si substrate.