Abstract: Shorting of a copper line with an adjacent line in a semiconductor device during chemical mechanical polishing may be prevented and thus reliability of the semiconductor device may be improved, when the semiconductor device includes a substrate, an interlayer insulating layer formed on the substrate and having a dual trench, and a copper line formed to fill the dual trench, wherein the dual trench includes a first trench inclined at a first angle with respect to the substrate, and a second trench connected to the first trench and inclined at a second angle that is smaller than the first angle with respect to the substrate.

Abstract: A double processing technique for device manufacture includes performing a first patterning step to form apertures in a resist layer which apertures are filled before the first resist layer is stripped and replaced by a second resist layer to be used in the second exposure.

Abstract: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.

Abstract: An exposure apparatus for transferring patterns on a phase shift mask into a wafer according to the present invention comprises a light source, a polarized light illuminator that selectively passes through a TM mode polarized light of light from the light source to cause it to be incident onto the phase shift mask, a polarization mode translator that translates the TM mode polarized light passing through the phase shift mask into TE mode polarized light, and a lens system irradiating the TE mode polarized light from the polarization mode translator on the wafer.

Abstract: Methods are disclosed for providing reduced particle generating silicon carbide. The silicon carbide articles may be used as component parts in apparatus used to process semiconductor wafers. The reduced particle generation during semiconductor processing reduces contamination on semiconductor wafers thus increasing their yield.

Abstract: Provided is an insulation layer patterning method employing a flowable oxide, which does not use a photo-resist. Also, an insulation layer pattern and display devices including the insulation layer are disclosed.

Abstract: Disclosed is a method for manufacturing an array substrate utilizing a laser ablation process. With the laser ablation process, a photoresist layer is removed along with the transparent conductive layer therefrom, while maintaining other portions of the transparent conductive layer. Moreover, the laser ablation process of the invention does not need additional photo-mask, so the fabrication cost can be reduced.

Abstract: A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.

Abstract: Wirings each having a side face with a different angle, which is made accurately, in a desired portion over one mother glass substrate are provided without increasing the steps. With the use of a multi-tone mask, a photoresist layer is formed, which has a tapered shape in which the area of a cross section is reduced gradually in a direction away from one mother glass substrate. At the time of forming one wiring, one photomask is used and a metal film is selectively etched, whereby one wiring having a side face, the shape (specifically, an angle with respect to a principal plane of a substrate) of which is different depending on a place, is obtained.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: A method is described for the manufacture of structured flexible metallic patterns in which a metallic layer on a flexible substrate is structured using laser ablation. The flexible patterns manufactured in this fashion may be used as interposers (strap) for RFID tags or RFID antennas.

Abstract: A method for fabricating an optical identification element is provided, wherein a removable plate or substrate having photosensitive material fabricated thereon, one or more gratings are written on the photosensitive material, then lines are etched to create one or more separate optical identification elements. The one or more gratings may be written by exposing the photosensitive material to ultraviolet (UV) light. The lines may be etched to create the one or more separate optical identification elements by photolithography to define/create the same.

Abstract: A method of producing a patterned mirror on a transparent conductive substrate comprises the steps of; coating a layer of conductive material onto a substrate, coating a layer of metal onto the layer of conductive material, coating a layer of photoresist onto the layer of metal, curing the layer of photoresist, exposing a desired pattern of transparent conductors through a first mask onto the layer of photoresist, developing the photoresist and simultaneously etching the layer of the conductive material and the layer of metal, exposing a desired pattern of metal conductors through a second mask onto the remaining layer of photoresist, developing the photoresist and etching the layer of metal.

Abstract: The invention provides a method for producing a quartz glass jig for use in semiconductor industries, which enables increasing the surface layer cleanliness simply and surely at low cost; it also provides a quartz glass jig improved in surface layer cleanliness. The inventive means for resolution are a method comprising processing a quartz glass raw material into a desired shape by a treatment inclusive of fire working, annealing for stress removal, and cleaning treatment to obtain the final product, the method is characterized by that it comprises performing gas phase etching step and gas phase purification step on the surface layer of the quartz glass jig after applying the annealing treatment for stress removal but before the cleaning treatment, wherein the gas phase purification step is carried out continuously after the gas phase etching step.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first photoresist film pattern over a semiconductor substrate including an underlying layer, exposing the first photoresist film pattern to generate an acid from the first photoresist film pattern, bleaching the first photoresist film pattern, and forming a second photoresist film pattern between the first photoresist patterns.

Abstract: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test.

Abstract: A method of multilevel microfabrication processing is provided. The method includes providing a planar substrate that comprises one or more material layers. A first hardmask layer placed on top of the substrate is patterned into the lithographic pattern desired for the top lithographic layer. Subsequent hardmask layers are patterned until the number of hardmask layers equals the number of lithographic layers desired. The method includes etching into the substrate and stripping the top hardmask layer. Furthermore, the method includes alternating etching into the substrate and stripping the subsequent hardmask layers until the bottom hardmask layer is stripped.

Abstract: Atomic oxygen generated in oxygen stripping plasmas reacts with and damages low-k dielectric materials during stripping of dielectric post etch residues. While damage of low-k dielectric materials during stripping of dielectric post etch residues is lower with hydrogen stripping plasmas, hydrogen stripping plasmas exhibit lower strip rates. Inclusion of oxygen in a hydrogen stripping plasma improves both photoresist strip rate and uniformity, while maintaining a hydrogen to oxygen ratio avoids low-k dielectric material damage.

Abstract: A method of electrostatically chucking a wafer while removing heat from the wafer in a plasma reactor includes providing a polished generally continuous surface on a puck, placing the wafer on the polished surface of the puck and cooling the puck. A chucking voltage is applied to an electrode within the puck to electrostatically pull the wafer onto the surface of the puck with sufficient force to attain a selected heat transfer coefficient between contacting surfaces of the puck and wafer.

Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

Abstract: A method of dividing and separating a wafer having a plurality of devices formed on its front surface, which are separated by streets. The method includes applying a resist film coating to a portion of the back surface of the wafer other than an area corresponding to the streets, and plasma etching the area of the back surface corresponding to the streets to divide the wafer into a plurality of individual devices. The thickness of the resist film coating is adjusted in the coating operation to allow the resist film to be completely removed during the plasma etching.

Abstract: A method and apparatus is provided for using a plasma generated from a processing gas mixture including H2O to efficiently strip photoresist material without causing significant damage to exposed, underlying low k dielectric material. The method includes disposing the processing gas mixture including the H2O over the wafer. The processing gas mixture including the H2O is then transformed into a plasma. The plasma serves to remove the photoresist material from the substrate without adversely affecting the exposed low k dielectric material.

Abstract: A method is provided. The method includes forming a conductive layer on an inner surface of a substrate and providing a sacrificial layer over the conductive layer. The method includes forming a plurality of channels in the sacrificial layer and plating the sacrificial layer to substantially fill the plurality of channels with a plating material comprising conducting material. The method also includes etching the sacrificial layer to form a conducting structure having fins where conducting material remains separated by microchannels where the sacrificial layer is etched.

Abstract: A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers to form a multi-tiered structure in the photo-resist layers.

Abstract: This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.

Abstract: A method for patterning a low dielectric insulating layer of a semiconductor device improves adhesion between a photoresist and the low dielectric (Low-K) insulating layer by removing at least one hydroxyl group from a surface of the Low-K insulating layer with a beam. Reliability of the device is thereby improved. The method includes forming a Low-K insulating layer on a semiconductor substrate, irradiating the Low-K insulating layer with a beam to make the Low-K insulating layer hydrophobic, forming a photoresist pattern on the Low-K insulating layer, and ashing the photoresist pattern.

Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

Abstract: A preferred embodiment of the invention provides a method for forming an integrated circuit. The method comprises forming a resist layer on a substrate. Preferably, the photoresist layer comprises a photo acid generator (PAG). Embodiments include irradiating the resist through a mask to generate a photoacid in the resist, heating the resist at a first temperature, and then heating the resist at a second temperature. Heating at the first temperature evaporates water from the resist. Heating at the second temperature deprotects the resist.

Abstract: Systems and methods for reducing alteration of a specimen during by charged particle based and other measurements systems are provided. One system configured to reduce alteration of a specimen during analysis includes a vacuum chamber in which the specimen is disposed during the analysis and an element disposed within the vacuum chamber. A surface of the element is cooled such that molecules in the vacuum chamber are adsorbed onto the surface and cannot cause alteration of a characteristic of the specimen during the analysis. One system configured to analyze a specimen includes an analysis subsystem configured to analyze the specimen while the specimen is disposed in a vacuum chamber and an element disposed within the vacuum chamber. A surface of the element is cooled such that molecules in the vacuum chamber are adsorbed onto the surface and cannot cause alteration of a characteristic of the specimen during the analysis.

Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract: A method of manufacturing a semiconductor device, includes: forming a resin layer with a resin containing an aromatic compound on a surface, where an electrode is formed, of a semiconductor substrate, by avoiding at least part of the electrode; removing an oxide film from a surface of the electrode using Ar gas and carbonizing the surface of the resin layer to form a carbonized layer; forming wiring from the electrode to over the carbonized layer; and etching, after forming the wiring, the carbonized layer by O2 plasma using the wiring as a mask so as to remove the carbonized layer partially.

Abstract: The present invention relates to a neutral particle beam processing apparatus. More specifically, the present invention relates to a neutral particle beam processing apparatus comprising a plasma discharging space inside which processing gases are converted to plasma ions through a plasma discharge, a heavy metal plate which converts the plasma ions into neutral particles through collisions, a plasma limiter which prevents plasma ions and electrons from passing through and allows the neutral particles produced by collisions of the plasma ions with the heavy metal plate to pass through, and a treating housing inside which a substrate to be treated is located, wherein the plasma discharging space is sandwiched between the heavy metal plate and the plasma limiter.

Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one contact opening is associated with each contact. Stripping of the patterned layer of photoresist and related residues is performed. After stripping, the stop layer is removed from the contacts. In one feature, the stop layer is removed from the contacts by etching the stop layer using a plasma that is generated from a plasma gas input that includes hydrogen and essentially no oxygen. In another feature, the photoresist is stripped after the stop layer is removed. Stripping the patterned layer of photoresist and the related residues is performed, in this case, using a plasma that is formed predominantly including hydrogen without oxygen.

Abstract: Provided are example embodiments of the invention including a range of polymer structures suitable for incorporation in barrier compositions for use, for example, in immersion photolithography in combination with a suitable solvent or solvent system. These polymers exhibit a weight average molecular weight (Mw) of 5,000 to 200,000 daltons and may be generally represented by formula I: wherein the expressions (1+m+n)=1; 0.1?(1/(1+m+n))?0.7; 0.3?(m/(1+m+n))?0.9; and 0.0?(n/(1+m+n))?0.6 are satisfied; R1, R2 and R3 are C1 to C5 alkyl, C1 to C5 alkoxy and hydroxyl groups; and Z represents an alkene that includes at least one hydrophilic group. Barrier coating compositions will include an organic solvent or solvent system selected from C3 to C10 alcohol-based organic solvents, C4 to C12 alkane-based organic solvents and mixtures thereof.

Abstract: A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

Abstract: A method of manufacturing a field emission device (FED) using a photoresist for performing multi-patterning processes, whereby different structures can be multi-patterned using a single photoresist mask. The photoresist has a solubility to a solvent by post-exposure heat-treatment, and a complicated structure can be formed using the photoresist.

Abstract: A method of junction delineation of non-epitaxial wafers comprises the steps of preparing a sample of the wafer, staining the sample using a mixture of between one and three parts hydrofluoric acid to fifty parts nitric acid to twenty parts water, and scanning the sample with a scanning electron microscope.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is then subjected to a surface treatment that provides sufficient energy for the extra electrons caused by the ashing process to escape from the substrate, and the remaining photoresist and polymer are stripped with stripping solvents after the surface treatment.

Abstract: A wet etching apparatus and method to shorten processing time and to eliminate formation of unintended mask pattern are described. In the conventional art, after a mask pattern is formed, alien substances such as water mist or stain are left on the substrate. The alien substances act as an etching block in the wet etching process. This generates an unintended mask pattern. The present invention uses ultraviolet light to remove the alien substances prior to the etching process. When the alien substances are removed, the intended mask pattern is generated after the etching process. The wet etching device according to the present invention includes an ultraviolet cleaner and a conveyor to convey substrates to and from the ultraviolet cleaner. Spaces for the ultraviolet cleaner and the conveyor are created in the wet etching apparatus by reducing space for cassettes and reducing space required by the loader.

Abstract: The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract: A method for forming fine patterns of a semiconductor device includes forming hard mask patterns over an underlying layer. A first organic film is formed over the hard mask patterns. A second organic film is formed over the first organic film. The second organic film is planarized until the first organic film is exposed. An etch-back process is performed on the first organic film until the underlying layer is exposed. The first organic film and the second organic film are etched to form organic mask patterns including the first organic film and the second organic film. Each organic mask pattern is formed between adjacent hard mask patterns. The underlying layer is etched using the hard mask patterns and the organic mask patterns as an etching mask to form an underlying layer pattern.

Abstract: A method for moving resist stripper across the surface of a semiconductor substrate includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.

Abstract: A plasma etching apparatus includes: a chamber capable of reducing pressure; a substrate support provided inside the chamber to place a substrate; a first electrode which is arranged outside and in proximity to the chamber and to which high frequency power is applied to generate plasma of an etching gas in the chamber; and a second electrode comprising a plurality of separated electrodes which are arranged between the chamber and the first electrode and to each of which high frequency power is applied independently.