Abstract: An adjustable nanopore is fabricated by placing the surfaces of two planar substrates in contact, wherein each substrate contains a hole having sharp corners and edges. A corner is brought into proximity with an edge to define a triangular aperture of variable area. Ionic current in a liquid solution and through the aperture is monitored as the area of the aperture is adjusted by moving one planar substrate with respect to the other along two directional axes and a rotational axis. Piezoelectric positioners can provide subnanometer repeatability in the adjustment process. The invention is useful for characterizing, cleaving, and capturing molecules, molecular complexes, and supramolecular complexes which pass through the nanopore, and provides an improvement over previous devices in which the hole size of nanopores fabricated by etching and/or redeposition is fixed after fabrication.

Abstract: A method for fabricating a thin film transistor array and driving circuit comprising the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form P+ doped regions; patterning out source/drain terminals and the lower electrode of a storage capacitor; etching back the N+ thin film; patterning out a gate and the upper electrode of the storage capacitor and patterning a passivation layer and a conductive layer to form pixel electrodes and a wiring layout.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either dielectric or resist layers. According to one aspect of the invention, first and second resist layers are formed into a dual damascene structure. Copper is grown by plating from the copper seed layer to form copper features that fill the pattern gaps.

Abstract: A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

Abstract: A surface-micromachined rotatable member formed on a substrate and a method for manufacturing thereof are disclosed. The surface-micromachined rotatable member, which can be a gear or a rotary stage, has a central hub, and an annulus connected to the central hub by an overarching bridge. The hub includes a stationary axle support attached to the substrate and surrounding an axle. The axle is retained within the axle support with an air-gap spacing therebetween of generally 0.3 &mgr;m or less. The rotatable member can be formed by alternately depositing and patterning layers of a semiconductor (e.g. polysilicon or a silicon-germanium alloy) and a sacrificial material and then removing the sacrificial material, at least in part. The present invention has applications for forming micromechanical or microelectromechanical devices requiring lower actuation forces, and providing improved reliability.

Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: A method for fabricating a pad oxide layer in integrate circuits is described. A zero oxide layer is formed on a silicon wafer, wherein a thickness of the zero oxide layer is slightly greater than the desired thickness of a pad oxide layer that is required in a subsequent process. Photolithography and etching are further conducted to pattern the zero oxide layer and the silicon wafer to form a plurality of alignment marks on the silicon wafer. A cleaning process is further conducted to remove the photoresist layer and a portion of the zero oxide layer to prevent photoresist debris remaining and to control the thickness of the zero oxide layer such that the thickness of the zero oxide layer is same as the desired thickness of the pad oxide layer that is needed in the subsequent process.

Abstract: The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

Abstract: The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

Abstract: A method for controlling etch bias of carbon doped oxide films comprising performing the etch in a cyclic two step process i.e., a carbon doped oxide (CDO) removal process, said CDO removal process comprises a first gas to etch a trench in the CDO layer. The CDO removal process is followed by a polymer deposition process. The polymer deposition process comprises introducing a second gas in the reactor to deposit a polymer in the trench of the CDO layer. The first gas comprises a first molecule having a first ratio of carbon atoms to fluorine atoms, and the second gas comprises a second molecule having a second ratio of carbon atoms to fluorine atoms, such that the second ratio of carbon atoms to fluorine atoms is greater than the first ratio of carbon atoms to fluorine atoms. The above process may be repeated to etch the final structure.

Abstract: An electrical standoff has a dielectric substrate with opposing horizontal surfaces and at least two opposing vertical end walls. A transmission structure having planar elements is formed on the at least one of the horizontal surfaces with the planar elements of the transmission structure extending to the two opposing vertical end walls. The electrical standoff is formed from a wafer of dielectric material having at least a first transmission structure formed thereon. A low temperature water soluble wax is applied over the transmission structure and a protective covering is placed over the water soluble wax. The wafer is sawn to form the electrical standoff with the electrical standoff having two opposing sawn vertical end walls intersecting the planar elements of the transmission structure. The protective covering and the low temperature water soluble wax are removed from the electrical standoff.

Abstract: Contact holes (36a, 36b) are formed by means of plasma etching, such that the contact holes are formed from the top surface of a silicon oxide insulating film (31) down to a wiring layer (33a) at a deep position and a wiring layer (33b) at a shallow position, respectively, which are embedded in the insulating film (31). A process gas containing C4F8, CO, and Ar is used, while the process pressure is set to be from 30 to 60 mTorr, and the partial pressure of the C4F8 gas is set to be from 0.07 to 0.35 mTorr. Under these conditions, the process gas is turned into plasma, and the insulating film (31) is etched with the plasma to form the contact holes (36a, 36b).

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.

Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.

Abstract: A method of fabricating an ultra narrow gate electrode for an FET and/or a conductive line in an integrated circuit by first forming a mask for the gate electrode and/or conductive line on a semiconductor substrate of minimal width dimension by optical lithography and reducing the width of the mask by laser irradiation with the beam at an angle and the semiconductor substrate rotating at a high rate of speed.

Abstract: In accordance with the present invention, a method is provided for shrinking critical dimension in semiconductor processes. This method comprises a step of performing an over-exposure process to a photosensitive layer to form a patterned photosensitive layer on a substrate by using a patterned reticle. Due to the unexposed region of the photosensitive layer being diminished by over-exposure the critical dimension is shrunk. Then, a sacrificial layer is applied for the purpose of pattern reverse-transferring. Next, the patterned photosensitive layer is removed such that the pattern is transferred to the sacrificial layer with a shrunk critical dimension. In cooperation of the present exposure technology with the present invention, the shrinkage of a critical dimension is accomplished, for example, using an I-line exposure light source in a critical dimension of 0.25 &mgr;m process, or using a deep UV (ultraviolet) exposure light source in a critical dimension of 0.13 &mgr;m process.

Abstract: A method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region is provided. In the method, a contact pad is formed in the active metal contact region and the bit line contact region using a conductive plug. An etch stopper is formed on the upper sides of the conductive plug. A portion of a lower interlayer dielectric layer is etched so that the etch stopper protrudes above the lower interlayer dielectric layer. A bit line stack is formed in the bit line contact region. An etch stopper is formed in the active metal contact region. An upper interlayer dielectric layer is etched to expose the surfaces of the etch stopper and bit line capping layer pattern of the bit line stack. The exposed surfaces of the etch stopper and bit line capping layer pattern are etched to form a contact hole which exposes the conductive plug and a bit line conductive layer of the bit line stack. The contact hole is filled with a conductive layer.

Abstract: Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.

Abstract: Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

Abstract: Trench and stacked capacitors are commonly used in the construction of DRAMs utilized in electronic devices. Conventional methods of manufacture typically result in capacitor structures having relatively smooth sidewall profiles which are integrated into a capacitor structure. The present invention provides a novel method by which the capacitance density of both trench and stacked capacitors can be increased, without increasing the footprint or depth of the capacitor structure, by increasing the surface area of the sidewall profiles of the capacitor structures using an iterative etch process that comprises an isotropic plasma etching step to achieve an enlarged sidewall profile.

Abstract: A method of anisotropic etching of silicon with structures, preferably defined with an etching mask, by using a plasma, with a polymer being applied during a polymerization step to the lateral border of the structures defined by the etching mask, then being partially removed again during the following etching step and being redeposited in deeper side walls of the structure newly formed due to the etching reaction, and the etching is performed with an etching gas containing 3 to 40 vol % oxygen. In this way it is possible to prevent sulfur contamination in the exhaust gas area in high rate etching of silicon.

Abstract: First of all, a semiconductor substrate that has a gate dielectric layer thereon is provided. Then a polysilicon layer is formed on the gate dielectric layer. Next, a dielectric layer having a first thickness is formed on the polysilicon layer. Afterward, form and define a photoresist layer on the dielectric layer. The dielectric layer is then etched by way of using the photoresist layer as an etching mask and a mixing gas that comprises a C2F6 and a CH2F2 as an etchant until the polysilicon layer is over etched to consume a second thickness, so as to form a hard mask with a trapezoid profile, wherein the second thickness is about half of the first thickness. After removing the photoresist layer, the polysilicon layer is etched by way of using the hard mask as an etching mask to form a poly-gate.

Abstract: A method is provided herein for trim etching a resist line in a plasma etch apparatus. The method provides a reduced rate of vertical direction etching of the resist, and an increased rate of horizontal direction etching of the resist, by applying a lower biasing power to the plasma etch apparatus that is conventionally used. The resulting resist has an increased height in relation to its width which adds to the structural integrity of the resist line and significantly reduces problems of discontinuity in the resist line.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer. The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer.

Abstract: Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract: A method of anisotropic etching of silicon with structures, preferably defined with an etching mask, by using a plasma, with a polymer being applied during a polymerization step to the lateral border of the structures defined by the etching mask, then being partially removed again during the following etching step and being redeposited in deeper side walls of the structure newly formed due to the etching reaction, and the etching is performed with an etching gas containing 3 to 40 vol % oxygen. In this way it is possible to prevent sulfur contamination in the exhaust gas area in high rate etching of silicon.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.

Abstract: A method is disclosed for forming a micromechanical device. The method includes fully or partially forming one or more micromechanical structures multiple times on a first substrate. A second substrate is bonded onto the first substrate so as to cover the multiple areas each having one or more micromechanical structures, so as to form a substrate assembly. The substrate assembly is then separated into individual dies, each die having the one or more micromechanical structures held on a portion of the first substrate, with a portion of the second substrate bonded to the first substrate portion. Finally, the second substrate portion is removed from each die to expose the one or more micromechanical structures on the first substrate portion.

Abstract: A microstructure comprising a spider-like membrane and a wedge beneath is designed and fabricated on the silicon substrate using common IC techniques and silicon anisotropic etching process. The wedge beneath can contact the membrane to provide mechanical support, or form a narrow gap with the membrane to realize several device functions. The microstructures are adaptable for many applications and can be easily implemented into standard CMOS chips.

Abstract: A method of forming a patterned photoresist layer is performed in a nitrogen gas atmosphere. The method includes the steps of sequentially forming a layer to be etched and first photoresist layer on a semiconductor substrate, and sequentially forming an intermediate barrier layer and second photoresist layer on the first photoresist layer. The second photoresist layer is patterned, and the intermediate barrier layer is etched using the patterned second photoresist layer as a mask. The first photoresist layer is etched in a nitrogen gas atmosphere, and the first photoresist layer is etched using the patterned intermediate barrier layer as a mask.

Abstract: A surface-micromachined rotatable member formed on a substrate and a method for manufacturing thereof are disclosed. The surface-micromachined rotatable member, which can be a gear or a rotary stage, has a central hub, and an annulus connected to the central hub by an overarching bridge. The hub includes a stationary axle support attached to the substrate and surrounding an axle. The axle is retained within the axle support with an air-gap spacing therebetween of generally 0.3 &mgr;m or less. The rotatable member can be formed by alternately depositing and patterning layers of a semiconductor (e.g. polysilicon or a silicon-germanium alloy) and a sacrificial material and then removing the sacrificial material, at least in part. The present invention has applications for forming micromechanical or microelectromechanical devices requiring lower actuation forces, and providing improved reliability.

Abstract: A method of preparing a TEM sample. A focused ion beam is used to deposit a mask on the material to be sampled. Reactive ion etching removes material not protected by the mask, leaving a wall thin enough to be imaged by TEM.

Abstract: A method for fabricating MEMS wherein a structural member is released without using a sacrificial layer. In one embodiment, the method comprises forming a buried hydrogen-rich layer in a semiconductor substrate, defining a release structure in the semiconductor substrate above the buried hydrogen-rich layer, and separating at least a portion of the release structure from the semiconductor substrate by cleaving the semiconductor substrate at the buried hydrogen-rich layer. The method can be used to fabricate hybrid devices wherein a MEMS device and a semiconductor device are formed on the same chip.

Abstract: A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Abstract: The high Q inductor process for reducing substrate interaction of integrated inductors includes etching away some of the silicon substrate after the inductor has been formed on the substrate. A first etch process is performed to form an opening in the center of the inductor exposing the silicon substrate. A second etch process is performed to etch the exposed silicon substrate to form a trench in the silicon substrate. A third etch process is performed to etch the trench into an inverted pyramidal cavity within the substrate and extending beneath the inductor. The pyramidal cavity is then filled with a solution, such as spin-on-glass thereby providing mechanical support for the inductor.

Abstract: A method of fabricating a node contact opening is described. A dielectric layer is formed on a substrate. A first conductive layer is formed on the dielectric layer. The first conductive layer is etched to form a trapezoidally cross-sectioned opening exposing a portion of the dielectric layer. The dielectric layer exposed by the trapezoidally cross-sectioned opening is etched to form a node contact opening in the dielectric layer exposing a part the substrate. A second conductive layer is formed to fill the node contact opening and in contact with the conductive layer.

Abstract: A method for anisotropic plasma etching of laterally defined patterns in a silicon substrate is described. Protective layers made of at least one silicon compound with a second reaction partner that is entirely compatible with the chemistry of the etching process are deposited before and/or during plasma etching onto the sidewalls of the laterally defined patterns.

Abstract: A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF4) with the inclusion of chlorine (Cl2) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.

Abstract: A method is proposed for anisotropic etching of micro- and nanofeatures in silicon substrates using independently controlled etching steps and polymer deposition steps which succeed one another alternatingly, the quantity of polymer deposited decreasing in the course of the polymer deposition steps, thus preventing any underetching of the micro- and nanofeatures.

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid.

Abstract: A method is provided for directly measuring the source/drain resistance of a metal oxide semiconductor (MOS) device. Embodiments include partially deconstructing a typical MOS device by removing its gate and gate oxide from the substrate, as by etching, while preserving its gate sidewall spacer (typically silicon nitride). A sacrificial oxide spacer is formed on the nitride spacer, as by anisotropically etching a deposited oxide layer, and the area surrounding the sacrificial oxide spacer is filled with a layer of nitride. The sacrificial oxide spacer is then selectively etched to expose a portion of the main surface of the substrate and leave the nitride spacer and layer, thus creating a location near the edge of a source/drain region for a metal contact to be formed, as by chemical vapor deposition (CVD).

Abstract: There is provided a method for forming a metal line of a semiconductor device, in which a (TiAl)N layer having a lower reflectivity and permeability is formed as anti-reflective coating layer. Since the (TiAl)N anti-reflective coating layer effectively prevent a metal line from reflecting in lightening process using a shorter wavelength such as DUV, a fine metal line can be formed exactly.

Abstract: A method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. A first dielectric layer is formed on a pad layer for a square oxide structure or a polysilicon layer overlying a gate oxide layer for a floating gate, and a second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned to form parallel openings in a first direction using a first photosensitive mask. A second photosensitive mask, having a plurality of parallel openings in a second direction perpendicular to the first direction is formed over the second dielectric layer and the first dielectric layer. The first dielectric layer is etched through square openings where the openings in the second photosensitive mask and the openings in the second dielectric layer intersect, thereby forming square openings in the first dielectric layer. The second photosensitive mask and the second dielectric layer are removed.

Abstract: The present disclosure pertains to our discovery that a particular sequence of processing steps will lead to the formation of a rounded top corner on a trench formed in a semiconductor substrate.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: A method of fabricating semiconductor device. First, a masking layer having an opening pattern is formed on a material layer, and then a mask spacer is formed on the sidewall of the opening. The opening is filled with an insulating layer to cover the material layer exposed by the opening. The masking layer and the mask spacer are removed, allowing the remaining insulating layer to be a mask for defining a pattern of the material layer. Then, the material layer not covered by the insulating layer is removed. The insulating layer is removed again to expose the patterned material layer.

Abstract: A method for determining the crystal orientation of a wafer using anisotropic etching in which an etching mask having mask openings such as circle scale marks arranged one beside the other is applied in relation to a preexisting marking of the wafer. Mask openings are configured in a double-T shape and are arranged one beside the other so that their first, transversely extending segments and the second transversely extending segments are situated at a predetermined distance apart and the areas connecting the segments are situated equidistant. The crystal orientation is determined with the distance of the two particular adjacent mask openings, the intervening space of which is least undercut, from the preexisting marking.