Abstract: A method for forming plugs using chemical-mechanical polishing, which includes providing a conductive layer having an inter-layer dielectric formed thereon; then, forming a contact hole in the inter-layer dielectric exposing portions of the conductive layer. Thereafter, a diffusion barrier layer and a glue layer are sequentially formed over the inter-layer dielectric and the exposed conductive layer. Next, a first metallic layer is deposited over the glue layer, and then etched back to form a residual first metallic layer. Subsequently, a second metallic layer is deposited over the glue layer and the residual first metallic layer. Finally, chemical-mechanical polishing is used to remove the second metallic layer above the inter-layer dielectric to form a metal plug. By depositing plug metal in stages, exposed cavities are no longer formed after a CMP operation is performed, thus avoiding the problem of CMP slurry getting inside a metal plug.

Abstract: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed "enhanced physical bombardment". Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber.

Abstract: A semiconductor device suitable for increasing operation speed and microminiaturization is provided. First and second impurity diffusion regions are formed sandwiching an element isolation insulation film. After a metal film is deposited all over a substrate, a heat treatment for silicidization is applied to form a metal silicide layer on the first and second impurity diffusion regions. The metal film not silicided is removed by etching with a predetermined region of the metal film on the two metal silicide layers and on the element isolation insulation film covered with a mask. The metal silicide layers on the first and second impurity diffusion regions are electrically connected by a metal interconnection layer that is not silicided and that extends on and in direct contact with the element isolation insulation film.

Abstract: Copper can be pattern etched in a manner which provides the desired feature dimension and integrity, at acceptable rates, and with selectivity over adjacent materials. To provide for feature integrity, the portion of the copper feature surface which has been etched to the desired dimensions and shape must be protected during the etching of adjacent feature surfaces. To avoid the trapping of reactive species interior of the etched copper surface, hydrogen is applied to that surface. Hydrogen is adsorbed on the copper exterior surface and may be absorbed into the exterior surface of the copper, so that it is available to react with species which would otherwise penetrate that exterior surface and react with the copper interior to that surface. Sufficient hydrogen must be applied to the exterior surface of the etched portion of the copper feature to prevent incident reactive species present due to etching of adjacent feature surfaces from penetrating the previously etched feature exterior surface.

Abstract: A method for etching a metal layer of a semiconductor device is provided. A metal layer formed on a substrate is etched using a hard mask and a mixed etching gas containing chlorine and oxygen in which the ratio of oxygen gas is preferably about 0.5-0.8. Under such conditions, a metal layer pattern of a fine profile is formed. Since the hard mask is thin, it is possible to prevent etch reactants generated in a process of etching the metal layer from being deposited on the side surface of the resultant formed of the metal layer pattern and the hard mask. As a result, no additional processing is required to remove the etch reactants from the side surfaces and the metal layer etching process is simplified.

Abstract: A method for etching a TiN layer of a wafer stack in a plasma processing chamber. The method includes the step of etching at least partially through the TiN layer using a first chemistry, which preferably includes a TiN etchant, a noble gas, and a polymer-forming chemical. In one embodiment, the TiN etchant is Cl.sub.2, the noble gas is argon, and the polymer-forming chemical is CHF.sub.3.

Abstract: Polystringers that cause NAND-type memory core cells to malfunction are removed. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. Next, the device is exposed to oxygen gas in a high temperature environment to oxidize the surface of the device, and in particular to remove the polystringers.

Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

Abstract: A method for etching selected portions of an aluminum-containing layer of a layer stack that is disposed on a substrate. The aluminum-containing layer is disposed below a photoresist mask having a pattern thereon. The method includes providing a plasma processing chamber and positioning the substrate having thereon the layer stack, including the aluminum containing layer and the photoresist mask, within the plasma processing chamber. The method further includes flowing an etchant source gas that comprises HCl, a chlorine-containing source gas, and an oxygen-containing source gas into the plasma processing chamber. The flow rate of the oxygen-containing source gas is less than about 20 percent of a total flow rate of the etchant source gas. There is also included striking a plasma out of the etchant source gas, wherein the plasma is employed to etch at least partially through the aluminum-containing layer.

Abstract: A dual damascene process can be used to form an interconnect. A first dielectric layer is formed on a semiconductor substrate having a device layer formed thereon. A stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the stop layer. A hard mask layer is formed and patterned on the second dielectric layer so that an opening is formed to expose the second dielectric layer therewithin. The second dielectric layer, the stop layer and a part of the first dielectric layer are etched within the opening by photolithography and etching, so that a contact window is formed. Using the hard mask layer as a hard mask, an etching is performed so that a metal trench penetrating through the second dielectric layer is formed, and the device layer within the contact window is exposed.

Abstract: A method for forming a semiconductor device contact plug in a contact hole without a plug cavity. The method forms a contact hole on a substrate, and then forms a barrier layer in the contact hole. Next, a contact plug is formed on the barrier layer in the contact hole. After the formation of the contact plug, a portion of the barrier layer is selectively removed using a gas mixture of a first gas and a second gas. The first gas etches the barrier layer, and the second gas forms a protective layer to prevent a cavity from forming.

Abstract: The novel process forms a first recess, such as a contact hole, within a first dielectric layer upon a semiconductor substrate. At least one diffusion barrier layer, selected from a group consisting of ceramics, metallics, and intermetallics, is formed within the first recess and at least partially conformably formed upon the first dielectric layer. A first electrically conductive layer is then formed within the recess over a said diffusion barrier layer. Preferably, the first electrically conductive layer is substantially composed of tungsten. The first electrically conductive layer is planarized above the recess thereby forming a top surface thereof. A second dielectric layer is formed over the first dielectric layer and said first electrically conductive layer. A second recess is formed in the second dielectric layer. The second recess extends from an upper surface of the second dielectric layer to the top surface of the first electrically conductive layer.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

Abstract: An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Abstract: A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer.

Abstract: In the preparation of semiconductor structures having multilevel copper conductive features which must be interconnected, it is frequently desired to remove portions of a copper layer deposited over a substrate. In particular, where lines and contacts are created by depositing a copper layer to fill trenches and vias present in a dielectric layer, it is desired to remove the portion of the copper layer which does not form the desired line or contact. The present invention provides a method of etching a copper layer (film) to remove the portion of the film which is not part of the desired conductive interconnect structure, while avoiding over etching of the structure and the formation of corrosive surface contaminants on the surface of the etched copper. The method of etching is referred to as the etchback process, since, in a typical fabrication process, the deposited copper layer is etched back to the upper or "field" surface of a substrate containing trenches and vias which are filled by the copper.

Abstract: A method of etching an opening having tapered wall in a layer of silicon carbide (SiC) includes forming a layer of a resist on the SiC layer. An opening having tapered wall is formed in the resist layer so as to expose a portion of the SiC layer. The exposed portion of the SiC layer is then exposed to a plasma of a gas containing carbon and fluorine to etch an opening through the SiC layer with the opening having tapered walls. If a layer of a glass is provided under the SiC layer, the plasma will also etch through the glass layer to provide an opening in the glass layer having tapered walls.

Abstract: A method of forming an interconnection line of a semiconductor device includes the steps of forming an insulating layer on a substrate, forming a contact hole in the insulating layer, forming a first conductive material layer in the contact hole so that a top surface level of the first conductive material layer is the same as or higher than a top surface level of the insulating layer and so that a portion of the first conductive material layer remains on the insulating layer, and forming a second conductive material layer on the first conductive material layer as the portion of the first conductive material layer remaining on the insulating layer is removed.

Abstract: Disclosed is a process for exposing a metal-containing surface feature on an integrated circuit wafer by laser ablation. According to the invention, a silicon dioxide passivation layer is provided upon the surface feature. The silicon dioxide layer is transparent to electromagnetic radiation having a specified wavelength, such that the electromagnetic radiation is directed through the silicon dioxide layer onto the underlying surface feature. A portion of the surface feature is ablated. Ablation of the surface feature causes removal of an overlying portion of the silicon dioxide layer, thereby exposing the surface feature. Laser ablation may further be performed on optional overlying layers of silicon nitride and polyimide.

Abstract: A method for forming a capacitor structure includes the steps of forming a conductive layer in a substrate, and forming a dielectric layer on the conductive layer opposite the substrate. An aluminum layer is formed on the dielectric layer, and this aluminum layer is patterned so that portions of the dielectric layer are exposed. The patterned aluminum layer is then oxidized to form an alumina masking layer. The alumina masking layer can then be used to selectively etch portions of the dielectric and conductive layers exposed thereby. Related systems are also disclosed.

Abstract: Methods of forming electrically conductive lines include the steps of forming a first electrically insulating layer (e.g., SiO.sub.2) on a face of a semiconductor substrate and then forming a layer of polycrystalline silicon (polysilicon) as a blanket layer on the first electrically insulating layer. A metal silicide layer (e.g., TiSix) is then formed on the polysilicon layer by reacting the polysilicon layer with an appropriate metal such as titanium (Ti) using a thermal treatment step. Thereafter, a second electrically insulating layer (e.g., SiO.sub.2, Si.sub.3 N.sub.4) is formed on the metal silicide layer using conventional techniques. A layer of photoresist is then deposited onto the second electrically insulating layer and patterned as an etching mask using conventional photolithographic processing steps.

Abstract: The present invention provides a method for forming a metallic wiring pattern, in which narrowing of a resist during patterning of a metallic film is prevented, adhesion of sputtered metallic film to the side walls of the resist is also prevented, and thereby a highly accurate metallic wiring pattern can be achieved.

Abstract: A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

Abstract: Disclosed is an inventive multiple-chemistry etching method suited for etching through selected portions of layers in a layer stack in a plasma processing chamber. The layer stack preferably includes at least an anti-reflective layer and a metallization layer disposed below the anti-reflective layer. The method includes a first etching step where the anti-reflective layer of the layer stack is at least partially etched with a first chemistry, the first chemistry comprising an etchant chemical and a polymer-forming chemical. Once the first etching step is complete, the method proceeds to a second etching step where at least part of the metallization layer of the layer stack is etched with a second chemistry different from the first chemistry.

Abstract: A method for etching a tungsten containing layer 25 on a substrate 10 substantially anisotropically, with good etching selectivity, and without forming excessive passivating deposits on the etched features. In the method, the substrate 10 is placed in a plasma zone 55, and process gas comprising SF.sub.6, CHF.sub.3, and N.sub.2, is introduced into the plasma zone. A plasma is formed from the process gas to anisotropically etch the tungsten containing layer 22. Preferably, the plasma is formed using combined inductive and capacitive plasma operated at a predefined inductive:capacitive power ratio.

Abstract: The object of the present invention is to provide a semiconductor device and a process of producing the same, in which a low contact resistance is ensured, the interwiring connection of a multilayered conductor wiring structure has good long term reliability, and the production time can be reduced. An interlaminar insulating layer 4 is etched with an etchant gas containing a fluorine-based gas to form a contact hole 6, during which a fluoride layer 22 is formed on a Ti layer 13 which forms an upper protective layer of a conductor wiring layer 3 on the bottom of the contact hole 6. According to the present invention, the fluoride layer 22 is removed, together with the Ti layer 13 on the bottom of the contact hole 6, by a gas mixture of a fluorine-based gas and oxygen gas in an ashing apparatus.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

Abstract: A method in a substrate processing chamber for forming a conductive feature by etching through a conductive layer disposed above a semiconductor substrate. The method includes etching at least partially through the conductive layer using a first etch recipe to form a top portion of the conductive feature. The method further includes thereafter etching at least partially through a remaining thickness of the conductive layer using a second etch recipe different from the first etch recipe to form a bottom portion of the conductive feature. The bottom portion is disposed below the top portion. The second etch recipe is configured to yield a sloped etch foot in the bottom portion of the conductive feature.

Abstract: There is provided a process which assures a large etching selectivity for resist mask or interlayer insulating film and excellent anisotropy and results in lesser particle contamination and after-corrosion by mainly constituting, with a decomposition byproduct of resist mask, a side wall protection film material which is indispensable for anisotropic etching in the plasma etching of an Al-based metal and by enhancing ion impact resistance and radical attack resistance through reinforcement of film quality to obtain sufficient side wall protection film even when an amount of deposition of the side wall protection film is reduced.

Abstract: In a dry etching method of aluminum (Al) alloy film comprising the steps of (1) forming an alloy film of which a major component is Al on a semiconductor substrate, (2) forming a resist pattern on the alloy film, and (3) dry etching the alloy film using the resist pattern as a mask with etching gas to which ammonia gas is added, a flow rate of the ammonia gas being set at between not less than half of a flow rate of the etching gas and not more than the flow rate of the etching gas. Improved fine pattern dry etching of Al alloy including Si and Cu is achieved.

Abstract: A mixed etching gas consisting of boron trichloride, a rare gas, and chlorine is used for etching of an aluminum metal film by dry-etching. In the first step, high frequency power is used to etch and remove alloy grains which tend to form residues and to etch an aluminum metal film in an anisotropic mode. Just before the under-layered silicon film is exposed, the frequency power is lowered but is kept higher than the minimum power required for anisotropic etching to enable etching selectivity with respect to the silicon dioxide film to be achieved.

Abstract: A method of etching a multicomponent alloy on a substrate, without forming etchant residue on the substrate, is described. In the method, the substrate is placed in a process chamber comprising a plasma generator and plasma electrodes. A process gas comprising a volumetric flow ratio V.sub.r of (i) a chlorine-containing gas capable of ionizing to form dissociated Cl.sup.+ plasma ions and non-dissociated Cl.sub.2.sup.+ plasma ions, and (ii) an inert gas capable of enhancing dissociation of the chlorine-containing gas, in introduced into the process chamber. The process gas is ionized to form plasma ions that energetically impinge on the substrate by (i) applying RF current at a first power level to the plasma generator, and (ii) applying RF current at a second power level to the plasma electrodes. The combination of (i) the volumetric flow ratio V.sub.r of the process gas and (ii) the power ratio P.sub.

Abstract: A method of manufacturing a semiconductor component includes sputtering a first metal layer (16) over a substrate (11), sputtering a second metal layer (17) over the first metal layer (16), selectively etching the second metal layer (17) versus the first metal layer (16), selectively etching the first metal layer (16) versus the second metal layer (17), and thereafter, selectively re-etching the second metal layer (17) versus the first metal layer (16).

Abstract: A method for forming a tungsten wiring, wherein an etch barrier layer is formed on an area where a metal wiring will be formed, using chlorine-based plasma so that the etch barrier layer is used as a mask upon forming a metal wiring, thereby eliminating a limitation on the thickness of the tungsten junction layer. the method includes the steps of sequentially forming a tungsten junction layer and a tungsten film over a semiconductor substrate, forming a negative type photoresist film pattern using a metal wiring mask, forming a copper thin film on a selectively exposed portion of the tungsten film, growing the copper thin film in a chlorine-based plasma atmosphere, thereby forming a copper chloride thin film, removing the photoresist film pattern, sequentially etching the tungsten film and tungsten junction layer using the copper chloride thin film as a mask, and removing the copper chloride thin film, thereby forming a tungsten wiring.

Abstract: A plasma etch method for patterning for use within an integrated circuit a blanket conductor layer such that an integrated circuit layer adjoining the blanket conductor layer is not damaged when the blanket conductor layer is patterned to form a patterned conductor layer through the plasma etch method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a blanket conductor layer, where the blanket conductor layer communicates electrically with the semiconductor substrate in a fashion such that an electrical charge is shunted from the blanket conductor layer into the semiconductor substrate when the blanket conductor layer is patterned to form the patterned conductor layer through the plasma etch method. There is then patterned through the plasma etch method the blanket conductor layer to form the patterned conductor layer.

Abstract: Pitting in active regions along the edges of a gate electrode when etching a composite comprising an anti-reflective coating on polysilicon is avoided by etching the anti-reflective coating with an etchant that forms a protective passivating coating on at least the sidewalls of the etched anti-reflective pattern and on the underlying polysilicon layer. Subsequently, anisotropic etching is conducted to remove the protective passivating coating from the surface of the polysilicon layer, leaving the etched anti-reflective pattern protected from the main polysilicon etch on at least its sidewalls by the passivating coating to prevent interaction. In another embodiment, the anti-reflective coating is etched without formation of a passivating coating, and the polysilicon layer subsequently etched with an etchant that forms a passivating coating.

Abstract: In a method of removing a polymer and the leavings of the resist pattern that have adhered during dry etching to a film formed on a semiconductor substrate, the etched film undergoes plasma etching with the resist patter as a mask. Next, the resist pattern is removed by O.sub.2 plasma ashing and then the surface of the substrate is washed with pure water. Thereafter, with the substrate heated to 40.degree. C. or higher, the surface of the substrate is exposed to HF vapor and then the surface of the substrate is rinsed with pure water. With this method, the polymer and the leavings of the resist pattern that have adhered to the etched film can be removed easily.

Abstract: A method is described for the prevention of the corrosion of interconnection wirings made of aluminum or aluminum-copper alloys in semiconductor integrated circuits. The invention uses a weak solution of NH.sub.4 OH to remove chlorine-containing residues that adhere to the sidewalls of the metal wirings patterned by reactive ion etching using chlorine-containing gaseous components, thus effectively quenching the chain reaction of aluminum electrochemical corrosion involving these chlorine-containing residues as an intermediary.

Abstract: A method for forming an electrode on a mesa structure of a semiconductor substrate. The method comprises the steps of: selectively forming an electrode on a predetermined area in a surface of the semiconductor substrate; and subjecting the substrate to a selective etching by use of the electrode as a mask to form a mesa structure on the substrate so that the mesa structure is self-aligned just under the electrode.