Abstract: A method for fabricating a Mach-Zehnder modulator includes: preparing a substrate product having a waveguide mesa, an embedding resin body and an inorganic insulator, the waveguide mesa being disposed on a supporting base, the inorganic insulator covering the embedding resin body to separate the embedding resin body from the waveguide mesa, the waveguide mesa having top and side faces covered with the inorganic insulator, and the embedding resin body embedding the side face of the waveguide mesa; forming an opening in the inorganic insulator by etching to form an inorganic insulating region, the opening reaching the top face of the waveguide mesa, the inorganic insulating region covering the embedding resin body and the side face of the inorganic insulator; and forming an ohmic electrode in the opening to make contact with the top face of the mesa, the inorganic insulating region separating the ohmic electrode from the embedding resin body.

Abstract: A package structure is provided. The package structure includes a first under bump metallurgy (UBM) layer formed over a first substrate, a first protrusion structure formed over the first UBM layer, wherein the first protrusion structure extends upward away from the first UBM layer. The package structure includes a first electrical connector formed over the first protrusion structure. The first electrical connector is surrounded by the first protrusion structure, and the first protrusion structure has an outer sidewall surface, and the outer sidewall surface of the first protrusion structure is aligned with an outer surface of the first UBM layer.

Abstract: The present invention discloses a touch panel and a method of manufacturing a touch panel, to reduce the visibility of the transparent etching line of the transparent electrodes on the touch panel. The touch panel comprises a plurality of transparent electrode disposed distantly on the transparent conductive layer and the passivation layer of a transparent substrate, where the passivation layer covering the transparent conductive layer, to make the refractive index of the passivation layer and the transparent electrodes match with each other. Oxide with high refractive index added in the passivation material is filled in the etched area of the transparent conductive layer, so that the optical refractive index of the etched area and ITO area on transparent conductive layer become closer, and the difference in refractive index curve between ITO area and etched area is reduced, therefore, the effect of making the transparent electrode pattern is achieved.

Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Abstract: A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells.

Abstract: By cleaning with use of a cleaning liquid that contains 10-30% by mass of hydrogen peroxide, 0.005-10% by mass of a quaternary ammonium hydroxide, 0.005-5% by mass of potassium hydroxide, 0.000005-0.005% by mass of an amino polymethylene phosphonic acid and water, a hard mask, an organosiloxane-based thin film, dry etching residue and a photoresist can be removed without corroding a low-dielectric-constant interlayer dielectric film, a wiring material such as copper or an copper alloy, a barrier metal and a barrier dielectric film. According to preferred embodiments of the present invention, damage to copper wiring lines is suppressed even in cases where an acid is added into the cleaning liquid and significant decomposition of hydrogen peroxide is not caused even in cases where titanium is added into the cleaning liquid.

Abstract: An organic light emitting diode (OLED) display that is flexible is disclosed. According to one aspect it includes: a flexible substrate, a moisture permeation preventing layer formed on the flexible substrate, a barrier layer formed on the moisture permeation preventing layer, an OLED formed on the barrier layer, a thin film encapsulation layer covering the OLED, and a lower protection film attached beneath the flexible substrate.

Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.

Abstract: A method is provided for manufacturing a semiconductor device having a heat-resistant resin film with flip-chip connection structure using a solder bump or a gold bump and an epoxy resin compound laminated thereon, in which adhesiveness is improved particularly after exposure to high temperature and high humidity environments for a long period of time, thereby enhancing the reliability of the semiconductor device. The method, in accordance with the present invention, for manufacturing a semiconductor device having a heat-resistant resin film formed on a semiconductor element and an epoxy resin compound layer laminated thereon, comprises the steps of carrying out a plasma treatment on a surface of the heat-resistant resin film on which the epoxy resin compound layer is laminated using a nitrogen atom-containing gas containing at least one of nitrogen, ammonia, and hydrazine.

Abstract: A method for etching features in an etch layer is provided. An organic mask layer is etched, using a hard mask as an etch mask. The hard mask is removed, by selectively etching the hard mask with respect to the organic mask and etch layer. Features are etched in the etch layer, using the organic mask as an etch mask.

Abstract: In some embodiments, methods for forming a three dimensional NAND structure include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon consisting layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating layers; providing a process gas comprising sulfur hexafluoride and oxygen to the process chamber; providing RF power of about 4 kW to about 6 kW to a first inductive RF coil and a second inductive RF coil disposed proximate the process chamber to ignite the process gas to form a plasma, wherein a current flowing through the first inductive RF coil is out of phase with RF current flowing through the second inductive RF coil; and etching through a desired number of the alternating layers to form a feature.

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract: A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps.

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.

Abstract: Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT.

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Abstract: A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure.

Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

Abstract: One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.

Abstract: A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Abstract: A tensile strain state in semiconductor components is adjusted. A pretensioned (tensile strain) layer is applied to a substrate (FIG. 1, (A)). Bridge structures (FIG. 1, (B)) are introduced in the layers by lithography and etching. The bridges are connected to the layer on both sides and are thus continuous. The geometric shape of the bridges, formed with a cross-section modulation, is determined by the windows (FIG. 1 (C)) in the layer. When the substrate is etched selectively, the bridge is undercut through the windows. The geometric structuring of the cross-section (FIG. 1, (D)) causes a redistribution of the originally homogeneous strain when the bridges are detached from the substrate, with the larger cross-sections relaxing at the expense of the smaller cross-sections, where the pretension is increased. Only a multiplication of stresses (or strain) originally present in the sample is possible, with the multiplication factor determined by lengths, widths and depths, and/or the relationships thereof.

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: The substrate is provided with a layer of first material, a first etching mask, a covering layer and a second etching mask. The covering layer has a covered main area and an uncovered secondary area. The secondary area of the covering layer is partially etched via the second etching mask to form a salient pattern. Lateral spacers are formed around the salient pattern defining a third etching mask. The second etching mask is eliminated. The covering layer is etched by means of the third etching mask to form a salient pattern in the covering layer and to uncover the first etching mask and the first material. The layer of first material is etched to form the pattern made from the first material.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film containing boron on a semiconductor substrate, forming a film containing silicon oxide on the film containing boron, patterning the film containing silicon oxide and etching the film containing boron with a gas containing chlorine by using the patterned film containing silicon oxide as a mask.

Abstract: A substrate processing method that processes a substrate including a processing target layer, an intermediate layer, and a mask layer as stacked in that order. The intermediate layer includes an Si-ARC (Si-containing Anti-Reflection Coating) film and the mask layer has an opening exposing a part of the Si-ARC. The substrate processing method includes a shrink etching step during which an opening width reduction process and an etching process are performed concurrently. In the opening width reduction process, deposits are formed on a sidewall surface of the opening of the mask layer by a plasma generated from a gaseous mixture of an anisotropic etching gas and one of a depositive gas and H2 gas. And in the etching process, the Si-ARC film forming a bottom portion of the opening are etched.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: An intermediate film 222 in a three-layered resist film 225 is formed by the chemical vapor deposition process at a temperature not higher than 300° C., using Si(OR1)(OR2)(OR3)(OR4), where each of R1, R2, R3 and R4 independently represents a carbon-containing group or a hydrogen atom, excluding the case where all of R1 to R4 are hydrogen atoms.

Abstract: A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.

Abstract: A plasma processing method includes: etching an anti reflection coating film with plasma generated from an etching gas by using a resist film that is patterned as a mask, in a deposited film in which an Si-ARC film constituting the anti reflection coating film is formed on a layer to be etched and the ArF resist film is formed on the anti reflection coating film; and modifying the ArF resist film with plasma generated from a modifying gas including a CF4 gas, a COS gas and an Ar gas by introducing the modifying gas into a plasma processing apparatus, wherein the modifying is performed before the etching.

Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.

Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.

Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.

Abstract: The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics.

Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.

Abstract: A method for processing an amorphous carbon film which has been formed on a substrate and wet-cleaned after being dry-etched includes preparing the substrate having the wet-cleaned amorphous carbon film and modifying a surface of the amorphous carbon film, before forming an upper layer on the wet-cleaned amorphous carbon film.

Abstract: In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.

Abstract: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped.

Abstract: In a semiconductor that has a structure in which a work function controlling metal conductor is provided on a high dielectric insulation film, fine processing is performed without deteriorating a device. In a method of semiconductor processing, in which the semiconductor has an insulation film containing Hf or Zr formed on a semiconductor substrate and a conductor film containing Ti or Ta or Ru formed on an insulation film, and the conductor film is processed by using a resist formed on the conductor film under a plasma atmosphere, the resist is removed under the plasma atmosphere of gas that contains hydrogen and does not contain oxygen.

Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.

Abstract: A plasma processing method performed in a plasma processing apparatus including a processing chamber accommodating a substrate in which a plasma is generated; a mounting table mounting the substrate, which is provided in the processing chamber and to which a plasma attraction high frequency voltage is applied; and a facing electrode provided to face the mounting table in the processing chamber, to which a negative DC voltage is applied, the method including: applying a plasma attraction high frequency voltage to the mounting table for a predetermined period of time; and stopping the application of the plasma attraction high frequency voltage to the mounting table. In the plasma processing method, the application of the plasma attraction high frequency voltage and stopping thereof are alternately repeated.

Abstract: A method for manufacturing a circuit pattern-provided substrate including forming a resist layer on a substrate, forming an opening corresponding to a circuit pattern and having an eaves cross-sectional shape in the resist layer, forming a thin film layer having a portion formed on the substrate in the opening and a portion formed on the resist layer, and removing the resist layer such that the resist layer and the portion of the thin film layer formed on the resist layer are removed from the substrate. The forming of the opening comprises exposing the resist layer with a mask device which changes an exposure amount of the resist layer such that the eaves cross-sectional shape has a space at a boundary between the resist layer and the substrate.

Abstract: A method of forming a photoresist-comprising pattern on a substrate includes forming a patterned first photoresist having spaced first masking shields in at least one cross section over a substrate. The first masking shields are exposed to a fluorine-containing plasma effective to form a hydrogen and fluorine-containing organic polymer coating about outermost surfaces of the first masking shields. A second photoresist is deposited over and in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating. The second photoresist which is in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating is exposed to a pattern of actinic energy and thereafter spaced second masking shields are formed in the one cross section which comprise the second photoresist and correspond to the actinic energy pattern. The first and second masking shields together form at least a part of a photoresist-comprising pattern on the substrate.

Abstract: Methods of patterning a material are disclosed. A first resist pattern is formed on a field. A protective layer is formed over the first resist pattern and at least a portion of the field. A second resist pattern is formed over a portion of the protective layer. A portion of a material to be patterned deposited adjacent to the first and second resist patterns is removed.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent.