Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.

Abstract: A method for manufacturing a magnetic sensor that allows the sensor to be constructed with a very narrow track width and with smooth, well defined side walls. A tri-layer mask structure is deposited over a series of sensor layers. The tri-layer mask structure includes an under-layer, a Si containing hard mask deposited over the under-layer and a photoresist layer deposited over the Si containing hard mask. The photoresist layer is photolithographically patterned to define a photoresist mask. A first reactive ion etching is performed to transfer the image of the photoresist mask onto the Si containing hard mask. The first reactive ion etching is performed in a chemistry that includes CF4, CHF3, O2, and He. A second reactive ion etching is then performed in an oxygen chemistry to transfer the image of the Si containing hard mask onto the under-layer, and an ion milling is performed to define the sensor.

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.

Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: A dry etching method for a silicon nitride film capable of improving throughput is provided. A dry etching method for dry-etching a silicon nitride film 103 includes dry-etching the silicon nitride film 103 without generating plasma by using a processing gas containing at least a hydrogen fluoride gas (HF gas) and a fluorine gas (F2 gas), with respect to a processing target object 100 including the silicon nitride film 103.

Abstract: A method for etching a substrate includes etching at least one first layer of the substrate with a non-uniform substrate temperature and etching at least one second layer of the substrate with uniform substrate temperatures.

Abstract: A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

Abstract: Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.

Abstract: A method of patterning a hard mask layer for defining a deep trench is described. A substrate formed with an isolation structure therein is provided. A hard mask layer is formed over the substrate provided. A patterned photoresist layer is formed over the hard mask layer, having therein a deep-trench opening pattern over the isolation structure. An etching gas not containing hydrogen is used to etch the hard mask layer with the patterned photoresist layer as a mask and thereby transfer the deep-trench opening pattern to the hard mask layer.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.

Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

Abstract: A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least ?20° C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region.

Abstract: Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0.8 to about 4.

Abstract: A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.

Abstract: A substrate processing method capable of selectively removing a nitride film. Oxygen plasma containing plasmarized oxygen gas is made to be in contact with a silicon nitride film, which is made of SiN, of a wafer to thereby cause the silicon nitride film to be changed to a silicon monoxide film. The silicon monoxide film is selectively etched by hydrofluoric acid generated from HF gas supplied toward the silicon monoxide film.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer.

Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

Abstract: Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and having an oxide-nitride-based structure on a backside of the semiconductor substrate. The IC device structure can be etched to remove a nitride-related material from the backside oxide-nitride-based structure, and further to remove the first pad oxide-based layer from the front side of the semiconductor substrate. On the removed front side of the semiconductor substrate a second pad oxide-based layer can be formed, e.g., for forming an isolation structure for device component or circuitry isolation.

Abstract: An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound 6 is formed directly on a channel 5 of a transistor 1 comprising a source electrode 2, a drain electrode 3, a gate electrode 4 and the n-type channel 5 having a nanotube-shaped structure and provided between the source electrode 2 and the drain electrode 3.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: Silicon oxide film having, as a sublayer, a silicon nitride film layer serving as a protective film layer for 5 gate formed on silicon substrate is etched by introducing a processing gas including a gaseous mixture containing at least C4F6, Ar, O2 and N2 into an airtight processing chamber and carrying out a plasma treatment in a self-alignment contact process, thereby forming contact hole. For the 10 processing gas, e.g., the ratio of N2 gas flow rate to C4F6 gas flow rate ranges from 25/8 to 85/8, the ratio of O2 and N2 gas flow rate to C4F6 gas flow rate ranges from 15/4 to 45/4 and the ratio of N2 gas flow rate to O2 gas flow rate ranges from 5 to 17. Accordingly, stable contact holes of 15 high aspect ratio exhibiting desirable control characteristics is formed while minimizing etching the silicon nitride film, a protective film layer for gate.

Abstract: An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound 6 is formed directly on a channel 5 of a transistor 1 comprising a source electrode 2, a drain electrode 3, a gate electrode 4 and the n-type channel 5 having a nanotube-shaped structure and provided between the source electrode 2 and the drain electrode 3.

Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.

Abstract: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.

Abstract: The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer, dry-etching the third metal layer by using the first photoresist pattern, simultaneously dry-etching the second and first metal layers by using the first photoresist pattern, dry-etching the active layer by using the first photoresist pattern, etching the first photoresist pattern to form a second photoresist pattern by which the channel region is removed and forming a source electrode and a drain electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.

Abstract: A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.

Abstract: A method for fabricating an inductor structure or a dual damascene structure includes following steps. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric layer. A polymer is also formed in the first opening during the first etching process. Next, a polymer-removing step is performed to remove the polymer. Thereafter, a second etching process is performed on the dielectric layer to form a second opening in the dielectric layer. Furthermore, the first opening and the second opening are filled with a conductive material so as to form an inductor structure or a dual damascene structure.

Abstract: A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or etch byproducts. Either the silicide or the etch byproducts or their combination may block the ensuing polysilicon etch which is needed to remove the polysilicon gate structure and to thereafter replace it with an appropriate metal gate technology.

Abstract: The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to improved substrate patterning for multi-gate transistors.

Abstract: A method of manufacturing a semiconductor device is disclosed. In the method of manufacturing the semiconductor device, a first insulating layer is formed on a semiconductor substrate. A metal line layer and an etch-stop layer are formed over the first insulating layer. The etch-stop layer and the metal line layer are patterned to form a metal line. A second insulating layer is formed on the first insulating layer and the etch-stop layer. A first etch process for etching part of the second insulating layer is performed by using a first etch gas so that the etch-stop layer is exposed. A second etch process for removing the etch-stop layer is performed by using a second etch gas so that the metal line is exposed.

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Abstract: A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask, and the hydrogen concentration of the patterned silicon nitride layer is more than 1022 atoms/cm3. Thereafter, the conductive layer and the dielectric layer are etched utilizing the hard mask as a mask. Finally, an etching solution is utilized to remove the hard mask.