Silicon Nitride Patents (Class 438/744)
  • Patent number: 5874369
    Abstract: Vias are formed in a dielectric film overlying an electrode layer by sweeping a laser beam over the area in which the via is to be formed. In particular, a Nd:YAG laser, producing a beam of light having a 266 nm wave length, effectively ablates a barium strontium titanate dielectric film, without adversely affecting an underlying platinum electrode. The present invention overcomes the problem of wet chemical etching of dielectric films to form vias. Wet chemical etching often requires etchants that adversely affect the underlying metal electrode and typically require the use of environmentally undesirable chemicals.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Mukta Shaji Farooq, Mark Joseph LaPlante
  • Patent number: 5854136
    Abstract: This invention describes a three-step process for etching a layer of silicon nitride over a thin layer of silicon dioxide on a semiconductor substrate for producing silicon nitride pattern with nearly vertical sidewalls, very small critical dimension bias and no trenching in the silicon dioxide, comprising a first step of a highly anisotropic etch process with a high etch rate, achieved by adding CHF.sub.3 to the gaseous mixture of SF.sub.6 and He, carried out at a relatively high power and low pressure, used to etch the bulk of the silicon nitride layer, a second step of lower etch anisotropy and etch rate, achieved by replacing CHF.sub.3 with HBr, carried out at higher pressure and lower power, used to etch out the remainder of the nitride layer with a small over-etch beyond the end point, a third step of high Si.sub.3 N.sub.4 /SiO.sub.2 etch selectivity, achieved by adding an oxidant to the reactive gas mixture, used to remove any remaining silicon nitride residues.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: December 29, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Chang Huang, Yuh Da Fan, Yung-Jung Chang
  • Patent number: 5851927
    Abstract: A method for forming a semiconductor device, including providing a silicon substrate (10), forming a gate stack (11) on the substrate (10), coating a deep ultra-violet (DUV) photoresist (30) on the gate stack (11), exposing and developing the photoresist (30), and etching the gate stack (11). According to the present invention, the gate stack (11) has a dielectric nitride layer (26), particularly, a silicon nitride layer. An adhesive oxide layer (28) is provided between the nitride layer (26) and the photoresist (30) to prevent undesirable lifting of the photoresist (30). Yield is greatly increased and defectivity is reduced.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 22, 1998
    Assignee: Motorola, Inc.
    Inventors: Paul Kevin Cox, Thy Ngu-Uyen Tran, Samuel Jay Wright, Judith Sobresky
  • Patent number: 5817579
    Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer through a first reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer through a second reactive ion etch (RIE) method employing a second etchant gas composition comprising carbon tetrafluoride and oxygen.
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: October 6, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jun-Cheng Ko, Erik S. Jeng
  • Patent number: 5788767
    Abstract: The present invention is a method for using a single SiN layer as a passivation film. The single layer SiN can be strengthened to withstand stress by adjusting the process parameters during formation of the SiN layer. In general, the process can be changed by increasing the low frequency power 5% during the deposition. Alternatively, the pressure of the SiN deposition may be decreased about 20% in pressure.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: August 4, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jun-Cheng Ko, Liang-Tung Tony Chang
  • Patent number: 5767018
    Abstract: Pitting in active regions along the edges of a gate electrode when etching a composite comprising an anti-reflective coating on polysilicon is avoided by etching the anti-reflective coating with an etchant that forms a protective passivating coating on at least the sidewalls of the etched anti-reflective pattern and on the underlying polysilicon layer. Subsequently, anisotropic etching is conducted to remove the protective passivating coating from the surface of the polysilicon layer, leaving the etched anti-reflective pattern protected from the main polysilicon etch on at least its sidewalls by the passivating coating to prevent interaction. In another embodiment, the anti-reflective coating is etched without formation of a passivating coating, and the polysilicon layer subsequently etched with an etchant that forms a passivating coating.
    Type: Grant
    Filed: November 8, 1995
    Date of Patent: June 16, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Scott A. Bell
  • Patent number: 5756402
    Abstract: A method for etching a silicon nitride film, includes the steps of supplying a fluorine radical, a compound of fluorine and hydrogen, and an oxygen radical close to a substrate having the silicon nitride film, and selectively etching the silicon nitride film from the substrate with the fluorine radical, the compound of fluorine and hydrogen, and the oxygen radical.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: May 26, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sadayuki Jimbo, Tokuhisa Ohiwa, Haruki Mori, Akira Kobayashi, Tadashi Shinmura, Yasuyuki Taniguchi
  • Patent number: 5753565
    Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: May 19, 1998
    Assignee: Micron Technology, Inc.
    Inventor: David S. Becker
  • Patent number: 5750441
    Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: May 12, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Thomas A. Figura, Bradley J. Howard