Utilizing Electromagnetic Or Wave Energy Patents (Class 438/746)
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Patent number: 7887636Abstract: A substrate dryer includes, among other things, means for generating isopropyl alcohol bubbles, and a vibrator to atomize stored isopropyl alcohol. A heater may be provided to heat pumped isopropyl alcohol, as wells as a spray nozzle to spray the heated IPA to the vibrator. It is possible to increase the concentration of the isopropyl alcohol supplied for the purpose of drying the substrate. Improved substrate drying is achieved.Type: GrantFiled: January 11, 2006Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyeon Nam, Seung-Kun Lee
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Patent number: 7883951Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.Type: GrantFiled: November 2, 2006Date of Patent: February 8, 2011Assignee: Intel CorporationInventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
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Patent number: 7776757Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than ?1.4 volts.Type: GrantFiled: January 15, 2009Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Simon Su-Horng Lin, Yu-Ming Lee, Shao-Yen Ku, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
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Patent number: 7776756Abstract: An etching apparatus includes a chamber containing an etching solution including first and second components and water, a concentration of the water in the etching solution is at a specified level or lower; a circulation path circulating the etching solution; a concentration controller sampling the etching liquid from the circulation path and controls concentrations of the etching solution respectively; and a refilling chemical liquid feeder feeding a refilling chemical liquid including the first component having a concentration higher than the first component in the etching solution.Type: GrantFiled: July 30, 2007Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Okuchi, Hiroyasu Iimori, Mami Saito, Yoshihiro Ogawa, Hiroshi Tomita, Soichi Nadahara
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Publication number: 20100195684Abstract: A method for fabricating a semiconductor laser device, by etching facets using a photoelectrochemical (PEC) etch, so that the facets are sufficiently smooth to support optical modes within a cavity bounded by the facets.Type: ApplicationFiled: February 1, 2010Publication date: August 5, 2010Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Adele C. Tamboli, Evelyn L. Hu, Steven P. DenBaars, Arpan Chakraborty
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Publication number: 20100190351Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.Type: ApplicationFiled: April 6, 2010Publication date: July 29, 2010Applicant: Micron Technology, Inc.Inventors: Li Li, Don L. Yates
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Patent number: 7732351Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique and a manufacturing apparatus of a semiconductor device which simplify a lithography step using a photoresist is provided, so that the manufacturing cost is reduced, and the throughput is improved. An irradiated object, in which a light absorbing layer and an insulating layer are stacked over a substrate, is irradiated with a multi-mode laser beam and a single-mode laser beam so that both the laser beams overlap with each other, and an opening is formed by ablation in part of the irradiated object the irradiation of which is performed so that both the laser beams overlap with each other.Type: GrantFiled: September 18, 2007Date of Patent: June 8, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hirotada Oishi, Koichiro Tanaka
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Publication number: 20100120255Abstract: A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mask material onto the foundation film so as to cover the core pattern, the mask material being crosslinkable upon supply acid from the core pattern; etching back the mask material to expose an upper surface of the core pattern and remove a portion of the mask material formed on the end portion of the core pattern, thereby leaving a mask material side wall portion formed on a side wall of the core pattern; and removing the core pattern and processing the foundation film by using the mask material sidewall portion left on the foundation film as a mask.Type: ApplicationFiled: September 22, 2009Publication date: May 13, 2010Inventors: Kentaro MATSUNGA, Hirokazu Kato, Tomoya Oori
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Patent number: 7709341Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.Type: GrantFiled: June 2, 2006Date of Patent: May 4, 2010Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
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Patent number: 7691207Abstract: A method for cleaning a disk-shape glass substrate, which comprises rotating the disk-shape glass substrate on its center with its main surface vertical, and making a cleaning fluid irradiated with ultrasonic waves run down on the outer peripheral edge surface of the rotating glass substrate.Type: GrantFiled: July 14, 2006Date of Patent: April 6, 2010Assignee: Asahi Glass Company, LimitedInventors: Osamu Miyahara, Kazuo Mannami, Kuniyuki Someya, Tsutomu Maruyama
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Publication number: 20100015810Abstract: A processing object 2 is sucked and fixed by a sucker 11 and rotated by a rotator 12. In that state, a processing liquid supplied from a processing liquid supply 22 is applied through a processing liquid application tube 21 onto a surface of the processing object 2. Thermal electrons emitted from a thermionic source 33 are accelerated by an acceleration electrode 34 and pass through a Be film 32 to impinge upon the processing liquid on the surface of the processing object 2. When the processing liquid on the surface of the processing object is irradiated with the electron beam, the processing liquid is ionized or radicalized to become active, thereby effectively processing the surface of the processing object 2.Type: ApplicationFiled: June 22, 2007Publication date: January 21, 2010Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Yutaro Yanagisawa, Katsuyoshi Fujita
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Publication number: 20090283800Abstract: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.Type: ApplicationFiled: May 12, 2009Publication date: November 19, 2009Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Won-bin Im, Ram Seshadri, Steven P. DenBaars
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Patent number: 7598181Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.Type: GrantFiled: July 19, 2005Date of Patent: October 6, 2009Assignee: Micron Technology, Inc.Inventors: Theodore M. Taylor, Stephen J. Kramer
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Publication number: 20090191716Abstract: A polysilicon layer removing method capable of substantially removing etching residue, while improving the shape of an etching boundary is disclosed. The method for removing the polysilicon layer from a beveled portion of a wafer W through wet etching includes hydrophilizing the polysilicon layer, without removing the polysilicon layer from the beveled portion, and supplying an etchant having the mixture of hydrofluoric acid and nitric acid onto the hydrophilized polysilicon layer of the beveled portion, while the wafer is rotated at revolutions enough for flattening an etching boundary.Type: ApplicationFiled: January 30, 2009Publication date: July 30, 2009Applicant: TOKYO ELECTRON LIMITEDInventor: Mitsunori Nakamori
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Patent number: 7563717Abstract: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper side of the insulating layer. The second polishing step is performed, after completing the first polishing step, for planarizing the insulating interlayer.Type: GrantFiled: December 28, 2005Date of Patent: July 21, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Ji Hyung Yune
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Patent number: 7550395Abstract: A method for locally controlling an electrical potential of a semiconductor structure or device, and hence locally controlling lateral and/or vertical photoelectrochemical (PEC) etch rates, by appropriate placement of electrically resistive layers or layers that impede electron flow within the semiconductor structure, and/or by positioning a cathode in contact with specific layers of the semiconductor structure during PEC etching.Type: GrantFiled: October 31, 2005Date of Patent: June 23, 2009Assignee: The Regents of the University of CaliforniaInventors: Evelyn L. Hu, Shuji Nakamura, Elaine D. Haberer, Rajat Sharma
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Patent number: 7538042Abstract: A method of manufacturing a structure is provided. This method include a steps of preparing a first substrate having a projection, forming a first layer on the projection, transferring the first layer to a second substrate, and removing at least apart of the second substrate.Type: GrantFiled: March 2, 2005Date of Patent: May 26, 2009Assignee: Canon Kabushiki KaishaInventors: Aya Imada, Tohru Den
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Patent number: 7452478Abstract: This invention provides a method for converting materials for stabilizing surfaces of semiconductor nanoparticles. In this method, surfaces of semiconductor nanoparticles are first modified and then dissolved by photoetching in the presence of materials for stabilization to obtain nanoparticles that are stabilized in an aqueous solution.Type: GrantFiled: August 27, 2003Date of Patent: November 18, 2008Assignee: Hitachi Software Engineering Co., Ltd.Inventors: Keiichi Sato, Susumu Kuwabata
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Publication number: 20080242104Abstract: A method of manufacturing a semiconductor device has a first exposure to the photoresist by using a first mask having a first portion of a monitor pattern, a second exposure to the photoresist by using a second mask having a second portion of the monitor pattern so that a first image of the first portion and a second image of the second portion are connected.Type: ApplicationFiled: March 26, 2008Publication date: October 2, 2008Applicant: FUITSU LIMITEDInventors: Kazuhito HONMA, Masaru MIYAZAKI, Masanori ONODERA
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Patent number: 7410814Abstract: An effective electropurge process and apparatus for wet processing of semiconductor wafers applies electrical charges to the wafer surface with an ample voltage sufficient to provide an effective field intensity which can substantially eliminate intolerable sub-0.05 micron “killer” defects when making highly advanced microchips with a feature size or line width less than 0.15 micron. The process can be used with frequent voltage reversal for automated wet-batch cleaning operations using cassettes that hold 10 to 50 wafers at a time and in various other operations involving megasonic transducers, mechanical brush scrubbers, laser cleaners and CMP equipment. The electropurge process is primarily intended for Fab plants where large wafers with a diameter of 200 to 400 mm require 250 to 350 steps including many dry layering, patterning and doping operations and at least 30 wet processing steps.Type: GrantFiled: October 19, 2005Date of Patent: August 12, 2008Inventors: Ted A. Loxley, Vincent A. Greene
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Patent number: 7410909Abstract: A method of removing an ion implanted photoresist comprises performing first cleaning a semiconductor substrate having the ion implanted photoresist using hot deionized water to which a megasonic process is applied, first rinsing the semiconductor substrate using cold deionized water, drying the semiconductor substrate, removing the ion implanted photoresist, and second cleaning the semiconductor wafer using an SPM solution.Type: GrantFiled: December 28, 2006Date of Patent: August 12, 2008Assignee: Hynix Semiconductor Inc.Inventors: Ji Hye Han, Ok Min Moon, Woo Jin Kim, Hyo Seob Yoon, Ji Yong Park, Kee Joon Oh
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Patent number: 7375017Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.Type: GrantFiled: January 23, 2006Date of Patent: May 20, 2008Assignee: Nanya Technology CorporationInventors: Tzu-En Ho, Chih-Hao Chang, Chang-Rong Wu, Kuo-Hui Su
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Publication number: 20080111175Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.Type: ApplicationFiled: November 13, 2006Publication date: May 15, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Richard O. Henry, Kenneth T. Settlemyer
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Patent number: 7307026Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.Type: GrantFiled: February 25, 2004Date of Patent: December 11, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Christof Streck, Guido Koerner, Thorsten Kammler
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Publication number: 20070269990Abstract: A method of removing an ion implanted photoresist comprises performing first cleaning a semiconductor substrate having the ion implanted photoresist using hot deionized water to which a megasonic process is applied, first rinsing the semiconductor substrate using cold deionized water, drying the semiconductor substrate, removing the ion implanted photoresist, and second cleaning the semiconductor wafer using an SPM solution.Type: ApplicationFiled: December 28, 2006Publication date: November 22, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Ji Hye Han
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Publication number: 20070207606Abstract: A method for removing residual flux applied to a wafer process is disclosed by the present invention, the method comprises the steps of: providing a wafer; forming a plurality of bumps on the surface of the wafer; coating flux on the surfaces of the bumps; reflowing the bumps; immersing the wafer in a cleaning solvent; cleaning the wafer by a plasma descum cleaning; rinsing the wafer; and drying the wafer.Type: ApplicationFiled: January 11, 2007Publication date: September 6, 2007Inventors: Chun-Chi Wang, Yao-Feng Huang, Chih-Hsing Chen, Chi-Yu Wang
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Patent number: 7247577Abstract: A wafer planarization process with a conditioning tool having an electrical insulator that electrically insulates the abrasive surface of the conditioning tool. The electrical insulator extends the useful life of the abrasive surface of the conditioning tool by reducing the level of electrochemically driven corrosion.Type: GrantFiled: April 18, 2006Date of Patent: July 24, 2007Assignee: 3M Innovative Properties CompanyInventors: Gary M. Palmgren, Brian D. Goers, Douglas J. Pysher
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Patent number: 7129160Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.Type: GrantFiled: August 29, 2002Date of Patent: October 31, 2006Assignee: Micron Technology, Inc.Inventor: Dinesh Chopra
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Patent number: 7064082Abstract: The present invention pertains to a more efficient system and method for forming rectifying junction contacts in PIN alloy-semiconductor devices using photoelectrical and chemical etching. The present invention provides a means of creating rectifying junction contacts on alloy-semiconductor devices such as CdTe and CdZnTe, among others. In addition, the present invention also provides a simple and low cost method for revealing wafer surface morphology of alloy-semiconductors, thus providing an efficient and effective means for selecting single grain semiconductor substrates. Further, the present invention provides radiation detectors employing such alloy-semiconductor devices having improved rectifying junctions as the detector element.Type: GrantFiled: January 15, 2004Date of Patent: June 20, 2006Assignee: Science Applications International CorporationInventors: Raulf M. Polichar, Kuo-Tong Chen
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Patent number: 7049235Abstract: A method of manufacturing a semiconductor device includes a process for forming a photoresist pattern. In the disclosed process, residual photoresist polymers are removed using a photoresist polymer remover composition that includes: (a) 5% to 15% of sulfuric acid based on the total weight of said composition, (b) 1% to 5% of hydrogen peroxide or 0.0001% to 0.05% of ozone based on the total weight of said composition, (c) 0.1% to 5% of acetic acid based on the total weight of said composition, (d) 0.0001% to 0.5% of ammonium fluoride based on the total weight of said composition and (e) remaining amount of water.Type: GrantFiled: November 26, 2003Date of Patent: May 23, 2006Assignee: Hynix Semiconductor Inc.Inventors: Seong Hwan Park, Chang Hwan Lee
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Patent number: 7026255Abstract: In a method for photo-electrochemical etching of a semiconductor sample, the semiconductor sample is brought in contact with an electrolyte liquid. The contact area formed thereby is illuminated through the electrolyte liquid with UV light. The photo-current created by UV light irradiation at the contact area is measured. To increase the etching quality, a jet of fresh electrolyte liquid is repeatedly applied to the contact area. A device for carrying out the method includes a container to be filled with an electrolyte liquid, a UV source for illuminating the semiconductor sample with UV light through the electrolyte liquid, and a measuring instrument for measuring the photo-current created during UV light irradiation of the contact area. Further provided are an inlet for supplying fresh electrolyte liquid, directed towards the semiconductor sample, and a device attached to the inlet for repeated production of electrolyte fluid jets, directed towards the semiconductor sample.Type: GrantFiled: October 24, 2003Date of Patent: April 11, 2006Inventor: Thomas Wolff
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Patent number: 7018936Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.Type: GrantFiled: January 12, 2004Date of Patent: March 28, 2006Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
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Patent number: 7018938Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.Type: GrantFiled: November 14, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Subramanyam A. Iyer, Justin K. Brask, Vijayakumar S. Ramachandrarao
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Patent number: 6989312Abstract: Provided is a method for fabricating a semiconductor optical device that can be used as a reflecting semiconductor mirror or an optical filter, in which two or more types of semiconductor layers having different etch rates are alternately stacked, at least one type of semiconductor layers is selectively etched to form an air-gap structure, and an oxide or a nitride having a good heat transfer property is deposited so that the air gap is buried, whereby it is possible to effectively implement the semiconductor reflector or the optical filter having a high reflectance in a small period because of the large index contrast between the oxide or the nitride buried in the air gap and the semiconductor layer.Type: GrantFiled: March 16, 2004Date of Patent: January 24, 2006Assignee: Electronics and Telecommunications Research InstituteInventors: Hyun Woo Song, Won Seok Han, Jong Hee Kim, Young Gu Ju, O Kyun Kwon, Sang Hee Park
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Patent number: 6943124Abstract: A method is provided for forming features in a polyimide layer that is employed as an insulating layer or buffer layer during the fabrication of semiconductor devices or chip packaging structures. A pattern is formed in a photosensitive layer that has a high film retention after the development step and a crosslinked network that strengthens and stabilizes it for subsequent processing. The process involves exposing a negative tone photosensitive layer with a first exposure dose that is less than the normal dose used to image the material. The exposed layer is developed to provide a scum free substrate. A second exposure dose then strengthens the formed image by crosslinking unreacted components. First and second exposure doses are determined from a plot of film thickness loss vs. exposure energy. The method applies to photosensitive polyimide precursors as well as negative photoresists that are crosslinked by free radical or chemical amplification mechanisms.Type: GrantFiled: July 17, 2002Date of Patent: September 13, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shin-Rung Lu, Ho-Ku Lan
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Patent number: 6914008Abstract: A structure having pores includes a first layer containing alumina, a second layer that includes at least one of Ti, Zr, Hf, Nb, Ta, Mo, W and Si, and a third layer with electrical conductivity, in this order, wherein the first and second layers have pores.Type: GrantFiled: May 6, 2004Date of Patent: July 5, 2005Assignee: Canon Kabushiki KaishaInventors: Toru Den, Nobuhiro Yasui, Tatsuya Saito
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Patent number: 6897161Abstract: A component having small holes, such as a silicon electrode plate having gas nozzles, used in a plasma processing apparatus is cleaned by producing a cavitation zone that extends through an entire depth of the holes so that deposited layers on the inner walls of the holes formed during the use in the apparatus are removed. The cleaned component can subsequently be re-used in the apparatus, and the production cost and the consumption of natural resources are decreased.Type: GrantFiled: February 11, 2003Date of Patent: May 24, 2005Assignee: Kawasaki Microelectronics, Inc.Inventor: Katsunori Suzuki
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Patent number: 6878634Abstract: A structure having recesses and projections is provided. A method of manufacturing the structure comprises the steps of preparing a first substrate having a projection, forming a first layer on the projection, transferring the first layer to a second substrate, and forming a recessed/projected surface structure in the second substrate by using the first layer.Type: GrantFiled: March 26, 2003Date of Patent: April 12, 2005Assignee: Canon Kabushiki KaishaInventors: Aya Imada, Tohru Den
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Patent number: 6869889Abstract: A metal carbide film may be etched in an etchant bath using sonication. The sonication may drive the reaction and, particularly, the gaseous byproducts in the form of carbon dioxide. Thus, the use of sonication invokes a favorable equilibrium to pattern metal carbide films, for example, for use as metal gate electrodes.Type: GrantFiled: April 7, 2004Date of Patent: March 22, 2005Assignee: Intel CorporationInventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Terence Bacuita, Robert S. Chau
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Patent number: 6863769Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.Type: GrantFiled: September 12, 2003Date of Patent: March 8, 2005Assignee: Infineon Technologies AGInventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jörn Lützen
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Patent number: 6852643Abstract: A method for using ammonium fluoride solution in a photoelectrochemical etching process of a silicon wafer, comprising steps of: placing a wafer after the pre-etching process into an alcohol solution for activating the surface of wafer and into an ammonium fluoride solution as an etching solution; and illuminating the back of wafer with a halogen light and performing a photoelectrochemical etching process in a potentiostatic.Type: GrantFiled: September 30, 2003Date of Patent: February 8, 2005Assignee: National Central UniversityInventors: Jing-Chie Lin, Chih-Chang Tsai, Chien-Ming Lai, Wen-Chu Hsiao
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Patent number: 6849859Abstract: The figure of a substrate is very precisely measured and a figured-correcting layer is provided on the substrate. The thickness of the figure-correcting layer is locally measured and compared to the first measurement. The local measurement of the figure-correcting layer is accomplished through a variety of methods, including interferometry and fluorescence or ultrasound measurements. Adjustments in the thickness of the figure-correcting layer are made until the top of the figure-correcting layer matches a desired figure specification.Type: GrantFiled: March 21, 2001Date of Patent: February 1, 2005Assignee: Euv Limited Liability CorporationInventors: James A. Folta, Eberhard Spiller
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Patent number: 6835319Abstract: A method of patterning a substrate includes forming a liquid film on the substrate surface and directing laser energy from a laser through the film to etch the substrate surface. Etched material is carried away from the substrate surface via evaporation of the film during the etching. The liquid film may be formed on the substrate surface by jetting a liquid vapor onto the substrate.Type: GrantFiled: February 21, 2002Date of Patent: December 28, 2004Assignee: Data Storage InstituteInventors: Wen Dong Song, Minghui Hong, Yong Feng Lu
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Patent number: 6803322Abstract: The present invention pertains to a more efficient system and method for forming rectifying junction contacts in PIN alloy-semiconductor devices using photoelectrical and chemical etching. The present invention provides a means of creating rectifying junction contacts on alloy-semiconductor devices such as CdTe and CdZnTe, among others. In addition, the present invention also provides a simple and low cost method for revealing wafer surface morphology of alloy-semiconductors, thus providing an efficient and effective means for selecting single grain semiconductor substrates. Further, the present invention provides radiation detectors employing such alloy-semiconductor devices having improved rectifying junctions as the detector element.Type: GrantFiled: December 15, 2000Date of Patent: October 12, 2004Assignee: Science Applications International CorporationInventors: Raulf M. Polichar, Kuo-Tong Chen
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Patent number: 6784007Abstract: The present invention provides a nano-structure which can be applied to various high-function devices. The nano-structure includes an anodically oxidized layer having a plurality of kinds of pores.Type: GrantFiled: September 24, 2002Date of Patent: August 31, 2004Assignee: Canon Kabushiki KaishaInventors: Tatsuya Iwasaki, Tohru Den
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Patent number: 6770568Abstract: To provide for increased differentiation in etch rates, sonication may be used during etching. Such sonication may alter the relative etch rates of portions of a desired layer.Type: GrantFiled: September 12, 2002Date of Patent: August 3, 2004Assignee: Intel CorporationInventor: Justin K. Brask
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Publication number: 20040087175Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.Type: ApplicationFiled: November 2, 2002Publication date: May 6, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Kai-Ming Ching, Chia Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Wen-Hsiang Tseng
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Publication number: 20030194873Abstract: A structure having recesses and projections is provided. A method of manufacturing the structure comprises the steps of preparing a first substrate having a projection, forming a first layer on the projection, transferring the first layer to a second substrate, and forming a recessed/projected surface structure in the second substrate by using the first layer.Type: ApplicationFiled: March 26, 2003Publication date: October 16, 2003Applicant: CANON KABUSHIKI KAISHAInventors: Aya Imada, Tohru Den
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Patent number: 6589882Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.Type: GrantFiled: October 24, 2001Date of Patent: July 8, 2003Assignee: Micron Technology, Inc.Inventors: Michael T. Andreas, Paul A. Morgan
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Patent number: 6586337Abstract: An apparatus for in situ CMP endpoint detection is presented which includes a probe member for emitting and receiving light signals, a transparent plug mounted over the end of the probe, and a support member located about, and slidably engaged with, the outer circumference of the probe. In use, the plug is inserted into an opening in a polishing pad so that the top of the plug is recessed or coplanar with respect to the polishing surface of the pad and the support member is inserted into an opening in a platen such that a seal is formed between the platen and the support member. The probe member, plug, and/or support member may be disposable and replaceable either alone or in combination.Type: GrantFiled: November 9, 2001Date of Patent: July 1, 2003Assignee: SpeedFam-IPEC CorporationInventor: Prabodh J. Parikh