Liquid Phase Etching Patents (Class 438/745)
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Patent number: 11908938Abstract: A substrate processing liquid is used to etch a substrate in which at least either a bottom wall or a side wall forming a trench structure is an etched layer made of metal or a metal compound. The substrate processing liquid includes a chemical liquid containing H2O2 molecules or HO2? functioning as an etchant for etching the metal, and a complex forming agent containing NH4+ and forming a complex with ions of the metal and is adjusted to a pH of 5 or more.Type: GrantFiled: March 4, 2021Date of Patent: February 20, 2024Assignee: SCREEN HOLDINGS CO., LTD.Inventors: Dai Ueda, Yosuke Hanawa
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Patent number: 11881408Abstract: Elements of photonic devices with high aspect ratio patterns are fabricated. A stabilizing catalyst that forms a stable metal-semiconductor alloy allows to etch a substrate in vertical direction even at very low oxidant concentration without external bias or magnetic field. A metal layer on the substrate reacts with the oxidant contained in air and catalyzes the semiconductor etching by the etchant. Air in continuous flow at the metal layer allows to maintain constant the oxidant concentration in proximity of the metal layer. The process can continue for a long time in order to form very high aspect ratio structures in the order of 10,000:1. Once the etched semiconductor structure is formed, the continuous air flow supports the reactant species diffusing through the etched semiconductor structure to maintain a uniform etching rate. The continuous air flow supports the diffusion of reaction by-products to avoid poisoning of the etching reaction.Type: GrantFiled: July 28, 2020Date of Patent: January 23, 2024Assignee: Paul Scherrer InstitutInventors: Lucia Romano, Konstantins Jefimovs, Matias Kagias, Joan Vila Comamala, Marco Stampanoni
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Patent number: 11851597Abstract: An etchant composition, a tackifier, an alkaline solution, a method of removing polyimide and an etching process are provided. The etchant composition includes a tackifier (A) and an alkaline solution (B). The tackifier (A) includes a resin containing a hydroxyl group (a), a surfactant (b) and a first solvent (c1). The alkaline solution (B) includes an alkaline compound (d) and a second solvent (c2).Type: GrantFiled: April 27, 2021Date of Patent: December 26, 2023Assignee: eChem Solutions Corp.Inventors: Yu-Ning Chen, Ming-Che Chung
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Patent number: 11639470Abstract: An etching composition for a silver-containing thin film, the etching composition comprising an inorganic acid compound, a sulfonic acid compound, an organic acid compound, a nitrate, a metal oxidizing agent, an amino acid compound, and water.Type: GrantFiled: July 29, 2021Date of Patent: May 2, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jonghee Park, Hyoung Sik Kim, O Byoung Kwon, Gi-Yong Nam, Kyungchan Min, Suck Jun Lee, Youngmin Kim, Jinhyung Kim, Donghun Lee, Kyu-Hun Lim, Dongmin Jang
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Patent number: 11626294Abstract: A substrate processing method includes etching a substrate having a first film and a second film at a first etching rate; changing an etching rate from the first etching rate to a second etching rate; and etching the substrate at the second etching rate.Type: GrantFiled: February 27, 2020Date of Patent: April 11, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Takumi Honda, Koji Kagawa
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Patent number: 11508610Abstract: Methods and apparatus for supporting a substrate are provided herein. In some embodiments, a substrate support to support a substrate having a given diameter includes: a base ring having an inner diameter less than the given diameter, the base ring having a support surface configured to contact a first surface of the substrate and to form a seal between the support surface and the first surface of the substrate, when disposed atop the base ring; and a clamp ring having an inner diameter less than the given diameter, wherein the clamp ring includes a contact surface proximate the inner diameter configured to contact an upper surface of the substrate, when present, and wherein the clamp ring and the base ring are further configured to provide a bias force toward each other to clamp the substrate in the substrate support.Type: GrantFiled: April 18, 2019Date of Patent: November 22, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Chang Ke, Bonnie Chia, Song-Moon Suh, Cheng-Hsiung Tsai, Yuanhong Guo, Lei Zhou, David Langtry
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Patent number: 11291999Abstract: A method and system for improving throughput of a fluidic system such as a biopolymer analysis system by cleaning accumulated or clogging biopolymer from the fluidic system is disclosed. The method and system utilize a light energy source to photocleave the biopolymer molecules that may accumulate or aggregate in the fluidic system or clog a passageway. The accumulated biopolymer may be exposed to a light energy source for a sufficient period of time such that the biopolymer molecule is dosed with sufficient energy to photocleave the biopolymer molecules, thereby restoring the efficiency of and flow through the system.Type: GrantFiled: August 31, 2015Date of Patent: April 5, 2022Assignee: Bionano Genomics, Inc.Inventors: David Xian Wei Yao, William K. Ridgeway
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Patent number: 11256142Abstract: A liquid crystal display apparatus includes first and second substrates and a liquid crystal layer of vertical alignment type. The first substrate includes pixel electrodes and a first alignment film, whereas the second substrate includes a counter electrode and a second alignment film. Each pixel includes first and second subpixels which allow respectively different voltages to be applied across the liquid crystal layer. Each pixel electrode includes a subpixel electrode provided for each of the first and second subpixels. Each of the first and second subpixels includes first to fourth liquid crystal domains having respectively different reference alignment directions being defined by the first and second alignment films. First to fourth directions, which are the reference alignment directions of the first to fourth liquid crystal domains, each make an angle which is substantially equal to an odd multiple of 45° with respect to the pixel transverse direction.Type: GrantFiled: May 27, 2020Date of Patent: February 22, 2022Assignees: SAKAI DISPLAY PRODUCTS CORPORATION, SHARP KABUSHIKI KAISHAInventors: Mitsuaki Hirata, Fumikazu Shimoshikiryoh
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Patent number: 11211281Abstract: A substrate processing apparatus includes a placing unit, a supply, an embankment and a moving mechanism. The placing unit is configured to place a substrate thereon. The supply is configured to supply a processing liquid onto the substrate placed on the placing unit. The embankment is disposed to surround the substrate placed on the placing unit to suppress an outflow of the processing liquid supplied onto the substrate from the substrate. The moving mechanism is configured to vary a height of the embankment.Type: GrantFiled: December 9, 2019Date of Patent: December 28, 2021Assignee: TOKYO ELECTRON LIMITEDInventor: Kenji Sekiguchi
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Patent number: 11195768Abstract: A manufacturing method of a through electrode substrate includes: a step of preparing a substrate including a first surface and a second surface positioned oppositely to the first surface, and provided with a through hole; a step of providing a sealing layer blocking the through hole on the first surface of the substrate; an electrode forming step of forming a through electrode inside the through hole, the through electrode having a fist part extending along a sidewall of the through hole, and a second part connected to the first part and spreading along the sealing layer; and a step of removing the sealing layer.Type: GrantFiled: June 2, 2017Date of Patent: December 7, 2021Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Hiroshi Kudo, Takamasa Takano
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Patent number: 11168253Abstract: A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.Type: GrantFiled: January 6, 2020Date of Patent: November 9, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., DONGWOO FINE-CHEM CO., LTD.Inventors: Changsu Jeon, Jungmin Oh, Hyosan Lee, Hoon Han, Jinkyu Roh, Hyojoong Yoon, Dongwun Shin
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Patent number: 11152219Abstract: A method of selectively removing aluminium oxide or nitride material from a microelectronic substrate, the method comprising contacting the material with an aqueous etching composition comprising: an etchant comprising a source of fluoride; and a metal corrosion inhibitor; wherein the composition has a pH in the range of from 3 to 8. Aqueous etching compositions and uses are also described.Type: GrantFiled: June 17, 2019Date of Patent: October 19, 2021Assignee: Entegris, Inc.Inventors: Chieh Ju Wang, Hsing-Chen Wu, Chia-Jung Hsu
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Patent number: 11142694Abstract: An etchant composition and a method of fabricating a semiconductor device, the composition including an inorganic acid; about 0.01 parts by weight to about 0.5 parts by weight of colloidal silica; about 0.01 parts by weight to about 30 parts by weight of an ammonium-based additive; and about 20 parts by weight to about 50 parts by weight of a solvent, all parts by weight being based on 100 parts by weight of the inorganic acid.Type: GrantFiled: September 10, 2019Date of Patent: October 12, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., Soulbrain Co., Ltd.Inventors: Jung-ah Kim, Young-chan Kim, Hyo-san Lee, Hoon Han, Jin-uk Lee, Jung-hun Lim, Ik-hee Kim
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Patent number: 11062978Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.Type: GrantFiled: September 30, 2019Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
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Patent number: 11021791Abstract: A film forming apparatus is provided. The film forming apparatus includes an inner tube configured to accommodate a workpiece and having a first space defined by a side wall of the inner tube and an upper wall of the inner tube that is connected to the side wall, an exhaust pipe fluidly connected to the first space, at least one top hole defined in the upper wall of the inner tube, at least one side hole defined in the side wall of the inner tube, an outer tube surrounding the inner tube, and a reaction gas supply pipe fluidly connected to a second space defined by and formed between the inner tube and the outer tube, wherein the reaction gas supply pipe is positioned higher vertically than the exhaust pipe.Type: GrantFiled: October 23, 2018Date of Patent: June 1, 2021Inventor: Hyun Ho Chio
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Patent number: 10699912Abstract: A computer program product and methods are provided for semiconductor processing. The method includes forming a masking layer on a first region. The method also includes implanting a second region. The method further includes depositing a protective layer over the first region and the second region, with the protective layer being selectively etchable to the masking layer and thicker over the second region. The additional includes removing the protective layer from the first region. The method also includes etching the masking layer exposing a bottom layer. The method further includes removing the protective layer from the second region and the bottom layer from the first region.Type: GrantFiled: October 12, 2018Date of Patent: June 30, 2020Assignee: International Business Machines CorporationInventors: Indira Seshadri, Ekmini A. De Silva
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Patent number: 10651061Abstract: A substrate processing apparatus includes a processing unit and a control unit. The processing unit is configured to perform an etching processing by immersing a substrate in a processing liquid containing phosphoric acid and a silicon-containing compound. The control unit is configured to control the processing liquid such that the substrate is processed, in a first processing time of the etching processing, with the processing liquid having a first phosphoric acid concentration and a first silicon concentration, and the substrate is processed, in a second processing time later than the first processing time, with the processing liquid having a second preset phosphoric acid concentration lower than the first phosphoric acid concentration and a second preset silicon concentration lower than the first silicon concentration or with the processing liquid having the second preset phosphoric acid concentration and the first silicon concentration.Type: GrantFiled: October 18, 2018Date of Patent: May 12, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Hiroki Ohno, Takao Inada, Hisashi Kawano
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Patent number: 10497719Abstract: A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.Type: GrantFiled: January 25, 2018Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Joon Goo Hong, Kang Ill Seo, Borna J. Obradovic
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Patent number: 10459340Abstract: A developing method includes: forming a liquid pool of a diluted developing solution diluted with pure water in a central portion of a substrate; forming a liquid film of the diluted developing solution on a surface of the substrate by accelerating rotation of the substrate to diffuse the liquid pool of the diluted developing solution on the entire surface of the substrate; and then supplying a developing solution onto the substrate. Supplying a developing solution includes: supplying the developing solution from a developing solution supply nozzle having a liquid contact surface while securing a gap having a predetermined size between the developing solution supply nozzle and the substrate; and moving the developing solution supply nozzle in a radial direction passing through a center of the substrate while forming a liquid pool of the developing solution between the substrate and the liquid contact surface of the developing solution supply nozzle.Type: GrantFiled: November 27, 2015Date of Patent: October 29, 2019Assignee: TOKYO ELECTRON LIMITEDInventors: Koshi Muta, Hideharu Kyoda, Minoru Kubota
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Patent number: 10388729Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.Type: GrantFiled: May 16, 2016Date of Patent: August 20, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: John Zhang, Lawrence Clevenger, Kangguo Cheng, Balasubramanian Haran
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Patent number: 10347498Abstract: Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.Type: GrantFiled: March 16, 2018Date of Patent: July 9, 2019Assignee: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventors: Chih-yu Hsu, Peng Shen, Nathan Stafford
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Patent number: 10292275Abstract: A method of manufacturing a glass substrate that has a through hole, includes (1) forming an initial hole in a glass substrate by irradiating laser light from a first surface side of the glass substrate; (2) performing a first etching process using a first etching solution to form, from the initial hole, a first through hole that extends from a first opening formed at a first surface to a second opening formed at a second surface, and to make a ratio “d1/Rt1” of a thickness “d1” of the glass substrate with respect to a diameter “Rt1” of the first opening to be within a range between 10 to 20; and (3) performing a second etching process to enlarge the first through hole using a second etching solution, whose etching rate with respect to the glass substrate is faster than that of the first etching solution.Type: GrantFiled: April 5, 2017Date of Patent: May 14, 2019Assignee: AGC INC.Inventor: Mamoru Isobe
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Patent number: 10280325Abstract: A jet ink composition, a jet ink coating method and a resulting jet ink coated article are all predicated upon the jet ink composition which includes in addition to a particulate pigment material and a solvent composition a resin composition. The resin composition includes an uncured silicone resin, an uncured epoxy resin and an uncured melamine resin. Upon thermal cure the uncured resin composition forms a cured resin composition with superior adhesion to substrates such as but not limited to glass substrates, ceramic substrates and metal oxide substrates.Type: GrantFiled: May 17, 2017Date of Patent: May 7, 2019Assignee: CORNING INCORPORATEDInventors: Tzu-Han Chen, Ruei-ming Huang, Yongsheng Yan
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Patent number: 10032661Abstract: A semiconductor device, method, and tool of manufacture includes a semiconductor manufacturing tool. The semiconductor manufacturing tool includes push pins in a chuck and an edge ring over the chuck. The push pins are configured to hold a wafer, and are operable to vary a height of the wafer with respect to the chuck. The edge ring has a first width at a base proximate the chuck, and a second width at a point distal the chuck. The first width is greater than the second width. A distance from the wafer to the edge ring varies when the push pins vary the height of the wafer with respect to the chuck.Type: GrantFiled: November 18, 2016Date of Patent: July 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Je Chuang, Yu-Lin Sung, Yi-Wei Chiu, Tzu-Chan Weng
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Patent number: 10032664Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.Type: GrantFiled: June 6, 2016Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 9881818Abstract: A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching solution by dissolving titanium in an ammonia-hydrogen peroxide solution in advance before use of the ammonia-hydrogen peroxide solution for etching. The flow step flows the etching solution after the preparation step so that a concentration of the etching solution in a processing bath is constant. The processing step etches a metal film on a semiconductor wafer with the etching solution by putting in the processing bath the semiconductor wafer having a resist film and the metal film after the flow step is started. The metal film is preferably formed of titanium, and a temperature of the etching solution is preferably adjusted by flowing the etching solution so that the etching solution flows via a temperature controller.Type: GrantFiled: September 19, 2014Date of Patent: January 30, 2018Assignee: Mitsubishi Electric CorporationInventors: Nobuaki Yamanaka, Daisuke Chikamori, Shinichirou Katsuki
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Patent number: 9831088Abstract: A removal composition and process for selectively removing a first metal gate material (e.g., titanium nitride) relative to a second metal gate material (e.g., tantalum nitride) from a microelectronic device having said material thereon. The removal composition can include fluoride or alternatively be substantially devoid of fluoride. The substrate preferably comprises a high-k/metal gate integration scheme.Type: GrantFiled: October 6, 2011Date of Patent: November 28, 2017Assignee: ENTEGRIS, INC.Inventors: Tianniu Chen, Nicole E. Thomas, Steven Lippy, Jeffrey A. Barnes, Emanuel I. Cooper, Peng Zhang
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Patent number: 9799530Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; supplying a mixture of phosphoric acid and a silicon-containing material into a process tank, in which the mixture has a predetermined silicon concentration; and submerging the wafer into the mixture within the process tank to remove the silicon nitride. An etching apparatus of selectively removing silicon nitride is also provided.Type: GrantFiled: October 17, 2013Date of Patent: October 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Hsueh Changchien, Yu-Ming Lee, Chi-Ming Yang
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Patent number: 9779979Abstract: An apparatus for processing wafer-shaped articles comprises a spin chuck adapted to hold and spin a wafer-shaped article of a predetermined diameter during a processing operation. A liquid collector surrounds the spin chuck, and comprises a first inner surface. The first inner surface comprises a first conductive material. The collector further comprises a first conductive pathway for grounding the first conductive material.Type: GrantFiled: February 24, 2014Date of Patent: October 3, 2017Assignee: LAM RESEARCH AGInventors: Reinhold Schwarzenbacher, Milan Pliska
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Patent number: 9773915Abstract: A semiconductor device using oxide semiconductor with favorable electrical characteristics, or a highly reliable semiconductor device is provided. A semiconductor device is manufactured by: forming an oxide semiconductor layer over an insulating surface; forming source and drain electrodes over the oxide semiconductor layer; forming an insulating film and a conductive film in this order over the oxide semiconductor layer and the source and drain electrodes; etching part of the conductive film and insulating film to form a gate electrode and a gate insulating layer, and etching part of the upper portions of the source and drain electrodes to form a first covering layer containing a constituent element of the source and drain electrodes and in contact with the side surface of the gate insulating layer; oxidizing the first covering layer to form a second covering layer; and forming a protective insulating layer containing an oxide over the second covering layer.Type: GrantFiled: June 2, 2014Date of Patent: September 26, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Suguru Hondo
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Patent number: 9766540Abstract: A photomask and a method of forming the same, the photomask including a transparent substrate; a light shielding pattern on the transparent substrate, the light shielding pattern including molybdenum and silicon; and an etch stop layer covering at least a sidewall of the light shielding pattern, wherein the etch stop layer has an etch rate lower than an etch rate of the light shielding pattern with respect to an ammonia-based cleaning solution.Type: GrantFiled: December 22, 2015Date of Patent: September 19, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Keun Oh, Hyungho Ko, Inkyun Shin, Jaehyuck Choi, JunYoul Choi
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Patent number: 9685450Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.Type: GrantFiled: March 17, 2016Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
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Patent number: 9676661Abstract: The present invention provides an etching method of a glass substrate and a wet etching apparatus thereof. The etching method of the glass substrate comprises steps of: providing a glass substrate (1) to be etched, a wet bench (3), etchants and a supply line (7); setting a tank (9) in the wet bench (3); filling in the tank (9) with a predetermined amount of the etchants through the supply line (7); delivering the glass substrate (1) to be etched into the wet bench (3); raising the tank (9) until the glass substrate (1) is completely immersed with the etchants in the tank (9); lowering the tank (9) to expose the glass substrate (1) after a predetermined soaking time. The etching method of the glass substrate is simple and easy for operation. It is capable of shortening the etching process time and raising the production efficiency.Type: GrantFiled: July 14, 2014Date of Patent: June 13, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Jia Li
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Patent number: 9679869Abstract: This disclosure relates to a transmission line for high performance radio frequency (RF) applications. One such transmission line can include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer can have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the transmission line can include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer.Type: GrantFiled: May 4, 2012Date of Patent: June 13, 2017Assignee: Skyworks Solutions, Inc.Inventors: Sandra Louise Petty-Weeks, Guohao Zhang, Hardik Bhupendra Modi
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Patent number: 9673068Abstract: A method for processing a substrate with a porous film having a porous structure formed on a surface layer thereof includes the following a) and b) steps. The a) step is a step of mixing a first processing solution containing water with gas to generate droplets of the first processing solution and injecting the droplets of the first processing solution to the porous film. In addition, the b) step is a step of, after the a) step, mixing a second processing solution which is an organic solvent having higher volatility than the first processing solution with the gas to generate droplets of the second processing solution and injecting the droplets of the second processing solution to the porous film.Type: GrantFiled: December 15, 2014Date of Patent: June 6, 2017Assignee: SCREEN Holdings Co., LtdInventor: Kenji Kobayashi
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Patent number: 9669460Abstract: A method for finely powdering tungsten powder, which includes dispersing tungsten powder in an aqueous solution containing an oxidizing agent to form an oxide film in the surface of the tungsten powder and removing the oxide film with an alkaline aqueous solution. Also disclosed is a method for producing fine tungsten powder, which includes obtaining tungsten powder having an average particle size of 0.05 to 0.5 ?m by a process including the above method for finely powdering. Also disclosed is a tungsten powder having an average particle size of 0.05 to 0.5 ?m, in which the dMS value (product of an average particle size d (?m), true density M (g/cm3) and BET specific surface area S (m2/g)) is within the range of 6±0.8.Type: GrantFiled: August 29, 2012Date of Patent: June 6, 2017Assignee: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
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Patent number: 9650570Abstract: Compositions for etching polysilicon including aqueous compositions containing nitric acid, ammonium fluoride, and poly-carboxylic acid.Type: GrantFiled: March 30, 2015Date of Patent: May 16, 2017Assignee: Micron Technology, Inc.Inventors: Jerome A. Imonigie, Prashant Raghu
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Patent number: 9630834Abstract: An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.Type: GrantFiled: June 16, 2014Date of Patent: April 25, 2017Assignee: InSense, Inc.Inventors: Noureddine Tayebi, Hao Luo
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Patent number: 9627234Abstract: A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path.Type: GrantFiled: March 13, 2014Date of Patent: April 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Min Huang, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 9607905Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.Type: GrantFiled: September 2, 2015Date of Patent: March 28, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Mitsuhiko Sakai, Susumu Yoshimoto
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Patent number: 9575411Abstract: A developing apparatus includes: a substrate holder that hold a substrate horizontally; a developer nozzle that supplies a developer onto the substrate to form a liquid puddle; a turning flow generation mechanism including a rotary member that rotates about an axis perpendicular to the substrate while the rotary member is being in contact with the liquid puddle thereby to generate a turning flow in the liquid puddle of the developer formed on the substrate; and a moving mechanism for moving the turning flow generation mechanism along a surface of the substrate. The line-width uniformity of a pattern can be improved by forming turning flows in a desired region of the substrate and stirring the developer.Type: GrantFiled: August 4, 2014Date of Patent: February 21, 2017Assignee: Tokyo Electron LimitedInventors: Kousuke Yoshihara, Hideharu Kyouda, Koshi Muta, Taro Yamamoto, Yasushi Takiguchi
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Patent number: 9568829Abstract: A developing method includes: horizontally holding an exposed substrate by a substrate holder; forming a liquid puddle on a part of the substrate, by supplying a developer from a developer nozzle; rotating the substrate; spreading the liquid puddle on a whole surface of the substrate, by moving the developer nozzle such that a supply position of the developer on the rotating substrate is moved in a radial direction of the substrate; bringing, simultaneously with the spreading of the liquid puddle on the whole surface of the substrate, a contact part into contact with the liquid puddle, the contact part being configured to be moved together with the developer nozzle and having a surface opposed to the substrate which is smaller than the surface of the substrate. According to this method, an amount of liquid falling down to the outside of the substrate can be inhibited. In addition, since the rotating speed of the substrate can be decreased, spattering of the developer can be inhibited.Type: GrantFiled: August 1, 2014Date of Patent: February 14, 2017Assignee: Tokyo Electron LimitedInventors: Kousuke Yoshihara, Hideharu Kyouda, Koshi Muta, Taro Yamamoto, Yasushi Takiguchi, Masahiro Fukuda
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Patent number: 9463485Abstract: A method of forming a substrate for a fluid ejection device includes forming an opening through the substrate, with the opening having a long axis profile and a short axis profile, and with the long axis profile including a first portion extending from a minimum dimension of the long axis profile to a first side of the substrate, and a second portion including and extending from the minimum dimension of the long axis profile to a second side of the substrate opposite the first side. The method also includes forming a protective layer on sidewalls of the second portion of the long axis profile of the opening and excluding the protective layer from sidewalls of the first portion of the long axis profile of the opening.Type: GrantFiled: April 24, 2012Date of Patent: October 11, 2016Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Rio Rivas, Corey Deyo, Ed Friesen
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Patent number: 9466480Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.Type: GrantFiled: November 4, 2014Date of Patent: October 11, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Chueh-Yang Liu, Neng-Hui Yang
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Patent number: 9419206Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.Type: GrantFiled: July 25, 2013Date of Patent: August 16, 2016Assignee: MagnaChip Semiconductor, Ltd.Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
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Patent number: 9384988Abstract: A structure includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate, and a cap over a gate electrode of the gate structure. Top surfaces of the dielectric layer and gate electrode are co-planar. The gate structure extends a gate lateral distance between first and second gate structure sidewalls. The cap extends between first and second cap sidewalls. A first cap portion extends from a midline of the gate structure laterally towards the first gate structure sidewall and to the first cap sidewall a first cap lateral distance, and a second cap portion extends from the midline laterally towards the second gate structure sidewall and to the second cap sidewall a second cap lateral distance. The first cap lateral distance and the second cap lateral distance are at least half of the gate lateral distance.Type: GrantFiled: November 19, 2013Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Han Lin, Jr-Jung Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 9385197Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H2SO4, HCl, HF, H3PO4, or NH4OH and (b) a second component, including propylene carbonate, ethylene carbonate, diethyl carbonate, acetonitrile, or a combination thereof.Type: GrantFiled: October 28, 2014Date of Patent: July 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Andrew Joseph Kelly, Yusuke Oniki
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Patent number: 9349634Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.Type: GrantFiled: February 21, 2014Date of Patent: May 24, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chen-Hung Lu, Chie-Iuan Lin, Yen-Sen Wang, Ming-Yi Lin, Jyh-Kang Ting
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Patent number: 9287176Abstract: An optical device including a substrate formed of a light transmitting material and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Each side surface of the substrate has a corrugated sectional shape such that a plurality of concave portions and convex portions are alternately formed.Type: GrantFiled: August 28, 2014Date of Patent: March 15, 2016Assignee: Disco CorporationInventor: Kota Fukaya
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Patent number: RE48407Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.Type: GrantFiled: February 10, 2017Date of Patent: January 26, 2021Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOISInventors: Xiuling Li, Matthew T. Dejarld, Parsian Katal Mohseni, Jae Cheol Shin, Winston Chern