Liquid Phase Etching Patents (Class 438/745)
  • Patent number: 10699912
    Abstract: A computer program product and methods are provided for semiconductor processing. The method includes forming a masking layer on a first region. The method also includes implanting a second region. The method further includes depositing a protective layer over the first region and the second region, with the protective layer being selectively etchable to the masking layer and thicker over the second region. The additional includes removing the protective layer from the first region. The method also includes etching the masking layer exposing a bottom layer. The method further includes removing the protective layer from the second region and the bottom layer from the first region.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini A. De Silva
  • Patent number: 10651061
    Abstract: A substrate processing apparatus includes a processing unit and a control unit. The processing unit is configured to perform an etching processing by immersing a substrate in a processing liquid containing phosphoric acid and a silicon-containing compound. The control unit is configured to control the processing liquid such that the substrate is processed, in a first processing time of the etching processing, with the processing liquid having a first phosphoric acid concentration and a first silicon concentration, and the substrate is processed, in a second processing time later than the first processing time, with the processing liquid having a second preset phosphoric acid concentration lower than the first phosphoric acid concentration and a second preset silicon concentration lower than the first silicon concentration or with the processing liquid having the second preset phosphoric acid concentration and the first silicon concentration.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 12, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Ohno, Takao Inada, Hisashi Kawano
  • Patent number: 10497719
    Abstract: A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Goo Hong, Kang Ill Seo, Borna J. Obradovic
  • Patent number: 10459340
    Abstract: A developing method includes: forming a liquid pool of a diluted developing solution diluted with pure water in a central portion of a substrate; forming a liquid film of the diluted developing solution on a surface of the substrate by accelerating rotation of the substrate to diffuse the liquid pool of the diluted developing solution on the entire surface of the substrate; and then supplying a developing solution onto the substrate. Supplying a developing solution includes: supplying the developing solution from a developing solution supply nozzle having a liquid contact surface while securing a gap having a predetermined size between the developing solution supply nozzle and the substrate; and moving the developing solution supply nozzle in a radial direction passing through a center of the substrate while forming a liquid pool of the developing solution between the substrate and the liquid contact surface of the developing solution supply nozzle.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: October 29, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koshi Muta, Hideharu Kyoda, Minoru Kubota
  • Patent number: 10388729
    Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John Zhang, Lawrence Clevenger, Kangguo Cheng, Balasubramanian Haran
  • Patent number: 10347498
    Abstract: Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 9, 2019
    Assignee: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Chih-yu Hsu, Peng Shen, Nathan Stafford
  • Patent number: 10292275
    Abstract: A method of manufacturing a glass substrate that has a through hole, includes (1) forming an initial hole in a glass substrate by irradiating laser light from a first surface side of the glass substrate; (2) performing a first etching process using a first etching solution to form, from the initial hole, a first through hole that extends from a first opening formed at a first surface to a second opening formed at a second surface, and to make a ratio “d1/Rt1” of a thickness “d1” of the glass substrate with respect to a diameter “Rt1” of the first opening to be within a range between 10 to 20; and (3) performing a second etching process to enlarge the first through hole using a second etching solution, whose etching rate with respect to the glass substrate is faster than that of the first etching solution.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: May 14, 2019
    Assignee: AGC INC.
    Inventor: Mamoru Isobe
  • Patent number: 10280325
    Abstract: A jet ink composition, a jet ink coating method and a resulting jet ink coated article are all predicated upon the jet ink composition which includes in addition to a particulate pigment material and a solvent composition a resin composition. The resin composition includes an uncured silicone resin, an uncured epoxy resin and an uncured melamine resin. Upon thermal cure the uncured resin composition forms a cured resin composition with superior adhesion to substrates such as but not limited to glass substrates, ceramic substrates and metal oxide substrates.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 7, 2019
    Assignee: CORNING INCORPORATED
    Inventors: Tzu-Han Chen, Ruei-ming Huang, Yongsheng Yan
  • Patent number: 10032664
    Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10032661
    Abstract: A semiconductor device, method, and tool of manufacture includes a semiconductor manufacturing tool. The semiconductor manufacturing tool includes push pins in a chuck and an edge ring over the chuck. The push pins are configured to hold a wafer, and are operable to vary a height of the wafer with respect to the chuck. The edge ring has a first width at a base proximate the chuck, and a second width at a point distal the chuck. The first width is greater than the second width. A distance from the wafer to the edge ring varies when the push pins vary the height of the wafer with respect to the chuck.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Je Chuang, Yu-Lin Sung, Yi-Wei Chiu, Tzu-Chan Weng
  • Patent number: 9881818
    Abstract: A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching solution by dissolving titanium in an ammonia-hydrogen peroxide solution in advance before use of the ammonia-hydrogen peroxide solution for etching. The flow step flows the etching solution after the preparation step so that a concentration of the etching solution in a processing bath is constant. The processing step etches a metal film on a semiconductor wafer with the etching solution by putting in the processing bath the semiconductor wafer having a resist film and the metal film after the flow step is started. The metal film is preferably formed of titanium, and a temperature of the etching solution is preferably adjusted by flowing the etching solution so that the etching solution flows via a temperature controller.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: January 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuaki Yamanaka, Daisuke Chikamori, Shinichirou Katsuki
  • Patent number: 9831088
    Abstract: A removal composition and process for selectively removing a first metal gate material (e.g., titanium nitride) relative to a second metal gate material (e.g., tantalum nitride) from a microelectronic device having said material thereon. The removal composition can include fluoride or alternatively be substantially devoid of fluoride. The substrate preferably comprises a high-k/metal gate integration scheme.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 28, 2017
    Assignee: ENTEGRIS, INC.
    Inventors: Tianniu Chen, Nicole E. Thomas, Steven Lippy, Jeffrey A. Barnes, Emanuel I. Cooper, Peng Zhang
  • Patent number: 9799530
    Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; supplying a mixture of phosphoric acid and a silicon-containing material into a process tank, in which the mixture has a predetermined silicon concentration; and submerging the wafer into the mixture within the process tank to remove the silicon nitride. An etching apparatus of selectively removing silicon nitride is also provided.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Hsueh Changchien, Yu-Ming Lee, Chi-Ming Yang
  • Patent number: 9779979
    Abstract: An apparatus for processing wafer-shaped articles comprises a spin chuck adapted to hold and spin a wafer-shaped article of a predetermined diameter during a processing operation. A liquid collector surrounds the spin chuck, and comprises a first inner surface. The first inner surface comprises a first conductive material. The collector further comprises a first conductive pathway for grounding the first conductive material.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 3, 2017
    Assignee: LAM RESEARCH AG
    Inventors: Reinhold Schwarzenbacher, Milan Pliska
  • Patent number: 9773915
    Abstract: A semiconductor device using oxide semiconductor with favorable electrical characteristics, or a highly reliable semiconductor device is provided. A semiconductor device is manufactured by: forming an oxide semiconductor layer over an insulating surface; forming source and drain electrodes over the oxide semiconductor layer; forming an insulating film and a conductive film in this order over the oxide semiconductor layer and the source and drain electrodes; etching part of the conductive film and insulating film to form a gate electrode and a gate insulating layer, and etching part of the upper portions of the source and drain electrodes to form a first covering layer containing a constituent element of the source and drain electrodes and in contact with the side surface of the gate insulating layer; oxidizing the first covering layer to form a second covering layer; and forming a protective insulating layer containing an oxide over the second covering layer.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: September 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Suguru Hondo
  • Patent number: 9766540
    Abstract: A photomask and a method of forming the same, the photomask including a transparent substrate; a light shielding pattern on the transparent substrate, the light shielding pattern including molybdenum and silicon; and an etch stop layer covering at least a sidewall of the light shielding pattern, wherein the etch stop layer has an etch rate lower than an etch rate of the light shielding pattern with respect to an ammonia-based cleaning solution.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Keun Oh, Hyungho Ko, Inkyun Shin, Jaehyuck Choi, JunYoul Choi
  • Patent number: 9685450
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Patent number: 9676661
    Abstract: The present invention provides an etching method of a glass substrate and a wet etching apparatus thereof. The etching method of the glass substrate comprises steps of: providing a glass substrate (1) to be etched, a wet bench (3), etchants and a supply line (7); setting a tank (9) in the wet bench (3); filling in the tank (9) with a predetermined amount of the etchants through the supply line (7); delivering the glass substrate (1) to be etched into the wet bench (3); raising the tank (9) until the glass substrate (1) is completely immersed with the etchants in the tank (9); lowering the tank (9) to expose the glass substrate (1) after a predetermined soaking time. The etching method of the glass substrate is simple and easy for operation. It is capable of shortening the etching process time and raising the production efficiency.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: June 13, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Jia Li
  • Patent number: 9679869
    Abstract: This disclosure relates to a transmission line for high performance radio frequency (RF) applications. One such transmission line can include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer can have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the transmission line can include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: June 13, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Sandra Louise Petty-Weeks, Guohao Zhang, Hardik Bhupendra Modi
  • Patent number: 9669460
    Abstract: A method for finely powdering tungsten powder, which includes dispersing tungsten powder in an aqueous solution containing an oxidizing agent to form an oxide film in the surface of the tungsten powder and removing the oxide film with an alkaline aqueous solution. Also disclosed is a method for producing fine tungsten powder, which includes obtaining tungsten powder having an average particle size of 0.05 to 0.5 ?m by a process including the above method for finely powdering. Also disclosed is a tungsten powder having an average particle size of 0.05 to 0.5 ?m, in which the dMS value (product of an average particle size d (?m), true density M (g/cm3) and BET specific surface area S (m2/g)) is within the range of 6±0.8.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: June 6, 2017
    Assignee: SHOWA DENKO K.K.
    Inventors: Kazumi Naito, Shoji Yabe
  • Patent number: 9673068
    Abstract: A method for processing a substrate with a porous film having a porous structure formed on a surface layer thereof includes the following a) and b) steps. The a) step is a step of mixing a first processing solution containing water with gas to generate droplets of the first processing solution and injecting the droplets of the first processing solution to the porous film. In addition, the b) step is a step of, after the a) step, mixing a second processing solution which is an organic solvent having higher volatility than the first processing solution with the gas to generate droplets of the second processing solution and injecting the droplets of the second processing solution to the porous film.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 6, 2017
    Assignee: SCREEN Holdings Co., Ltd
    Inventor: Kenji Kobayashi
  • Patent number: 9650570
    Abstract: Compositions for etching polysilicon including aqueous compositions containing nitric acid, ammonium fluoride, and poly-carboxylic acid.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu
  • Patent number: 9630834
    Abstract: An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: April 25, 2017
    Assignee: InSense, Inc.
    Inventors: Noureddine Tayebi, Hao Luo
  • Patent number: 9627234
    Abstract: A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Min Huang, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9607905
    Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: March 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuhiko Sakai, Susumu Yoshimoto
  • Patent number: 9575411
    Abstract: A developing apparatus includes: a substrate holder that hold a substrate horizontally; a developer nozzle that supplies a developer onto the substrate to form a liquid puddle; a turning flow generation mechanism including a rotary member that rotates about an axis perpendicular to the substrate while the rotary member is being in contact with the liquid puddle thereby to generate a turning flow in the liquid puddle of the developer formed on the substrate; and a moving mechanism for moving the turning flow generation mechanism along a surface of the substrate. The line-width uniformity of a pattern can be improved by forming turning flows in a desired region of the substrate and stirring the developer.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: February 21, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kousuke Yoshihara, Hideharu Kyouda, Koshi Muta, Taro Yamamoto, Yasushi Takiguchi
  • Patent number: 9568829
    Abstract: A developing method includes: horizontally holding an exposed substrate by a substrate holder; forming a liquid puddle on a part of the substrate, by supplying a developer from a developer nozzle; rotating the substrate; spreading the liquid puddle on a whole surface of the substrate, by moving the developer nozzle such that a supply position of the developer on the rotating substrate is moved in a radial direction of the substrate; bringing, simultaneously with the spreading of the liquid puddle on the whole surface of the substrate, a contact part into contact with the liquid puddle, the contact part being configured to be moved together with the developer nozzle and having a surface opposed to the substrate which is smaller than the surface of the substrate. According to this method, an amount of liquid falling down to the outside of the substrate can be inhibited. In addition, since the rotating speed of the substrate can be decreased, spattering of the developer can be inhibited.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 14, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kousuke Yoshihara, Hideharu Kyouda, Koshi Muta, Taro Yamamoto, Yasushi Takiguchi, Masahiro Fukuda
  • Patent number: 9463485
    Abstract: A method of forming a substrate for a fluid ejection device includes forming an opening through the substrate, with the opening having a long axis profile and a short axis profile, and with the long axis profile including a first portion extending from a minimum dimension of the long axis profile to a first side of the substrate, and a second portion including and extending from the minimum dimension of the long axis profile to a second side of the substrate opposite the first side. The method also includes forming a protective layer on sidewalls of the second portion of the long axis profile of the opening and excluding the protective layer from sidewalls of the first portion of the long axis profile of the opening.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: October 11, 2016
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Rio Rivas, Corey Deyo, Ed Friesen
  • Patent number: 9466480
    Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Chueh-Yang Liu, Neng-Hui Yang
  • Patent number: 9419206
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: August 16, 2016
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
  • Patent number: 9385197
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H2SO4, HCl, HF, H3PO4, or NH4OH and (b) a second component, including propylene carbonate, ethylene carbonate, diethyl carbonate, acetonitrile, or a combination thereof.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Andrew Joseph Kelly, Yusuke Oniki
  • Patent number: 9384988
    Abstract: A structure includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate, and a cap over a gate electrode of the gate structure. Top surfaces of the dielectric layer and gate electrode are co-planar. The gate structure extends a gate lateral distance between first and second gate structure sidewalls. The cap extends between first and second cap sidewalls. A first cap portion extends from a midline of the gate structure laterally towards the first gate structure sidewall and to the first cap sidewall a first cap lateral distance, and a second cap portion extends from the midline laterally towards the second gate structure sidewall and to the second cap sidewall a second cap lateral distance. The first cap lateral distance and the second cap lateral distance are at least half of the gate lateral distance.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Jr-Jung Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 9349634
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: May 24, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chen-Hung Lu, Chie-Iuan Lin, Yen-Sen Wang, Ming-Yi Lin, Jyh-Kang Ting
  • Patent number: 9287176
    Abstract: An optical device including a substrate formed of a light transmitting material and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Each side surface of the substrate has a corrugated sectional shape such that a plurality of concave portions and convex portions are alternately formed.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 15, 2016
    Assignee: Disco Corporation
    Inventor: Kota Fukaya
  • Patent number: 9240505
    Abstract: A method of etching capable of rapidly and flatly performing wet etching on a Si substrate using fluonitric acid represented by HF(a)HNO3(b)H2O(c) (where the unit of a, b and c is wt % and a+b+c=100). The etching rate of an SiO2 layer with the highly concentrated fluonitric acid is significantly lowered by the appropriate selection of its composition as compared with the etching rate of the Si substrate, and etch the Si substrate until the SiO2 layer is exposed. In this way, it is possible to rapidly etch the Si substrate and significantly enhance the flatness of the etched surface.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: January 19, 2016
    Assignee: TOHOKU UNIVERSITY
    Inventors: Tadahiro Ohmi, Tomotsugu Ohashi, Kazuhiro Yoshikawa, Tatsuro Yoshida, Teppei Uchimura, Kazuki Soeda, Shigetoshi Sugawa
  • Patent number: 9236529
    Abstract: A semiconductor light emitting element in which changes in light distribution characteristics due to inclination angle of side surfaces are suppressed. The semiconductor light emitting element includes a semiconductor structure having a light extracting surface as its upper surface; a reflecting layer disposed on side surfaces of the semiconductor structure; and a positive electrode and a negative electrode disposed on a lower surface of the semiconductor structure. Side surfaces of the semiconductor structure are inclined, expanding upward from the lower surface to the upper surface. At least a portion of each side surface includes a plurality of protrusions, a plurality of recesses, or a combination thereof.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 12, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Akiyoshi Kinouchi, Ryohei Hirose, Hirofumi Nogami
  • Patent number: 9177827
    Abstract: Disclosed are an etchant which is used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel, and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant to be used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode, including hydrogen peroxide, an organic acid, and an organic phosphonic acid, wherein the organic acid is at least one member selected from citric acid and malic acid; a content of hydrogen peroxide is from 0.75 to 12% by mass; a content of the organic acid is from 0.75 to 25% by mass; and a content of the organic phosphonic acid is from 0.0005 to 1% by mass, and a method for manufacturing a semiconductor device using the etchant.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: November 3, 2015
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventor: Akira Hosomi
  • Patent number: 9159560
    Abstract: A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: October 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Woo Seo
  • Patent number: 9158203
    Abstract: Compositions useful for the selective removal of silicon nitride materials relative to poly-silicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon. The removal compositions include fluorosilicic acid, silicic acid, and at least one organic solvent. Typical process temperatures are less than about 100° C. and typical selectivity for nitride versus oxide etch is about 200:1 to about 2000:1. Under typical process conditions, nickel-based silicides as well as titanium and tantalum nitrides are largely unaffected, and polysilicon etch rates are less than about 1 ? min?1.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 13, 2015
    Assignee: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventors: Emanuel I. Cooper, Eileen Sparks, William R. Bowers, Mark A. Biscotto, Kevin P. Yanders, Michael B. Korzenski, Prerna Sonthalia, Nicole E. Thomas
  • Patent number: 9159630
    Abstract: Approaches for providing a single spacer, double hardmask dual-epi FinFET are disclosed. Specifically, at least one approach for providing the FinFET includes: forming a set of spacers along each sidewall of a plurality of fins of the FinFET device; forming a first ultra-thin hardmask over the plurality of fins; implanting the first ultra-thin hardmask over a first set of fins from the plurality of fins; removing the first ultra-thin hardmask over a second set of fins from the plurality of fins untreated by the implant; forming an epitaxial (epi) layer over the second set of fins; forming a second ultra-thin hardmask over the FinFET device; implanting the second ultra-thin hardmask; removing the second ultra-thin hardmask over the first set of fins; and growing an epi layer over the first set of fins.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Dae Geun Yang, Dae-han Choi
  • Patent number: 9139771
    Abstract: In order to provide a copper oxide etchant and an etching method using the same capable of selectively etching exposure/non-exposure portions when laser light exposure is performed by using copper oxide as a thermal-reactive resist material, the copper oxide etchant for selectively etching copper oxides having different oxidation numbers in a copper oxide-containing layer containing the copper oxide as a main component contains at least a chelating agent or salts thereof.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: September 22, 2015
    Assignee: ASAHI KASEI E-MATERIALS CORPORATION
    Inventors: Norikiyo Nakagawa, Takuto Nakata, Yoshimichi Mitamura
  • Patent number: 9111967
    Abstract: Disclosed is a liquid processing method capable of rapidly penetrating a liquid chemical into a concave portion formed on the surface of a substrate with the chemical liquid. The liquid processing method includes wetting the inside of the concave portion by supplying an organic solvent having surface tension smaller than the chemical liquid to the substrate, and cleaning the inside of the concave portion with the chemical liquid by supplying a cleaning liquid including the chemical liquid to the substrate and substituting the liquid inside the concave portion with the chemical liquid.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: August 18, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Sekiguchi, Yasushi Fujii, Tetsuya Sakazaki
  • Patent number: 9102901
    Abstract: The invention provides a process for removing a film from a substrate, said process comprising applying a composition to the film, and wherein the composition comprises at least the following: a) water; and b) at least one compound selected from the following compounds (i-v): i) NR4HF2 (Formula 1), wherein R?H, alkyl, substituted alkyl, ii) NR4F (Formula 2), wherein R?H, alkyl, substituted alkyl, iii) HF (hydrofluoric acid), iv) H2SiF6 (hexafluorosilicic acid), or v) combinations thereof. The invention also provides a composition comprising at least the following: a) water; and b) at least one compound selected from the following compounds (i-v): i) NR4HF2 (Formula 1), wherein R?H, alkyl, substituted alkyl, ii) NR4F (Formula 2), wherein R?H, alkyl, substituted alkyl, iii) HF (hydrofluoric acid), iv) H2SiF6 (hexafluorosilicic acid), or v) combinations thereof.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: August 11, 2015
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Deyan Wang, Martin W. Bayes, Peter Trefonas, Kathleen M. O'connell
  • Patent number: 9076920
    Abstract: An aqueous alkaline etching and cleaning composition for treating the surface of silicon substrates, the said composition comprising: (A) a quaternary ammonium hydroxide; and (B) a component selected from the group consisting of water-soluble acids and their water-soluble salts of the general formulas (I) to (V): (R1—S03-)nXn+ (I), R—P032?(Xn+)3-n (II); (RO—S03-)nXn+ (III), RO—P032?(Xn+)3-n, (IV), and [(RO)2P02?]nXn+ (V); wherein the n=1 or 2; X is hydrogen or alkaline or alkaline-earth metal; the variable R1 is an olefinically unsaturated aliphatic or cycloaliphatic moiety and R is R1 or an alkylaryl moiety; the use of the composition for treating silicon substrates, a method for treating the surface of silicon substrates, and methods for manufacturing devices generating electricity upon the exposure to electromagnetic radiation.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 7, 2015
    Assignee: BASF SE
    Inventors: Berthold Ferstl, Simon Braun, Achim Fessenbecker
  • Patent number: 9040424
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 9029268
    Abstract: Processes are described to etch metals. In an embodiment, a process may include contacting a substrate with a stripping solution to remove photoresist from the substrate to produce a stripped substrate. The stripped substrate may include a plurality of solder pillars and a plurality of metal-containing field regions disposed around the plurality of solder pillars. In an illustrative embodiment, the plurality field regions may include copper. Additionally, the process may include rinsing the stripped substrate to produce a rinsed substrate. The rinsed substrate may be substantially free of a Sn layer or a Sn oxide layer. Further, the process may include contacting the rinsed substrate with an etch solution that is capable of removing an amount of one or more metals from the plurality of field regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Dynaloy, LLC
    Inventors: Richard Dalton Peters, Travis Acra, Spencer Erich Hochstetler, Kimberly Dona Pollard
  • Patent number: 9023735
    Abstract: An etchant composition includes ammonium persulfate (((NH4)2)S2O8), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bong-Kyun Kim, Hong Sick Park, Wang Woo Lee, Young Min Moon, Seung Ho Yoon, Young Joo Choi, Sang-Woo Kim, Ki-Beom Lee, Dae-Woo Lee, Sam-Young Cho
  • Patent number: 9023228
    Abstract: A pickling solution for the surface pre-treatment of plastic surfaces in preparation for metallization, the solution comprising a source of Mn(VII) ions; and an inorganic acid; wherein the pickling solution is substantially free of chromium (VI) ions, alkali ions, and alkaline-earth ions.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: May 5, 2015
    Assignee: Enthone Inc.
    Inventors: Mark Peter Schildmann, Ulrich Prinz, Christoph Werner
  • Patent number: 9011707
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Patent number: 9012322
    Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Errol Todd Ryan