Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) generating plasma in the following conditions: (a1) an RF bias voltage has a frequency equal to or greater than 1 MHz, (a2) an RF source voltage has a frequency equal to or greater than 1 MHz, (a3) the RF source voltage is modulated by pulses in a cycle equal to or greater than 100 &mgr;sec, and (a4) pulse-on time is equal to or greater than 50 &mgr;sec, and (b) patterning multi-layered metal wirings by etching through the plasma The method makes it possible to reduce charging damage to a gate insulating film, even if wirings are further spaced away from adjacent ones and/or an antenna ratio of multi-layered metal wirings is further increased.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: A spinner apparatus for manufacturing a photomask, performing a developing process for forming a resist pattern on a specific substrate, and performing an etching process in which a resist pattern is used as an etching mask are provided. A plurality of supply nozzles for supplying a developing solution or an etching solution are provided above the substrate on which processes will be performed and processing conditions such as the temperature and flux of the chemicals supplied from each supply nozzle are independently controlled. Accordingly, it is possible to control the deviation of the critical dimensions of the device.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: A ruthenium containing metal 6′ adhering to a periphery of a device forming area, an end face and a rear face in a silicon substrate 10 is removed using a first remover containing (a) at least one compound selected from the group consisting of salts containing chlorate, perchlorate, iodate, periodate, salts containing bromine oxide ion, salts containing manganese oxide ion and salts containing tetravalent cerium ion and (b) at least one acid selected from the group consisting of nitric acid, acetic acid, iodic acid and chloric acid. After the removing treatment, the substrate is washed with hydrofluoric acid to remove the residual remover.

Abstract: A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H2O2 is used to remove residues without etching or damaging the OSG film in the ILD (108) or IMD (110).

Abstract: There is provided a grating fabrication device and method to form gratings on a semiconductor substrate. The substrate is loaded into a reactor filled with an etchant solution, and an array of parallel light of interference light with different periods is projected onto the substrate to etch the portion of the substrate that is exposed to the light via an oxidation-reduction reaction. At the same time, the inclination angle of the substrate is selectively varied to obtain the different grating periods.

Abstract: Provided is a method for producing regularly ordered narrow pores excellent in linearity, and a structure with such narrow pores. A method for producing a narrow pore comprises a step of radiating a particle beam onto a workpiece, and a step of carrying out anodic oxidation of the workpiece having been irradiated with the particle beam, to form a narrow pore in the workpiece.

Abstract: A cleaning method for semiconductor manufacturing process. A to-be-cleaned wafer having a metal layer thereon is provided. The wafer is placed into a chemical cleaning equipment unit to clean the wafer surface with a chemical cleaning solution while protecting the metal layer by a cathodic protection method. Next, the chemical cleaning solution on the wafer surface is rinsed away and the wafer is then dried to complete the cleaning method.

Abstract: A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).

Abstract: As shown in FIG. 1A, a first resist film 2 comprising organic high molecules and a second resist film 3 comprising a photosensitive material are sequentially applied to a substrate 1 by the spin coat method or the spray method for forming a two-layer resist. Then, a mask 4 with which a metallic fine opening pattern 6 is formed on a mask substrate 5 comprising a dielectric, such as glass, is tightly contacted with the two-layer resist. Then, light is projected onto the back of the mask substrate to carry out exposure with near field light 7 which is effused from the opening portions of the mask 4 where no metal is formed. Then, a pattern is formed by processing the second resist layer 3 for development with a developing solution.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A cleaning method for semiconductor manufacturing process. A to-be-cleaned wafer having a metal layer thereon is provided. The wafer is placed into a chemical cleaning equipment unit to clean the wafer surface with a chemical cleaning solution while protecting the metal layer by a cathodic protection method. Next, the chemical cleaning solution on the wafer surface is rinsed away and the wafer is then dried to complete the cleaning method.

Abstract: A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.

Abstract: A method of forming integrated circuitry includes forming a silicon nitride comprising layer over a semiconductor substrate. At least a portion of the silicon nitride comprising layer is etched using an etching chemistry comprising ammonia and at least one fluorocarbon. A method of forming shallow trench isolation in a semiconductor substrate includes depositing a silicon nitride comprising layer over a bulk semiconductor substrate. A photoresist comprising masking layer is formed over the silicon nitride comprising layer. The photoresist comprising masking layer is patterned effective to form a plurality of shallow trench mask openings therethrough. The silicon nitride comprising layer is etched through the mask openings substantially selectively relative to the photoresist using an etching chemistry comprising ammonia and at least one fluorocarbon.

Abstract: Conventional methods of forming a (111)-plane into a 45-degree-surface have employed a silicon wafer which requires a high processing cost, and methods utilizing an inexpensive (100) silicon wafer have not been successful in forming a 45-degree-surface having sufficient flatness. There is provided a method for manufacturing a semiconductor device preparing a substrate made of the (100) silicon wafer including steps of preparing a substrate made of the (100) silicon wafer, forming a pattern along a <100> direction of the (100) silicon, and etching with an anisotropic etchant using the pattern while applying an ultrasonic wave.

Abstract: A method of manufacturing a silicon device with a single crystal structure, including forming etching start patterns on a surface of a silicon substrate; etching the silicon substrate by applying a voltage to the silicon substrate while the silicon substrate is immersed in a solution containing fluorine ions, with the silicon substrate used a positive electrode, to form narrow etched portions that extend into the substrate from the etching start patterns; and accelerating etching of the silicon substrate by increasing current flowing through the silicon substrate after the narrow etched portions have reached a predetermined depth, so that neighboring etched portions are in communication with each other below the narrow etched portions and a free standing structure including part of the silicon substrate is formed, and a hollow portion is formed below the free standing structure.

Abstract: There is provided a grating fabrication device and method to form gratings on a semiconductor substrate. The substrate is loaded into a reactor filled with an etchant solution, and an array of parallel light of interference light with different periods is projected onto the substrate to etch the portion of the substrate that is exposed to the light via an oxidation-reduction reaction. At the same time, the inclination angle of the substrate is selectively varied to obtain the different grating periods.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: Adherent matrix layers such as post-etch and other post-process residues are removed from a substrate by exposing them to a vapor phase solvent to allow penetration of the vapor phase solvent into the adherent matrix layers and condensing the vapor phase solvent into the adherent matrix layers and revaporized to promote fragmentation of the matrix and facilitate removal. Megasonic energy may be transmitted via a transmission member to the adherent matrix through the solvent condensed thereon to loosen fragments and particles. The substrate is typically rotated to improve contact between the megasonic energy transmission member and the condensed solvent and achieve more uniform cleaning. A co-solvent which is soluble in the vapor phase solvent may be added to enhance removal of specific adherent matrix materials.

Abstract: An entire surface of a semiconductor substrate is coated with photoresist and baked. A circuit pattern area in the region excluding a peripheral region of the semiconductor substrate is subjected to normal exposure while a non-circuit area (photoresist remaining area) in the peripheral region of the semiconductor substrate is subjected to a weak light so that the photoresist will not be removed completely during a development step and the remaining photoresist will have a hydrophilic surface. This improves wettability for a developing solution, enabling to apply the developing solution uniformly over the semiconductor substrate surface. This in turn reduces irregularities of circuit pattern dimensions due to uneven development.

Abstract: A method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor wafer is disclosed. In the method, a semiconductor wafer that has on a top surface a multiplicity of solder bodies electrically connected to a multiplicity of bond pads through a multiplicity of copper wetting layers is first provided. When the multiplicity of solder bodies is found out of specification or must be removed for any other quality reasons, the semiconductor wafer is exposed to an etchant that has an etch rate toward the copper wetting layer at least 5 times the etch rate toward a metal that forms the multiplicity of bond pads. The semiconductor wafer may be removed from the etchant when the multiplicity of copper wetting layers is substantially dissolved such that the multiplicity of solder bodies is separated from the multiplicity of bond pads. The multiplicity of solder bodies may be either solder bumps or solder balls.

Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.

Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.

Abstract: Provided is a method for producing regularly ordered narrow pores excellent in linearity, and a structure with such narrow pores. A method for producing a narrow pore comprises a step of radiating a particle beam onto a workpiece, and a step of carrying out anodic oxidation of the workpiece having been irradiated with the particle beam, to form a narrow pore in the workpiece.

Abstract: Disclosed herein is a method for processing a substrate. The method includes supplying a liquid agent such as a developer onto the surface of a substrate, bringing an upper surface of a film formed of the liquid agent into contact with a liquid agent holding member arranged so as to face the substrate, holding the liquid agent between the substrate and the liquid agent holding member, moving the substrate or the liquid agent holding member, or both, in parallel to the main surface of the substrate, while the main surface of the substrate is being treated with the liquid agent. Since the concentrations of reaction products and starting reaction materials become uniform in the liquid agent which contacts the substrate, the entire substrate can be processed uniformly.

Abstract: A method for etching GaN material comprising configuring the GaN material as an anode in an electrochemical cell where the electrochemical cell is comprised of an anode, a cathode and an electrolyte, and applying a bias across the anode and the cathode to a level which is sufficient to induce etching of the material. The etch rate of the material is controllable by varying the bias level. The cell is additionally illuminated with a preselected level of UV light which provides for uniformity of the etching process. The present method is particularly useful for etching a GaN HBT from n-p-n GaN material.

Abstract: Generally, and in one form of the invention, a method is presented for the photo-stimulated etching of a CaF2 surface 12, comprising the steps of exposing the CaF2 surface 12 to an ambient species 16, exciting the CaF2 surface 12 and/or the ambient species 16 by photo-stimulation sufficiently to allow reaction of the CaF2 surface 12 with the ambient species 16 to form CaF2 ambient species products, and removing the ambient species 16 and the CaF2 ambient species products from the CaF2 surface 12. Other devices, systems and methods are also disclosed.

Abstract: A defective photoresist mask is removed from a metal layer prior to etching by low-temperature processing to minimize or substantially eliminate any resulting residue on the metal layer, thereby enabling the formation of an interconnection pattern with minimal defects. Embodiments include removing the defective mask by applying a solvent at a temperature of about 80° C. or less, forming a new photoresist mask, and etching the underlying metal layer. The substantial elimination of residue on the metal layer prior to etching avoids bridging between resulting interconnection lines and, hence, short circuiting and device failure.

Abstract: A method of determining the carrier concentration depth profile in n-type wide bandgap semiconductor wafers is disclosed. The method includes placing a semiconductor wafer within a photoelectrochemical capacitance-voltage measurement system, in contact with a Schottky electrolyte solution. A high energy ultraviolet light is directed through the electrolyte solution to impinge upon the surface of the semiconductor wafer. The ultraviolet light has an energy greater than the energy bandgap of the semiconductor material and thus facilitates reliable etching thereof. The etch is allowed to continue until a desired depth in the sample is obtained. Upon cessation of the etch, the carrier concentration is determined. The steps of determining the carrier concentration and etching are repeated until the desired carrier concentration depth profile has been obtained.

Abstract: Methods of forming substantially defect-free silicon structures at the submicron level by enhancing microscopic etchant concentration uniformity and reducing hydrogen bubble adhesion. Etchant mixtures are subjected to the application of ultrasonic waves. The ultrasonic waves promote cavitation that mixes the etchant mixture on a microscopic level, and also assists in promoting bubble detachment. Wetting agents are added to the etchant mixture to enhance the hydrophilicity of the silicon surfaces and thereby reduce bubble adhesion. Apparatus to carry out the method of forming silicon structures are also disclosed.

Abstract: Slurries used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such slurries. In one aspect of the invention, a planarizing slurry for planarizing a microelectronic-device substrate assembly is made by fracturing agglomerations of abrasive particles in a first slurry component into smaller agglomerations of abrasive particles or individual abrasive particles. The first slurry component can include water and the abrasive particles. The agglomerations of abrasive particles can be fractured into smaller units by imparting energy to the first slurry component before the first slurry component is mixed with a second slurry component. The agglomerations of abrasive particles are preferably fractured by imparting sonic energy to the first slurry component before it is mixed with the second slurry component. The agglomerations of abrasive particles in the first slurry component may also be fractured by ball milling or highly turbulent pumping.

Abstract: A method of fabricating a semiconductor component, the method including at least one step of etching an upper layer formed on a substrate. In the method, prior to forming the upper layer, at least one set made up of marker layers separated by intermediate layers of predetermined thicknesses is caused to be grown, where the marker layers and adjacent intermediate layers have different refractive indices, and then during etching of the upper layer refractive index discontinuities are detected optically and etching is stopped when the sequence of the optically detected discontinuities corresponds to a reference sequence representative of the thicknesses of the intermediate layers.

Abstract: The gate oxide film is prevented from being thinned partially. The semiconductor substrate (wafer) can be etched (processed) under excellent conditions. The impurities on the wafer surface can be analyzed and further reduced. In the first aspect, the substrate is irradiated with ultraviolet rays in contact with an F-containing aqueous solution, so that the oxide film and the substrate can be etched at roughly the same etching speed under excellent controllability without deteriorating the planarization of the substrate. In the second aspect, the substrate is etched by irradiating ultraviolet rays during exposure to an acid aqueous solution, so that surface metallic contamination and particles can be removed without deteriorating the wafer surface roughness. Further, the impurity elements in the outermost surface layer of the wafer can be analyzed at high precision by analyzing elements contained in the acid aqueous solution used for the etching.

Abstract: An improved method of deprocessing semiconductor chips provides faster, more accurate and more complete deprocessing. The chip to be deprocessed is placed in a chemical agent to loosen or undercut layers of material to be removed. A physical impact or series of impacts is then delivered to the chip, for example, by a compression wave transmitted through a fluid medium. The impact will cause chemically loosened or undercut material to break loose from the chip. The amount of time between when the chip is placed in the chemical agent and when the impact occurs, and the power and duration of the impact can be controlled to determine what layer of the chip structure will be exposed by the deprocessing.

Abstract: Material of a given chemical type is selectively electrochemically removed from a structure by subjecting portions of the structure to an electrolytic bath. The characteristics of certain parts of the structure are chosen to have electrochemical reduction half-cell potentials that enable removal of the undesired material to be achieved in the bath without applying external potential to any part of the structure. The electrolytic bath can be implemented with liquid that is inherently corrosive to, or inherently benign to, material of the chemical type being selectively removed.

Abstract: A method for etching nitride is provided, by which the etching rate and the roughness of the etching surface can be powerfully controlled, and by which the etching depth can be in-situ monitored. The etching method comprises the steps of: (i) coating a first electrode on a nitride chip; (ii) mounting the nitride chip on a holding device; (iii)dipping the holding device, the nitride chip and the first electrode in electrolysis liquid; (iv) irradiating the nitride chip with a UV light having a wavelength shorter than 254 nm; and (v) connecting the first electrode to a second electrode dipped in the electrolysis liquid by a galvanometer to in-situ monitor the etching current, so as to in-situ control the etching depth.

Abstract: Disclosed is a method for selectively etching an opening in order to reduce cusping on and thereby widen the opening. The opening in one embodiment comprises a contact opening with a diffusion barrier liner layer deposited thereover that has formed cusps at the mouth of the contact opening. The contact opening is exposed to an etching agent at a low temperature and pressure such that the etching agent adheres to the contact opening. Photons are then directed towards the contact opening at an acute angle to the surface of the contact opening. The acute angle causes the surface of the contact opening to block the photons from contacting the bottom of the contact opening with a high flux density. The photons impart an energy to activate the etching agent, causing substantial etching of an upper portion of the contact opening, while a lower portion does not receive a significant flux density and is not substantially etched.

Abstract: A method of processing semiconductor films and layers, especially Group III Nitride films, has been achieved, using laser-enhanced, room-temperature wet etching with dilute etchants. Etch rates of a few hundred .ANG./min up to a few thousand .ANG./min have been achieved for unintentionally doped n-type Group III Nitride films grown by MOCVD on a sapphire substrate. The etching is thought to take place photoelectrochemically with holes and electrons generated by incident illumination from 4.5 mW of HeCd laser power enhancing the oxidation and reduction reactions in an electrochemical cell.

Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).