With Relative Movement Between Substrate And Confined Pool Of Etchant Patents (Class 438/747)
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Patent number: 7743783Abstract: A method and apparatus for recycling a process fluid from a drain of a semiconductor process tool. The process fluid may be an acidic cobalt solution or an electroless cobalt solution used in a semiconductor process step to prevent electromigration in copper interconnects. The used process fluid is collected from the tool drain and recycled back to the tool inlet if a condition of the fluid is within a predetermined range. Otherwise, the used process fluid is drained from the system. The system may also operate in a bleed and feed mode where a portion of the used process fluid is periodically drained from the system.Type: GrantFiled: April 2, 2007Date of Patent: June 29, 2010Assignee: Air Liquide Electronics U.S. LPInventor: David Paul Edwards
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Patent number: 7709341Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.Type: GrantFiled: June 2, 2006Date of Patent: May 4, 2010Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
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Patent number: 7691207Abstract: A method for cleaning a disk-shape glass substrate, which comprises rotating the disk-shape glass substrate on its center with its main surface vertical, and making a cleaning fluid irradiated with ultrasonic waves run down on the outer peripheral edge surface of the rotating glass substrate.Type: GrantFiled: July 14, 2006Date of Patent: April 6, 2010Assignee: Asahi Glass Company, LimitedInventors: Osamu Miyahara, Kazuo Mannami, Kuniyuki Someya, Tsutomu Maruyama
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Publication number: 20100062611Abstract: Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.Type: ApplicationFiled: September 5, 2008Publication date: March 11, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Chyi Liu, Yao Fei Chuang, Martin Liu, Gwo-Yuh Shiau, Chia-Shiung Tsai
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Patent number: 7601642Abstract: The inventive method for processing a silicon wafer is a method comprising step 11 in which a single crystal ingot is sliced into thin disc-like wafers; step 13 in which the surface of each wafer is lapped to be planar; step 14 in which the wafer is subjected to alkaline cleaning to be removed of contaminants resulting from preceding machining; and step 16 in which the wafer is alternately transferred between two groups of etching tanks one of which contain acidic etching solutions and the other alkaline etching solutions, wherein an additional step 12 is introduced between step 11 and step 13 in which a wafer is immersed in an acidic solution containing hydrofluoric acid (HF) and nitric acid (HNO3) at a volume ratio of ? to ½ (HF/HNO3) so that degraded superficial layers occurring on the front and rear surfaces of the wafer as a result of machining can be removed and the edge surface of the wafer can be beveled.Type: GrantFiled: May 27, 2004Date of Patent: October 13, 2009Assignee: Sumco CorporationInventors: Sakae Koyata, Kazushige Takaishi
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Patent number: 7592201Abstract: As a step in performing a process on a structure, a hole pattern is provided in a thin layer of organic resin masking material formed over the structure to provide a process mask. A processing step is then performed through the openings in the mask, and after a processing step is completed the mask is adjusted by a re-flow process in which the structure is placed into an atmosphere of solvent vapor of a solvent of the mask material. By way of the reflow process, the mask material softens and re-flows to reduce the size of the openings in the mask causing edges of the surface areas on which the processing step was performed to be covered by the mask for subsequent processing steps.Type: GrantFiled: September 9, 2004Date of Patent: September 22, 2009Assignee: CSG Solar AGInventors: Trevor Lindsay Young, Rhett Evans
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Patent number: 7566644Abstract: A method for forming a gate electrode of a semiconductor device is provided wherein a hard mask layer which is a nitride film is deposited and subjected to an additional surface deposition process so that a matrix structure of a nitride film surface becomes more compact to reduce an etching ratio of the hard mask layer thereby increasing a thickness of the residual hard mask layer.Type: GrantFiled: June 2, 2005Date of Patent: July 28, 2009Assignee: Hynix Semiconductor Inc.Inventor: Ki Won Nam
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Patent number: 7563717Abstract: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper side of the insulating layer. The second polishing step is performed, after completing the first polishing step, for planarizing the insulating interlayer.Type: GrantFiled: December 28, 2005Date of Patent: July 21, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Ji Hyung Yune
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Patent number: 7521373Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.Type: GrantFiled: July 12, 2004Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventor: Donald L Yates
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Patent number: 7521374Abstract: According to one aspect of the present invention, a method and apparatus for cleaning a semiconductor substrate is provided. The method may include supporting a semiconductor substrate, the semiconductor substrate having a surface, and dispensing an amount of semiconductor substrate processing liquid onto the surface of the semiconductor substrate, the amount of semiconductor substrate processing liquid being such that substantially none of the semiconductor substrate processing liquid flows off the surface of the semiconductor substrate. The semiconductor substrate processing fluid may form a standing puddle on the surface of the semiconductor substrate. The semiconductor substrate may be rotated while the semiconductor substrate processing liquid is on the surface of the semiconductor substrate such that substantially all of the amount of semiconductor substrate processing liquid remains on the surface of the semiconductor substrate during said rotation.Type: GrantFiled: November 23, 2004Date of Patent: April 21, 2009Assignee: Applied Materials, Inc.Inventors: Steven Verhaverbeke, Dennis Yost, Roman Gouk
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Patent number: 7476554Abstract: A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit of the number or density of defects produced at the substrate due to the particles in the process for the substrate is determined, and the predetermined relative velocity is set at a value equal to or smaller than the relative velocity obtained when the number or density of defects reaches the upper limit.Type: GrantFiled: March 27, 2006Date of Patent: January 13, 2009Assignee: Panasonic CorporationInventors: Toshio Kaneko, Toru Nishiwaki
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Patent number: 7470622Abstract: A method of fabricating silicon micro-mirrors includes etching from opposite sides of a silicon wafer with a polished surface on at least one of the opposite sides, to form silicon bars each having a parallelogram-shaped cross-section and including a portion of the polished surface. At least one of the silicon bars is mounted on a mounting surface. The polished surface of the silicon bar may be used to reflect optical signals.Type: GrantFiled: June 17, 2005Date of Patent: December 30, 2008Assignee: Hymite A/SInventor: Lior Shiv
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Patent number: 7468325Abstract: A method of cleaning a silicon nitride layer on a substrate is provided to effectively remove negative-charged impurities such as polymer and particle from the silicon nitride layer. In the method, the zeta potential of the silicon nitride layer is changed from positive to negative, and then the silicon nitride layer is cleaned with a first solution selected from an alkali solution and an NC-2 solution. So the negatively-charged impurities can be easily removed due to a repulsion force. The substrate can be treated with spin scrubber or quick dump rinse before and/or after the changing of the zeta potential. To change the zeta potential, the substrate can be dipped into a second solution such as an SC-1 solution, an NC-2 solution, and an alkali solution.Type: GrantFiled: December 29, 2005Date of Patent: December 23, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Dae Heok Kwon
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Patent number: 7456113Abstract: The present invention is a method of use of a novel cleaning solution in a single wafer cleaning process. According to the present invention the method involves using a cleaning solution in a single wafer mode and the cleaning solution comprises at least ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), water (H2O) and a chelating agent. In an embodiment of the present invention the cleaning solution also contains a surfactant. Moreover, the present invention also teaches a method of combining an ammonia hydroxide, hydrogen peroxide, and chelating agent step with a short HF step in a fashion that minimizes process time in a way that the entire method removes aluminum and iron contamination efficiently without etching too much oxide. The single wafer cleaning processes may also be used to increase the yield of high-grade reclaimed wafers.Type: GrantFiled: June 6, 2005Date of Patent: November 25, 2008Assignee: Applied Materials, Inc.Inventors: Ronald Rayandayan, Steven Verhaverbeke, Hong Wang
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Patent number: 7432214Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.Type: GrantFiled: July 12, 2004Date of Patent: October 7, 2008Assignee: Micron Technology, Inc.Inventor: Donald L Yates
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Patent number: 7396773Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.Type: GrantFiled: December 6, 2002Date of Patent: July 8, 2008Assignee: Cypress Semiconductor CompanyInventors: Alain Blosse, Krishnaswamy Ramkumar
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Patent number: 7371694Abstract: The flatness of the surface of a Si substrate is requested as the present gate length is miniaturized. The present invention is a semiconductor device fabrication method for flattening a silicon surface by continuously supplying a high-temperature fluoride ammonium solution to the surface a silicon substrate in which at least the silicon surface is locally exposed.Type: GrantFiled: February 14, 2005Date of Patent: May 13, 2008Assignee: Elpida Memory Inc.Inventors: Ken Sasaki, Hiroyuki Sakaue, Takayuki Takahagi
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Patent number: 7371693Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.Type: GrantFiled: February 24, 2004Date of Patent: May 13, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
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Patent number: 7354869Abstract: A method for a substrate processing apparatus having a substrate holding mechanism and a chemical solution dispensing/sucking mechanism including a chemical solution dispensing port for supplying a first chemical solution and a chemical solution suction port, includes placing the target substrate on the substrate holding mechanism, laying out an auxiliary plate at a periphery of the substrate such that the two main faces are substantially flush with each other, supplying a second chemical solution onto the main faces, dispensing the first solution from the dispensing port and sucking the first and second solutions through the suction port, with the dispensing and suction ports brought into contact with the second solution, and while dispensing the first solution from the dispensing port and sucking the first solution through the suction port, scanning the dispensing/sucking mechanism such that the dispensing and suction ports are opposed to the main face of the substrate.Type: GrantFiled: April 12, 2005Date of Patent: April 8, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Sakurai, Masamitsu Itoh
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Patent number: 7354530Abstract: Alpha-amino acid containing chemical mechanical polishing compositions and slurries that are useful for polishing substrates including multiple layers of metals, or metals and dielectrics.Type: GrantFiled: January 10, 2005Date of Patent: April 8, 2008Inventors: Shumin Wang, Vlasta Brusic Kaufman
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Patent number: 7341065Abstract: Methods of preventing air-liquid interfaces on the surface of a wafer in order to prevent the formation of particle defects on a wafer are presented. The air-liquid interfaces may be prevented by covering the entire surface of the wafer with liquid at all times during a cleaning process while the surface of the wafer is hydrophobic. Methods of preventing the formation of silica agglomerates in a liquid during a pH transition from an alkaline pH to a neutral pH are also presented, including minimizing the turbulence in the liquid solution and reducing the temperature of the liquid solution during the transition.Type: GrantFiled: July 31, 2006Date of Patent: March 11, 2008Assignee: Applied Materials, Inc.Inventors: Steven Verhaverbeke, Christopher Laurent Beaudry
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Publication number: 20080057730Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: Texas Instruments IncorporatedInventors: Phillip Daniel Matz, Trace Hurd
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Patent number: 7332437Abstract: There is provided a method for processing a semiconductor wafer subjected to a chamfering process, a lapping process, an etching process, and a mirror-polishing process, wherein acid etching is performed after alkaline etching as the etching process, and the acid etching is performed with an acid etchant composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, a method for processing a semiconductor wafer subjected to a chamfering process, a surface grinding process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, and a method for processing a semiconductor wafer subjected to a flattening process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, a back surface polishing process is performed after the acid etching as the mirror-polishing process, and then a front surface polishing process is performed.Type: GrantFiled: June 25, 2001Date of Patent: February 19, 2008Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Takashi Nihonmatsu, Masahiko Yoshida, Yoshinori Sasaki, Masahito Saitoh, Toshiaki Takaku, Tadahiro Kato
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Patent number: 7312159Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.Type: GrantFiled: July 12, 2004Date of Patent: December 25, 2007Assignee: Micron Technology, Inc.Inventor: Donald L Yates
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Patent number: 7307026Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.Type: GrantFiled: February 25, 2004Date of Patent: December 11, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Christof Streck, Guido Koerner, Thorsten Kammler
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Publication number: 20070269990Abstract: A method of removing an ion implanted photoresist comprises performing first cleaning a semiconductor substrate having the ion implanted photoresist using hot deionized water to which a megasonic process is applied, first rinsing the semiconductor substrate using cold deionized water, drying the semiconductor substrate, removing the ion implanted photoresist, and second cleaning the semiconductor wafer using an SPM solution.Type: ApplicationFiled: December 28, 2006Publication date: November 22, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Ji Hye Han
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Patent number: 7291283Abstract: A combined wet etching method for stacked films which is capable of performing etching processes in a collective manner while controlling an amount of side-etching on each of stacked films and of making uniform side edges. In the wet etching method, two or more types of etching methods are performed in combination, on stacked films containing first and second films being deposited sequentially on a substrate and each having a different film property. The two or more types of wet etching methods include, at least, a first wet etching method in which side-etching on the first film is facilitated more than side-etching on the second film and a second wet etching method in which side-etching on the second film is facilitated more than side-etching on the first film.Type: GrantFiled: November 12, 2003Date of Patent: November 6, 2007Assignee: NEC LCD Technologies, Ltd.Inventors: Tadanori Uesugi, Shigeru Kimura
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Patent number: 7288207Abstract: A method for manufacturing a silicon wafer includes a planarizing process 13 for polishing or lapping the upperside and lowerside surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot, an etching process for dipping the silicon wafer into the etching liquid wherein silica powder is dispersed uniformly in an alkali aqueous solution, thereby etching the upperside and lowerside surfaces of the silicon wafer, and a both-side simultaneous polishing process 16 for polishing the upperside and lowerside surfaces of the etched silicon wafer simultaneously or a one-side polishing process for polishing the upperside and lowerside surfaces of the etched silicon wafer one after another, in this order.Type: GrantFiled: January 31, 2006Date of Patent: October 30, 2007Assignee: Sumco CorporationInventors: Sakae Koyata, Yuichi Kakizono, Tomohiro Hashii, Katsuhiko Murayama
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Publication number: 20070197036Abstract: A method for manufacturing an electro-optic device includes an electroconductive film forming step that forms an electroconductive film over surfaces of a substrate. A front electroconductive film removing step is also performed which removes the electroconductive film from the front surface of the substrate. A thin layer forming step is performed to form thin layers on the front surface of the substrate. Then, a rear electroconductive film removing step is performed which removes the electroconductive film from the rear surface of the substrate. At least one of the front electroconductive film removing step and the rear electroconductive film removing step is performed by applying a chemical agent capable of etching with the substrate rotated, to the rotation center of the surface of the substrate that is to be subjected to the removal of the electroconductive film, while a dry gas is jetted to the rotation center of the other surface that is not subjected to the removal of the electroconductive film.Type: ApplicationFiled: February 20, 2007Publication date: August 23, 2007Applicant: Seiko Epson CorporationInventors: Eiichi Miura, Atsuhito Matsuo
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Patent number: 7235141Abstract: A lift-off procedure is provided which enables prevention of damage to a wiring pattern caused by contact of a metal being peeled off from a wafer with a wiring pattern at a time of lift-off procedure. A wafer having a surface on which a pattern is formed which contains a pattern portion to be removed is soaked into a chemical liquid at an angle at which the surface faces downward.Type: GrantFiled: April 22, 2005Date of Patent: June 26, 2007Assignee: Oki Electric Industry Co., Ltd.Inventors: Masaru Suzuki, Yoshiki Nitta, Kazuhiko Ohmuro
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Patent number: 7205245Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.Type: GrantFiled: August 10, 2005Date of Patent: April 17, 2007Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Grady S. Waldo, Kevin J. Torek, Li Li
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Patent number: 7179693Abstract: The present invention relates to a method for manufacturing a thin film device. The thin film device is manufactured by bonding a second substrate (106) to a thin film device layer (103) provided on a protective layer (102) formed on a first substrate (101) through a first adhesive layer (105), then, completely or partly removing the first substrate (101) in accordance with a process including at least one process of a chemical process and a mechanical polishing process, bonding a third substrate (109) to the exposed protective layer (102) or the protective layer (102) covered with the partly removed first substrate (101) through a second adhesive layer (108) and separating or removing the second substrate (106). Thus, the thin film device suitable for a light and thin display panel is manufactured without deteriorating a ruggedness.Type: GrantFiled: March 14, 2005Date of Patent: February 20, 2007Assignee: Sony CorporationInventors: Akihiko Asano, Tomoatsu Kinoshita
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Patent number: 7172708Abstract: A thin-film device is fabricated by forming a protective layer and a thin-film device layer one by one on a first substrate and bonding a second substrate on the thin-film device layer via a first adhesive layer or a coating layer and first adhesive layer, removing the first substrate at least in a part thereof by etching with a chemical solution, bonding the protective layer, which covers the thin-film device layer on a side of the first substrate, to a third substrate via a second adhesive layer, and removing the second substrate. The protective layer is formed of at least two layers having resistance to the chemical solution used upon removal of the first substrate.Type: GrantFiled: February 19, 2004Date of Patent: February 6, 2007Assignee: Sony CorporationInventors: Tomoatsu Kinoshita, Akihiko Asano
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Patent number: 7104267Abstract: A process for treating a copper or copper alloy substrate surface with a composition and corrosion inhibitor solution to minimize defect formation and surface corrosion, the method including applying a composition including one or more chelating agents, a pH adjusting agent to produce a pH between about 3 and about 11, and deionized water, and then applying a corrosion inhibitor solution. The composition may further comprise a reducing agent and/or corrosion inhibitor. The method may further comprise applying the corrosion inhibitor solution prior to treating the substrate surface with the composition.Type: GrantFiled: November 29, 2000Date of Patent: September 12, 2006Assignee: Applied Materials Inc.Inventors: Ramin Emami, Shijian Li, Sen-Hou Ko, Fred C. Redeker, Madhavi Chandrachood
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Patent number: 7030034Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.Type: GrantFiled: September 18, 2003Date of Patent: April 18, 2006Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Grady S. Waldo, Kevin J. Torek, Li Li
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Patent number: 7026255Abstract: In a method for photo-electrochemical etching of a semiconductor sample, the semiconductor sample is brought in contact with an electrolyte liquid. The contact area formed thereby is illuminated through the electrolyte liquid with UV light. The photo-current created by UV light irradiation at the contact area is measured. To increase the etching quality, a jet of fresh electrolyte liquid is repeatedly applied to the contact area. A device for carrying out the method includes a container to be filled with an electrolyte liquid, a UV source for illuminating the semiconductor sample with UV light through the electrolyte liquid, and a measuring instrument for measuring the photo-current created during UV light irradiation of the contact area. Further provided are an inlet for supplying fresh electrolyte liquid, directed towards the semiconductor sample, and a device attached to the inlet for repeated production of electrolyte fluid jets, directed towards the semiconductor sample.Type: GrantFiled: October 24, 2003Date of Patent: April 11, 2006Inventor: Thomas Wolff
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Patent number: 7018939Abstract: A method is provided herein for cleaning a semiconductor device. In accordance with the method, a semiconductor device is provided (11), and a micellar solution is applied (13) to the semiconductor device. The method is particularly useful for cleaning copper and silicon surfaces and removing processing residues from the surfaces of vias or trenches.Type: GrantFiled: July 11, 2003Date of Patent: March 28, 2006Assignee: Motorola, Inc.Inventor: Balgovind K. Sharma
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Patent number: 7001086Abstract: A developing method comprises determining in advance the relation of resist dissolution concentration in a developing solution and resist dissolution speed by the developing solution, estimating in advance the resist dissolution concentration where the resist dissolution speed is a desired speed or more from the relation, and developing in a state in which the resist dissolution concentration in the developing solution is the estimated dissolution concentration or less.Type: GrantFiled: October 21, 2004Date of Patent: February 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masamitsu Itoh, Ikuo Yoneda, Hideaki Sakurai
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Patent number: 6992014Abstract: A method for controlling a process on a substrate. The method comprising: providing the substrate, the substrate having an upper surface, an opposite lower surface and an edge between the upper and lower surfaces; processing the upper surface of the substrate with a first fluid; directing a second fluid against a portion of the lower surface proximate to the edge of the substrate, wherein the second fluid flows adjacent to the edge of the substrate; and controlling the temperature of the second fluid in order to affect a processing of an edge region of the upper side of the substrate.Type: GrantFiled: November 13, 2002Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Casey J. Grant, Joel M. Sharrow, John J. Snyder
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Patent number: 6969688Abstract: A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.Type: GrantFiled: October 8, 2002Date of Patent: November 29, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Baw-Ching Perng, Fang-Cheng Chen, Hun-Jan Tao, Peng-Fu Hsu, Yue-Ho Hsieh, Chih-Cheng Wang, Shih-Yi Hsiao
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Patent number: 6955994Abstract: A method of manufacturing a semiconductor device, including the steps of (a) rowing an InP layer on a surface of starting growth, resulting in the InP layer having a convex structure, and (b) wet etching the InP layer by an enchant including hydrochloric acid and acetic acid, and thereby flattening a surface of the InP layer.Type: GrantFiled: December 21, 2001Date of Patent: October 18, 2005Assignee: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Hiroaki Ito, Takuya Fujii
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Patent number: 6900142Abstract: A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield.Type: GrantFiled: July 30, 2003Date of Patent: May 31, 2005Assignee: International Business Machines CorporationInventors: Emanual I. Cooper, John M. Cotte, Lisa A. Fanti, David E. Eichstadt, Stephen J. Kilpatrick, Henry A. Nye, III, Donna S. Zupanski-Nielsen
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Patent number: 6864186Abstract: A method and apparatus for reducing the contaminants in a wet etching bath by rapidly removing a substantial portion of the etching liquid from the bath such that the contaminants are removed from the air/liquid interface of the bath surface is described. By rapidly removing a substantial portion of the etching liquid from the bath, contaminants that are trapped by eddy currents and liquid/air surface tension forces are greatly reduced at the surface of the bath. The semiconductor wafers treated showed reduced levels of contamination.Type: GrantFiled: July 28, 1998Date of Patent: March 8, 2005Assignee: Micron Technology, Inc.Inventor: Donald L. Yates
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Patent number: 6863796Abstract: A method for cleaning an electrodeposition surface following an electroplating process including providing a process surface including electro-chemically deposited metal following an electrodeposition process; and, cleaning the process surface with a sulfuric acidic cleaning solution to remove electrodeposited metal particles according to at least one of an immersion and spraying process the spraying process including simultaneously rotating the process surface.Type: GrantFiled: July 2, 2002Date of Patent: March 8, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chia-Liang Chueh, Volume Chien, Shih-Ming Wang
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Patent number: 6861371Abstract: The present invention provides a substrate processing system and method which can prevent the filter from being stuffed with foreign objects and make the filter accordingly more durable. The substrate processing system 12 comprising a substrate processing unit 46 for processing substrates W with a processing liquid, and a processing liquid recovery passage 75 for passing the processing liquid discharged from the substrate processing unit 46, in which the processing liquid recovery passage 75 includes a filter 80 for removing foreign objects mixed in the processing liquid, a cleaning fluid supply passage 120 for feeding a cleaning fluid for cleaning the filter 80, and a discharge passage 115 for discharging the processing liquid and the cleaning fluid from the filter 80.Type: GrantFiled: November 1, 2002Date of Patent: March 1, 2005Assignee: Tokyo Electron LimitedInventors: Yuji Kamikawa, Eiichi Mukai
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Patent number: 6861005Abstract: Polysilicon formed over an underlying insulator may be highly selectively etched. Therefore, polysilicon may be selectively etched using tetraalkylammonium hydroxide or NH4OH to define a nitride waveguide. The resulting nitride waveguide may have smoother surfaces resulting in less loss of light intensity as light travels through the nitride waveguide.Type: GrantFiled: July 31, 2002Date of Patent: March 1, 2005Assignee: Intel CorporationInventor: Justin K. Brask
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Patent number: 6855640Abstract: When using hot alkaline etchants such as KOH, the wafer front side, where various devices and/or circuits are located, must be isolated from any contact with the etchant. This has been achieved by using two chambers that are separated from each other by the wafer that is to be etched. Etching solution in one chamber is in contact with the wafer's back surface while deionized water in the other chamber contacts the front surface. The relative liquid pressures in the chambers is arranged to be slightly higher in the chamber of the front surface so that leakage of etchant through a pin hole from back surface to front surface does not occur. As a further precaution, a monitor to detect the etchant is located in the DI water so that, if need be, etching can be terminated before irreparable damage is done.Type: GrantFiled: February 26, 2002Date of Patent: February 15, 2005Assignee: Institute of MicroelectronicsInventors: Zhe Wang, Qingxin Zhang, Pang Dow Foo, Hanhua Feng
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Patent number: 6852630Abstract: A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.Type: GrantFiled: April 23, 2001Date of Patent: February 8, 2005Assignee: ASM Nutool, Inc.Inventors: Bulent M. Basol, Cyprian Uzoh, Halit N. Yakupoglu, Homayoun Talieh
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Patent number: 6831307Abstract: An object of the present invention is to provide a novel semiconductor mounting system having a semiconductor mounting member, a metal member and a joining layer joining the mounting and metal members, to improve the flatness of a mounting surface and to control the temperature on the surface of a semiconductor. A semiconductor mounting system 12 has a semiconductor mounting member 1, a metal member 7 and a joining layer 27 joining the mounting member 1 and metal member 7. The metal member 1 has a surface mounting a semiconductor. The adhesive sheet 4 has a resin matrix 11 and a filler 10 dispersed in the resin matrix 11.Type: GrantFiled: February 25, 2003Date of Patent: December 14, 2004Assignee: NGK Insulators, Ltd.Inventor: Tomoyuki Fujii
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Patent number: 6806205Abstract: Disclosed is a a method of fabricating a MEMS device by means of surface micromachining without leaving any stiction or residues by etching silicon oxide of a sacrificial layer, which is an intermediate layer between a substrate and a microstructure, rather than by etching silicon oxide of a semiconductor device. The method according to the invention includes the steps of supplying alcohol vapor bubbled with anhydrous HF, maintaining a temperature of the supplying device and a moving path of the anhydrous HF and the alcohol to be higher than a boiling point of the alcohol, performing a vapor etching by controlling a temperature and a pressure to be within the vapor region of a phase equilibrium diagram of water, and removing silicon oxide of a sacrificial layer on a lower portion of the microstructure.Type: GrantFiled: December 29, 2000Date of Patent: October 19, 2004Assignee: Electronics and Telecommunications Research InstituteInventors: Won-Ick Jang, Chang-Auck Choi, Chi-Hoon Jun, Youn-Tae Kim, Myung-Lae Lee