With Relative Movement Between Substrate And Confined Pool Of Etchant Patents (Class 438/747)
  • Patent number: 6790683
    Abstract: The present invention is generally directed to various methods of controlling wet chemical processes in forming metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal while the wet chemical process is being performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: September 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Terri A. Couteau
  • Patent number: 6767840
    Abstract: An ultrasonic bath (30) is arranged below a wafer processing bath (10). Wafers (40) are processed while ultrasonic waves are transmitted from the ultrasonic bath (30) to the wafer processing bath (10). The wafers (40) are processed while being entirely dipped into the wafer processing bath (10) and rotated by wafer rotating rods (53).
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: July 27, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Fumio Uehara, Kiyofumi Sakaguchi, Kazutaka Yanagita, Masakazu Harada
  • Patent number: 6767841
    Abstract: A process for producing a semiconductor wafer is based upon etching the semiconductor wafer with an etching medium flowing in a laminar flow along a direction of flow toward an edge of the semiconductor wafer. There is a protective shield arranged in front of the edge of the semiconductor wafer, so that the etching medium flows onto the protective shield and not onto the edge of the semiconductor wafer. There is also a process that has the semiconductor wafer being inclined with respect to the direction of flow of the etching medium, so that there is an angle of less than 180° between the direction of flow of the etching medium and a first side of the semiconductor wafer. Also, there is an angle of greater than 180° between the direction of flow of the etching medium and a second side of the semiconductor wafer, and the second side of the semiconductor wafer is subsequently polished.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: July 27, 2004
    Assignee: Siltronic AG
    Inventors: Günter Schwab, Helmut Franke, Manfred Schöfberger
  • Patent number: 6762132
    Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 13, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Donald L. Yates
  • Patent number: 6750154
    Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: June 15, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Terry L. Gilton
  • Patent number: 6730605
    Abstract: A method to redistribute solid copper deposited by PVD on a wafer topography. The deposited copper is solubilized in a fluid for redistribution. The copper redistribution prevents inherent nonuniformity of the deposited copper film thickness by improving the uniformity of thickness of the copper film on the covered surfaces, such as vertical and bottom surfaces. The method provides the advantages of good adhesion and good grain growth and orientation that are achieved with copper deposited by PVD, and also provides the good step coverage as achieved with copper deposited by CVD.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: May 4, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Chantal Arena-Foster, Robert F. Foster, Joseph T. Hillman, Thomas J. Licata, Tugrul Yasar
  • Patent number: 6716365
    Abstract: A wafer protected by a protective film on a first surface is mounted on a base member. An etching bath cylinder, to which a gasket for sealing the periphery of the wafer on a second surface that is opposite to the first surface is attached, is placed on the wafer. An etching chamber is formed by vacuum chucking with a vacuum chuck cylinder in an etching pot. Nitrogen gas is supplied from a high pressure gas supply source to a hermetic room, which is formed by the base member and the wafer, while being regulated by a pressure regulator. The pressure regulator includes a water reservoir, a decompressing room having an orifice, a first balance tube, and a second balance tube. The wafer is etched while a pressure higher than that applied to the second surface from an etchant is put on the protective film by the nitrogen gas.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: April 6, 2004
    Assignee: Denso Corporation
    Inventors: Atusi Sakaida, Toshihisa Taniguchi
  • Patent number: 6709531
    Abstract: In this disclosure, air flow is formed above chemical liquid film and a move of the chemical liquid is generated by making the air flow into a contact with the surface of chemical liquid. Further, a negative pressure is generated in a space between a processing object substrate and a plate by rotating the plate. Consequently, uniformity of processing of chemical liquid is improved, so that liquid removing step can be carried out effectively. As a result, yield rate of chemical liquid treatment can be improved.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Riichiro Takahashi, Tatsuhiko Ema, Katsuya Okamura
  • Patent number: 6699400
    Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: March 2, 2004
    Inventors: Arne W. Ballantine, Scott A. Estes, Emily E. Fisch, Gary Milo, Ronald A. Warren
  • Patent number: 6686297
    Abstract: A method of manufacturing an electronic device, in particular but not exclusively a semiconductor device, in which method a substrate (2) is placed inside a process chamber (1) and a surface (3) of the substrate (2) is subjected to an ozone treatment comprising the steps of: providing a liquid onto the surface (3) of the substrate (2) via first supply means, introducing a solution comprising a liquid carrier solvent and ozone gas into the process chamber (1) via second supply means, without bringing about direct contact between the solution and the surface (3) of the substrate (2).
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: February 3, 2004
    Inventors: Georg Gogg, Dirk Maarten Knotter, Charlene Reaux, Steve Nelson
  • Patent number: 6646348
    Abstract: Polishing compositions comprising at least one soluble silane compound and at least one abrasive that are useful for polishing substrate surface features.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: November 11, 2003
    Assignee: Cabot Microelectronics Corporation
    Inventors: Steven K. Grumbine, Shumin Wang
  • Patent number: 6627558
    Abstract: A semiconductor processing apparatus (10) is disclosed which includes a process chamber (12) and at least one substrate support (18) disposed within the process chamber (12) operable to support a substrate wafer (20). The semiconductor processing apparatus includes at least one showerhead assembly (14) disposed within the process chamber (12) facing the substrate support (18) and has a showerhead plate (16). The showerhead plate (16) has a plurality of passageways (17) extending therethrough for directing process fluid toward a substrate wafer (20) disposed on the substrate support (18). A blocking assembly (21) is disposed within the process chamber (12), the blocking assembly has an active position (32) between the showerhead assembly (14) and the substrate support (18) to restrict the flow of process fluid between the showerhead assembly (14) and the substrate support (18).
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: September 30, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: David Jay Rose
  • Patent number: 6624087
    Abstract: An etchant for patterning indium tin oxide, wherein the etchant is a mixed solution of HCl, CH3COOH, and water, and a method of fabricating a liquid crystal display device are disclosed in the present invention. The method includes forming a gate electrode on a substrate, forming a gate insulating layer and an amorphous silicon layer on the gate electrode including the substrate, forming an active area by patterning the amorphous silicon layer, forming a source electrode and a drain electrode on the active area, forming a passivation layer on the source electrode and the drain electrode and the gate insulating layer, forming a contact hole exposing a part of the drain electrode, forming an indium tin oxide layer on the passivation layer, and forming an indium tin oxide electrode by selectively etching the indium tin oxide layer using a mixed solution of HCl, CH3COOH, and water as an etchant.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: September 23, 2003
    Assignee: LG. Philips Co., Ltd.
    Inventors: Byung Tae Roh, You Shin Ahn
  • Patent number: 6620738
    Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 16, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Hidetoshi Ishida, Atsushi Noma, Daisuke Ueda
  • Patent number: 6589882
    Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: July 8, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Paul A. Morgan
  • Patent number: 6579382
    Abstract: In this disclosure, air flow is formed above chemical liquid film and a move of the chemical liquid is generated by making the air flow into a contact with the surface of chemical liquid. Further, a negative pressure is generated in a space between a processing object substrate and a plate by rotating the plate. Consequently, uniformity of processing of chemical liquid is improved, so that liquid removing step can be carried out effectively. As a result, yield rate of chemical liquid treatment can be improved.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: June 17, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichi Ito
  • Patent number: 6566275
    Abstract: A spinner apparatus for manufacturing a photomask, performing a developing process for forming a resist pattern on a specific substrate, and performing an etching process in which a resist pattern is used as an etching mask are provided. A plurality of supply nozzles for supplying a developing solution or an etching solution are provided above the substrate on which processes will be performed and processing conditions such as the temperature and flux of the chemicals supplied from each supply nozzle are independently controlled. Accordingly, it is possible to control the deviation of the critical dimensions of the device.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 20, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-yong Moon
  • Patent number: 6566268
    Abstract: A method of planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is described. The method includes the step of positioning a fluid flow surface relative to the wafer surface so that (i) a space is defined between the wafer surface and the fluid flow surface, and (ii) the elevated portion of the semiconductor wafer is positioned in the space. The method also includes the step of advancing a fluid within the space so that the fluid contacts and erodes the elevated portion of the semiconductor wafer. An associated apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is also described.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: May 20, 2003
    Assignee: LSI Logic Corporation
    Inventor: John Gregory
  • Publication number: 20030073310
    Abstract: A non-contact apparatus and method for removing a metal layer from a substrate are provided. The apparatus includes a rotatable anode substrate support member configured to support a substrate in a face-up position and to electrically contact the substrate positioned thereon. A pivotally mounted cathode fluid dispensing nozzle assembly positioned above the anode substrate support member is also provided. A power supply in electrical communication with the anode substrate support member and the cathode fluid dispensing nozzle is provided, and a system controller configured to regulate at least one of a rate of rotation of the anode substrate support member, a radial position of the cathode fluid dispensing nozzle, and an output power of the power supply is provided. The method provides for the removal of a metal layer from a substrate by rotating the substrate in a face up position on a rotatable substrate support member.
    Type: Application
    Filed: October 16, 2001
    Publication date: April 17, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Donald J.K. Olgado, Joseph J. Stevens, Alexander Lerner
  • Patent number: 6528425
    Abstract: A substrate with striped ridge patterns formed on the surface thereof is transported along a transport path. A relationship is determined between the direction of the striped ridge patterns on the substrate surface and the direction of jetting out fluid to the substrate surface. The fluid is jetted out and blown to the substrate surface along the direction satisfying the determined relationship to process the surface of the substrate. It is possible to reliably perform a surface process of each substrate irrespective of different directions of striped ridge patterns on substrate surfaces.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Masahiro Uraguchi, Mitsugu Uemura, Ryuji Maeda
  • Patent number: 6495472
    Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and the cap layer are then etched to partially expose the conductor structure. The etching residues are removed with an amine-containing solution and the amine-containing solution is removed with an intermediate solvent to avoid erosion of the exposed conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can protect the conductor structure from erosion.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: December 17, 2002
    Assignee: United Microelectronics Corps.
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Patent number: 6489251
    Abstract: The present invention discloses a method of forming a slope lateral structure. In this invention, the silicon nitride and the silicon hydroxide with different etching rates are used. Thus, when the silicon nitride is etching, the top and laterals portion of the silicon hydroxide is suffering the slight etching. So that, when the silicon nitride is etched completely, a slope lateral silicon hydroxide is formed, because of the different etching time on the top and the bottom portion of the silicon hydroxide. Using the present invention, the conventional NROM process problem, which the wordlines are connected by the residue on the laterals of the protective layer after etching process can be solved.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: December 3, 2002
    Assignee: Macronix International Co., Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 6482751
    Abstract: A titanium dioxide layer serving as a mask used in a manufacturing process of integrated circuit and its removed method are disclosed. The method includes the steps of forming a titanium dioxide layer on the integrated circuit device to serve as a mask, and using an etchant to selectively remove the titanium dioxide layer. The titanium dioxide layer is formed by the steps of providing a titanium-containing material, adding an acid substance to the titanium-containing material to form a mixture, and exposing the integrated circuit device to the mixture to form the titanium dioxide layer thereon.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: November 19, 2002
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Kwei Lee, Hsin-Chih Liao
  • Publication number: 20020142584
    Abstract: Cleaning solutions and methods for removing residuals from the surface of an integrated circuit device. Such solutions and methods find particular application in the fabrication of a dual damascene structure following removal of excess portions of a silver-containing metal layer from a device surface. The cleaning solutions and methods facilitate removal of particulate residuals as well as unremoved portions of the metal layer in a single cleaning process. The cleaning solutions are dilute aqueous solutions containing hydrogen peroxide and at least one acidic component and are substantially free of particulate material. Acidic components include carboxylic acids and their salts.
    Type: Application
    Filed: March 27, 2001
    Publication date: October 3, 2002
    Applicant: Micron Technology, Inc.
    Inventor: Michael T. Andreas
  • Patent number: 6458712
    Abstract: A process is described for recycling test wafers used for quality control or damaged wafers used in the context of chip production by regenerative removal of the previously applied layers. The method is based on the object of developing a cost-effective, environmentally friendly and time-saving regeneration method. The object is achieved by removing the applied layers by wet blasting using a specific blast material.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: October 1, 2002
    Assignee: Infineon Technologies AG
    Inventors: Hans Krämer, Matthias Taubert, Gernot Loibnegger
  • Patent number: 6440871
    Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: August 27, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Terry L. Gilton
  • Publication number: 20020106904
    Abstract: Provided is an etching method of accurately forming a fine structure in a plastic substrate. A surface reformed layer insoluble by an etchant, for example, limonene is formed on a surface of a substrate soluble by the etchant by ion implantation treatment; an opening is formed in the surface reformed layer by dry etching treatment; and the substrate is subjected to wet etching treatment by dipping the substrate in the etchant. A peripheral portion, around the opening, of the surface reformed layer functions as a mask to allow the wet etching to anisotropically proceed, and a portion, on the side opposed to the opening, of the surface reformed layer functions as an end point of the wet etching. As a result, a recess having a uniform inner diameter in the depth direction can be formed in the substrate.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 8, 2002
    Inventors: Minehiro Tonosaki, Koji Kitagawa
  • Patent number: 6413355
    Abstract: A cleaning apparatus and a cleaning method for cleaning an object are provided. In the cleaning apparatus, a drying chamber 42 and a cleaning bath 41 are separated from each other up and down, respectively. Thus, a space in the drying chamber 42 can be insulated from a space of the cleaning bath 41 through a slide door 72. In the cleaning method, a drying process and a cleaning process are carried out separately on condition that the space in the drying chamber 42 is insulated from the space of the cleaning bath 41 through the slide door 72. Consequently, there is no possibility that, during the drying process, the object is subjected to a bad influence from a chemical treatment.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: July 2, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Yuji Kamikawa, Satoshi Nakashima, Kinya Ueno
  • Publication number: 20020072238
    Abstract: A fixed abrasive chemical polishing method uses an aqueous solution that has a variable pH. During polishing the pH of the aqueous solution is changed so that the polishing process can be more precisely controlled. The removal rate and removal selectivity between oxide and nitride can be controlled by varying the pH of the aqueous solution.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 13, 2002
    Inventors: Cheng-An Peng, Jiun-Fang Wang
  • Patent number: 6403496
    Abstract: A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: June 11, 2002
    Assignee: Windbond Electronics Corporation
    Inventor: Yu-Chung Tien
  • Patent number: 6399517
    Abstract: An etching method and an etching apparatus are provided. Silicon (Si) from surfaces semiconductor wafers W dissolves into an etching liquid E stored in a process bath 10. On detection of the concentration of silicon by a concentration sensor 50, the etching liquid E in the process bath 10 is discharged while leaving a part of the etching liquid when the Si concentration in the etching liquid E reaches a designated concentration. After that, a new etching liquid of substantially equal to an amount of the discharged etching liquid E is supplied into the process bath 10 and added to the etching liquid remaining in the bath 10. Consequently, it is possible to restrict the etching rate just after the exchange of etching liquid from rising excessively.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: June 4, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Yokomizo, Tom Williams
  • Patent number: 6399480
    Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: June 4, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Darin A. Chan, David K. Foote, Fei Wang, Minh Van Ngo
  • Patent number: 6395646
    Abstract: A machine for etching the edge of a wafer comprising a rotating holding plate having a work platform, the work platform having a first fillister for spraying gas to maintain a certain distance between the work platform and the wafer, a second fillister set around the periphery of the first fillister for reducing pressure of the sprayed gas at the edge of the wafer, and a plurality of holding pins; a vacuum manipulator; and an etching solution leading apparatus.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: May 28, 2002
    Assignee: Winbond Electronics Corp.
    Inventor: Yueh-liang Liu
  • Patent number: 6387821
    Abstract: In a method of manufacturing a semiconductor device having a multi-layer interconnection, after a via hole has been formed, the inside of the via hole is cleaned using a cleaning solution containing a complexing agent capable of forming a complex with contaminants of copper type metals.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: May 14, 2002
    Assignee: NEC Corporation
    Inventor: Hidemitsu Aoki
  • Patent number: 6387822
    Abstract: A method and apparatus for resist strip. Wafers (108) with a patterned resist formed thereon are placed in a carrier (104) in a process chamber (102). An ozonated deionized water mist (120) is sprayed on the surface of wafer (108). The ozonated deionized water mist (120) strips the resist and removes the resist residue without the use of hazardous chemicals. The ozonated deionized water mist (120) may be formed in an atomizer that mixes deionized water (116) with ozone (118). The ozonated deionized water mist (120) is then sprayed onto the wafers (108) while the wafers are being rotated.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: May 14, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Neal T. Murphy, Claire Ching-Shan Jung, Danny F. Mathews
  • Patent number: 6380099
    Abstract: A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: April 30, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Kazutaka Yanagita
  • Patent number: 6376390
    Abstract: Methods and apparatuses for removing material from discrete areas on a semiconductor wafer are described. In one implementation, an etchant applicator is provided having a tip portion. Liquid etchant material is suspended proximate the tip portion and the etchant applicator is moved, together with the suspended liquid, sufficiently close to a discrete area on a wafer to transfer liquid etchant onto the discrete area. In various embodiments the tip portion can comprise fluid permeable materials, fluid-absorbent materials, and/or wick assemblies. An exhaust outlet can be provided operably proximate the tip portion for removing material from over the wafer. The tip portion can be moved to touch the discrete area.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Dow, Richard H. Lane
  • Patent number: 6361708
    Abstract: A method and an apparatus for polishing a metal film formed on a semiconductor device are disclosed. A semiconductor wafer is immersed in an oxidizing solution before it is polished. As a result, the undesirable part of a W film deposited on the circumferential edge of the wafer is removed by etching.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: March 26, 2002
    Assignee: NEC Corporation
    Inventors: Akira Kubo, Mieko Suzuki
  • Patent number: 6358847
    Abstract: A method is described comprising removing an oxide from a surface and then commencing application of a passivation layer to the surface within 5 seconds of the oxide removal. The surface may be a copper surface which may further comprise a bonding pad surface. Removing the oxide may further comprise applying a solution comprising citric acid or hydrochloric acid. Applying the passivation layer may further comprise applying a solution comprising a member of the azole family where the azole family member may further comprise BTA. The method may also further comprise completely applying the passivation layer 35 seconds after commencing its application.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: March 19, 2002
    Assignee: Lam Research Corporation
    Inventors: Hugh Li, Diane J. Hymes
  • Patent number: 6358861
    Abstract: A method of manufacturing a silicon device with a single crystal structure, including forming etching start patterns on a surface of a silicon substrate; etching the silicon substrate by applying a voltage to the silicon substrate while the silicon substrate is immersed in a solution containing fluorine ions, with the silicon substrate used a positive electrode, to form narrow etched portions that extend into the substrate from the etching start patterns; and accelerating etching of the silicon substrate by increasing current flowing through the silicon substrate after the narrow etched portions have reached a predetermined depth, so that neighboring etched portions are in communication with each other below the narrow etched portions and a free standing structure including part of the silicon substrate is formed, and a hollow portion is formed below the free standing structure.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: March 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Ohji, Kazuhiko Tsutsumi, Patrick J. French
  • Publication number: 20020016082
    Abstract: The present invention is related to a method and apparatus for liquid treating and drying a substrate, such as a semiconductor wafer, the method comprising the step of immersing a substrate or a batch of substrates in a tank filled with a liquid, and removing the substrate(s) through an opening so that a flow of the liquid takes place through the opening during removal of the substrate. Simultaneously with the removal, a reduction of the surface tension of the liquid is caused to take place near the intersection line between the liquid and the substrate. For acquiring such a tensio-active effect, a uniform flow of a gas or vapor is used, or/and a local application of heat. The invention is equally related to an apparatus for performing the method of the invention.
    Type: Application
    Filed: June 27, 2001
    Publication date: February 7, 2002
    Inventors: Paul Mertens, Marc Meuris
  • Publication number: 20020013065
    Abstract: A holder driving mechanism holds a wafer holder with gripping portions, and swings it within a wafer processing bath. When the peripheral portion of a wafer comes into contact with the distal end portion of a swing support member, the wafer rotates and vertically moves in the wafer holder. The wafer can be efficiently swung, and processing can be made uniform. By supplying ultrasonic waves from an ultrasonic bath, the processing rate can be increased.
    Type: Application
    Filed: August 20, 2001
    Publication date: January 31, 2002
    Inventors: Kazutaka Yanagita, Kiyofumi Sakaguchi
  • Patent number: 6333275
    Abstract: A chemical etching system provides a mixture of sulfuric acid and hydrogen peroxide and serves as the etchant for removing residual copper from an edge bevel region of a semiconductor wafer. The etching system includes a dilution module where concentrated sulfuric acid and concentrated hydrogen peroxide are diluted to the appropriate concentrations and then stored. To reduce the likelihood that oxygen bubbles (from hydrogen peroxide decomposition) will appear in the etchant solution, stored sulfuric acid and hydrogen peroxide are mixed immediately prior to use. In this manner, the dissolved oxygen concentration in the hydrogen peroxide decreases well below the saturation level.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: December 25, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John B. Alexy, Jinbin Feng
  • Publication number: 20010044216
    Abstract: A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.
    Type: Application
    Filed: December 15, 1998
    Publication date: November 22, 2001
    Inventors: KIYOFUMI SAKAGUCHI, KAZUTAKA YANAGITA
  • Patent number: 6319846
    Abstract: A method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor wafer is disclosed. In the method, a semiconductor wafer that has on a top surface a multiplicity of solder bodies electrically connected to a multiplicity of bond pads through a multiplicity of copper wetting layers is first provided. When the multiplicity of solder bodies is found out of specification or must be removed for any other quality reasons, the semiconductor wafer is exposed to an etchant that has an etch rate toward the copper wetting layer at least 5 times the etch rate toward a metal that forms the multiplicity of bond pads. The semiconductor wafer may be removed from the etchant when the multiplicity of copper wetting layers is substantially dissolved such that the multiplicity of solder bodies is separated from the multiplicity of bond pads. The multiplicity of solder bodies may be either solder bumps or solder balls.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: November 20, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Kuo-Wei Lin, James Chen, Eugene Chu, Alex Fahn, Chiou-Shian Peng, Gilbert Fane, Kenneth Lin
  • Patent number: 6313043
    Abstract: A method of manufacturing a field emission element including the steps of: depositing an emitter electrode film on the surface of an emitter portion forming recess formed on a substrate; forming an emitter portion of an emitter electrode by removing the emitter electrode film deposited on the bottom of the emitter portion forming recess; depositing a sacrificial film on the surface of the emitter electrode and on the bottom of the emitter portion forming recess, and thereafter depositing a second gate electrode film on the surface of the sacrificial film. With this manufacture method, field emission elements having small unevenness in vertical positions of emitter and gate electrodes can be formed.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: November 6, 2001
    Assignee: Yamaha Corporation
    Inventor: Atsuo Hattori
  • Patent number: 6303514
    Abstract: The invention relates to an aqueous phosphoric acid etch bath composition with a readily soluble silicon containing composition. The baths are used in the etching step of composite semiconductor device manufacturing.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: October 16, 2001
    Assignee: Ashland Inc.
    Inventors: Thomas B. Hackett, Zach Hatcher, III
  • Patent number: 6300156
    Abstract: A process for fabricating a MEMS device is disclosed. The device has at least one hinged element. The MEMS device including the hinged element is delineated and defined on a semiconductor substrate. The substrate is placed device side down in a chamber. The MEMS device is then exposed to a release expedient for sufficient amount of time for the release expedient to dissolve a sacrificial material connecting the element to the substrate. Upon the dissolution of the sacrificial material, the element is released from the substrate and pivots away from the surface.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: October 9, 2001
    Assignees: Agere Systems Optoelectronics Guardian Corp., Lucent Technologies Inc.
    Inventors: Robert LeRoy Decker, Valerie Jeanne Kuck, Mark Anthony Paczkowski, Peter Gerald Simpkins
  • Patent number: 6294478
    Abstract: SOI substrates are fabricated with sufficient quality and with good reproducibility. At the same time, conservation of resources and reduction of cost are realized by reuse of the wafer and the like. Carried out to achieve the above are a step of bonding a principal surface of a first substrate to a principal surface of a second substrate, the first substrate being Si substrate in which at least one layer of non-porous thin film is formed through a porous Si layer, a step of exposing the porous Si layer in a side surface of a bonding substrate comprised of the first substrate and the second substrate, a step of dividing the porous Si layer by oxidizing the bonding substrate, and a step of removing the porous Si and oxidized porous Si layer on the second substrate separated by the division of the porous Si layer.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: September 25, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara
  • Patent number: 6281130
    Abstract: There is provided a method of applying a developing liquid onto a semiconductor wafer substrate having a UTR film thereon so as to minimize unexposed film thickness loss during development. This is achieved by applying the developing liquid from a developer nozzle which is off-set from the central position of the wafer substrate. The developing liquid is allowed to contact the wafer substrate for less than 10 seconds. As a result, there is overcome the problems of unexposed film thickness loss and critical dimension variations due to the developer nozzle effects.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: August 28, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Christopher L. Pike