Abstract: A layered heterostructure, comprising alternating layers of different semiconductors, wherein one of the atom species of one of the semiconductors has a faster diffusion rate along an oxidizing interface than an atom species of the other semiconductor at an oxidizing temperature, can be used to fabricate embedded nanostructures with arbitrary shape. The result of the oxidation will be an embedded nanostructure comprising the semiconductor having slower diffusing atom species surrounded by the semiconductor having the higher diffusing atom species. The method enables the fabrication of low- and multi-dimensional quantum-scale embedded nanostructures, such as quantum dots (QDs), toroids, and ellipsoids.

Abstract: Provided is a substrate processing method for processing a substrate. The substrate processing method includes a step of processing the substrate with a phosphoric acid liquid, a step of processing the substrate with a rinsing liquid, and a step of processing the substrate with a chemical liquid containing ammonia. After the substrate is processed with the rinsing liquid, the step of processing the substrate with a chemical liquid removes a portion of thickness of a film in a depth direction of a phosphorus diffusion region from the phosphorus diffusion region formed in the substrate when the substrate is processed with the phosphoric acid liquid.

Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.

Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.

Abstract: Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.

Abstract: Semiconductor device and method for forming a semiconductor device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layer of the bottom pad stack is removed by a batch process. Trench isolation regions are formed in the substrate.

Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.

Abstract: An etchant composition includes ammonium persulfate (((NH4)2)S2O8), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: Methods and systems for removing materials from microfeature workpieces are disclosed. A method in accordance with one embodiment of the invention includes providing a microfeature workpiece having a substrate material and a conductive material that includes a refractory metal (e.g., tantalum, tantalum nitride, titanium, and/or titanium nitride). First and second electrodes are positioned in electrical communication with the conductive material via a generally organic and/or non-aqueous electrolytic medium. At least one of the electrodes is spaced apart from the workpiece. At least a portion of the conductive material is removed by passing an electrical current along an electrical path that includes the first electrode, the electrolytic medium, and the second electrode. Electrolytically removing the conductive material can reduce the downforce applied to the workpiece.

Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

Abstract: Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate; forming a first etching layer on the substrate; forming a connecting layer on the first etching layer; forming a second etching layer on the connecting layer; forming a lighting structure on the second etching layer; and etching the first etching layer, the connecting layer, the second etching layer and the lighting structure, wherein an etching rate of the first etching layer and the second etching layer is lager than that of the connecting layer and the lighting structure, thereby to form the connecting layer and the lighting structure each with an inverted frustum-shaped structure.

Abstract: Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods.

Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Abstract: A method of manufacturing a Bulk Acoustic Wave device by providing an active layer formed of an electro-mechanical transducer material, providing a first electrode on the active layer, defining a first electrode portion of the device, whereby a remaining portion of the device is defined around the first electrode, providing a stop-layer on the first electrode, depositing a first dielectric layer on the resultant structure, and planarizing the first dielectric layer until the stop-layer on the first electrode is exposed.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate with a first block layer dividing an upper surface of the substrate into a plurality of epitaxial regions; forming a first semiconductor layer on the epitaxial regions; forming a second block layer partly covering the first semiconductor layer; forming a lighting structure on an uncovered portion of the first semiconductor layer; removing the first and the second block layers thereby defining clearances at the bottom surfaces of the first semiconductor layer and the lighting structure; and permeating etching solution into the first and second clearances to etch the first semiconductor layer and the lighting structure, thereby to form each of the first semiconductor layer and the lighting structure with an inverted frustum-shaped structure.

Abstract: A method of manufacturing a vertical GaN-based LED includes forming a nitride-based buffer layer on a silicon substrate; sequentially forming a p-type GaN layer, an active layer, and an n-type GaN layer on the nitride-based buffer layer; forming an n-electrode on the n-type GaN layer; forming a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed.

Abstract: In a liquid processing apparatus configured to remove, from a substrate including a first film and a second film formed above the first film, the first film and the second film, a first chemical-liquid supply part supplies, to a substrate W, a first liquid for dissolving the first film, a second chemical-liquid supply part supplies a second chemical liquid for weakening the second film, and a fluid supply part serving also as an impact giving part gives a physical impact to the second film so as to break the second film and supplies a fluid for washing away debris of the broken second film. A control device controls the respective parts such that, after the second liquid has been supplied and then the fluid has been supplied from the fluid supply part, the first chemical liquid is supplied.

Abstract: A method for fabricating an LED chip is provided. Firstly, a SiO2 pattern layer is formed on a top surface of a substrate. Then, lighting structures are grown on a portion of the top surface of substrate without the SiO2 pattern layer thereon. Thereafter, the SiO2 pattern layer is removed by wet etching to form spaces between bottoms of the lighting structures and substrate. An etching solution is used to permeate into the spaces and etch the lighting structures from the bottoms thereof, whereby the lighting structures each with a trapezoid shape is formed. Sidewalls of each of the lighting structures are inclined inwardly along a top-to-bottom direction.

Abstract: A semiconductor device is formed by implanting recess markers in a material during deposition and using the recess markers during etching of the material for precise in-situ removal rate definition and removal homogeneity-over-radius definition. An embodiment includes depositing a layer of material on a substrate, implanting first and second dopants in the material at first and second predetermined times during deposition of the material, etching the material, detecting the depths of the first and second dopants during etching, calculating the removal rate of the material in situ from the depths of the first and second dopants, and determining from the removal rate a stop position for etching.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a sacrificial layer on the second material layer; forming a patterned resist layer on the sacrificial layer; applying a first wet etching process using a first etch solution to the substrate to pattern the sacrificial layer using the patterned resist layer as a mask, resulting in a patterned sacrificial layer; applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) solution to the substrate to pattern the second material layer, resulting in a patterned second material layer; applying a second wet etching process using a second etch solution to the substrate to pattern the first material layer; and applying a third wet etching process using a third etch solution to remove the patterned sacrificial layer.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN.

Abstract: Methods are provided for manufacturing optical display devices which remove an etch resist and residual post-etch metal in a single step. These methods are particularly useful in the manufacture of LCDs.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of pillar structures over a substrate, forming gate electrodes over sidewalls of the pillar structures, forming a sacrificial layer buried between the pillar structures, etching the sacrificial layer and the substrate to form trenches in the substrate, forming first inter-layer insulation patterns buried over the trenches and removing the remaining sacrificial layer at substantially the same time, and forming second inter-layer insulation patterns over the first inter-layer insulation patterns and buried between the pillar structures.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.

Abstract: Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.

Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.

Abstract: A nanospring is formed by first forming a stack of alternating layers of materials which have different susceptibilities to a selective etch solution. The stack is formed over a substrate and is subsequently etched with a substantially non-isotropic etch to create a via having substantially straight sidewalls. The sidewalls of the via are exposed to the selective etch solution, thereby creating irregular sidewalls of the via. A metal film is conformally deposited within the via, and, after excess metal is removed, the stack of alternating layers of materials is etched to expose remaining portions of the conformably deposited film, which comprise the nanospring.

Abstract: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer of quantum dot material, and optionally, one or more layers of reflective Bragg reflectors. A mask is deposited over a top layer and reactive ion-beam etching applied to define a plurality of heterostructures. The release layer can be dissolved releasing the heterostructures from the wafer. Some exemplary applications of these methods include formation of fluorophore materials and high efficiency photon emitters, such as quantum dot VCSEL devices. Other applications include fabrication of other optoelectronic devices, such as photodetectors.

Abstract: An electrical resistance is produced in a semiconductor device by first providing a semiconductor resistor structure that includes a semiconductor resistor having formed thereon a native oxide layer. A portion of the native oxide layer that overlies a corresponding top surface portion of the semiconductor resistor is removed, in order to expose the top surface portion of the semiconductor resistor. Metal is deposited on the exposed top surface portion of the semiconductor resistor. A chemical reaction is effectuated in order to reduce the likelihood of metal reacting with the underlying silicon on any portion of the semiconductor resistor other than the top surface portion thereof. The chemical reaction can be an oxidation reaction that produces on the semiconductor resistor structure an oxide layer other than the native oxide layer and substantially thicker than the native oxide layer.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A multi-layer fabrication method for making three-dimensional structures is provided. In one embodiment, the formation of a multi-layer three-dimensional structure comprises: 1) fabricating a plurality of layers with each layer comprising at least two materials; 2) aligning the layers; 3) attaching the layers together to form a multi-layer structure; and 4) removing at least a portion of at least one of the materials from the multi-layer structure. Fabrication methods for making the required layers are also disclosed.

Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.

Abstract: A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.

Abstract: A novel cleaning method for preventing defects and particles resulting from post tungsten etch back or tungsten chemical mechanical polish is provided. The cleaning method comprises providing a stack structure of a semiconductor device including a tungsten plug in a dielectric layer. The tungsten plug has a top excess portion. A surface of the stack structure is then contacted with a cleaning solution comprising hydrogen peroxide. Next, the surface of the stack structure is contacted with dilute hydrofluoric acid. The cleaning solution and hydrofluoric acid are capable of removing the top excess portion and particles on the surface of the stack structure.

Abstract: A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripheral region. A contact region of the capping layer is etched. A spacer is formed on sidewalls of the capping layer. A contact region of the blocking oxide layer is etched by using the spacer as a mask. The spacer is removed while etching a contact region of the trap nitride layer. A contact region of the tunneling layer is etched.

Abstract: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film, including: etching the insulating film using reactive ion etching to a depth whereat said irregularity does not disappear; and sputter-etching the surface of the amorphous Si.

Abstract: In forming a narrow pattern, it is difficult to form a lift-off resist pattern with an overhang shape. Accordingly, it results in a phenomenon in which the angle at the end of the GMR layer is reduced to 45° or less. It is necessary to provide a lift-off resist pattern that forms the end of the GMR film to be at an angle of as abrupt as 45° or more and ensures lift-off.

Abstract: The present invention discloses a method for fabricating a light emitting diode element, which incorporates an epitaxial process with an etching process to etch LED epitaxial layers bottom up and form side-protrudent structures, whereby the LED epitaxial layers have non-rectangular inclines, which can solve the problem of total reflection and promote light-extraction efficiency. Further, the method of the present invention has a simple fabrication process, which can benefit mass production and lower cost.

Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.

Abstract: A method for forming a pattern of a semiconductor device comprises forming a spacer with an oxide film in a SPT process, and removing the spacer formed to have a horn shape before etching an underlying layer, so that the horn shape is transcribed in a lower portion, thereby facilitating control of critical dimension in etching the underlying layer so as to improve a characteristic of the device. A method for forming a pattern of a semiconductor device of the present invention comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial pattern to remain the spacer; etching the hard mask layer with the spacer as a mask to form a hard mask pattern; removing the spacer; and etching the underlying layer with the hard mask pattern as a mask.

Abstract: A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has a full-width half-maximum (FWHM) thickness value of less than approximately 70 nanometers. A strained silicon layer is formed over the relaxed silicon-germanium layer and is configured to act as quantum well device.

Abstract: A method for applying a heat insulation layer (11, 12, 13) or a metallic protective layer to a thermally stressed component (200) having a basic material (10) in order to eliminate local damage (14) or an untreated place in the coating, includes, in a first step, pretreating the local damage (14) or untreated place, and, in a second step, applying layers (17, 18) necessary for eliminating the local damage (14) or untreated place. A markedly improved lifetime of the processed component can be achieved in that, within the first step, the edge regions (15) of the layers (11, 12, 13) ending at the local damage (14) or untreated place are processed so that they form uniformly sloped and terrace-shaped edge regions (16). Furthermore, a precharacterization of the entire coated region of the operationally stressed component or critical places by FSECT makes it possible to reduce the risk in terms of otherwise overlooked layer regions, the remaining lifetime of which would not persist for the following operating time.

Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Abstract: A method of manufacturing a field emission device (FED), which reduces the number of photomask patterning processes and improves the manufacturing yield of the FED, is provided.

Abstract: A process for etching a thick aluminum contact layer of a semiconductor wafer comprises the formation of a wet etch photoresist mask and the opening of a window in the mask, followed by a wet etch of a first portion of the thickness of the contact layer exposed by the window and the inherent under cutting of the contact layer under the mask window. A dry etch is next carried out, using the same window as a mask, to cut the remaining web of the contact layer under the window. An etch stop layer of Ti or TiN can be formed within the body of the contact layer to define the depth of the initial wet etch into the contact layer.